Jeff
|
65eb821710
|
Well, apparently the PDP-10 MUL instruction really DOES store the high-order word first, and it only stores the low-order word if the destination is an accumulator (weird)
|
2017-03-07 14:09:24 -08:00 |
|
Jeff
|
7e207db2a1
|
Added PDP-10 JSP and JFCL operations (which seem to be the simplest means of getting and setting the processor flags)
|
2017-03-07 13:44:43 -08:00 |
|
Jeff
|
affaa1075c
|
Finished the PDP-10 Move Magnitude opcodes, along with the Push Down and Pop Up opcodes (uncovering some SIMH weirdness along the way)
|
2017-03-02 16:38:00 -08:00 |
|
Jeff
|
202374dd09
|
Added the PDP-10's four arithmetic flags along with a negate() function -- the first of our functions that actually needs to set those flags
|
2017-03-01 17:23:54 -08:00 |
|
Jeff
|
e870fd6eec
|
Fixed the accumulator update logic in all the PDP-10 half-word self-mode instructions, and started work on EXCH, BLT, and MOVE instructions (the BLT is a real odd-ball, and SIMH does some very strange things with the accumulator used by BLT, which we do NOT attempt to replicate; the strangeness is most noticeable when the accumulator is part of the range being transferred)
|
2017-03-01 16:00:48 -08:00 |
|
Jeff Parsons
|
f0bfe81cc9
|
Added more half-word opcode tests
|
2017-02-28 15:46:47 -08:00 |
|