Jeff
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65eb821710
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Well, apparently the PDP-10 MUL instruction really DOES store the high-order word first, and it only stores the low-order word if the destination is an accumulator (weird)
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2017-03-07 14:09:24 -08:00 |
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Jeff
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7e207db2a1
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Added PDP-10 JSP and JFCL operations (which seem to be the simplest means of getting and setting the processor flags)
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2017-03-07 13:44:43 -08:00 |
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Jeff
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25aa95cec8
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First cut at PDP-10 byte instructions
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2017-03-02 23:10:24 -08:00 |
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Jeff
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affaa1075c
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Finished the PDP-10 Move Magnitude opcodes, along with the Push Down and Pop Up opcodes (uncovering some SIMH weirdness along the way)
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2017-03-02 16:38:00 -08:00 |
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Jeff
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84f8cece67
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All PDP-10 MOVN (Move Negative) opcodes implemented
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2017-03-02 10:19:37 -08:00 |
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Jeff
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e870fd6eec
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Fixed the accumulator update logic in all the PDP-10 half-word self-mode instructions, and started work on EXCH, BLT, and MOVE instructions (the BLT is a real odd-ball, and SIMH does some very strange things with the accumulator used by BLT, which we do NOT attempt to replicate; the strangeness is most noticeable when the accumulator is part of the range being transferred)
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2017-03-01 16:00:48 -08:00 |
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Jeff Parsons
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f0bfe81cc9
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Added more half-word opcode tests
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2017-02-28 15:46:47 -08:00 |
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Jeff Parsons
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8863f1127c
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Added rudimentary PDP-10 assembler capability to the built-in debugger
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2017-02-27 18:06:08 -08:00 |
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