More 80386 instructions
This commit is contained in:
Jeff Parsons
jeffpar
parent
f098335db9
commit
f9cb8a5bec
15 changed files with 2873 additions and 1673 deletions
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@ -37,11 +37,11 @@ if (typeof module !== 'undefined') {
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}
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/**
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* op=0x0F,0x00 (GRP6 rm)
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* op=0x0F,0x00 (GRP6 mem/reg)
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*
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* @this {X86CPU}
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*/
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X86.opGrp6 = function GRP6()
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X86.opGRP6 = function GRP6()
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{
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var bModRM = this.getIPByte();
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if ((bModRM & 0x38) < 0x10) { // possible reg values: 0x00, 0x08, 0x10, 0x18, 0x20, 0x28, 0x30, 0x38
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@ -51,11 +51,11 @@ X86.opGrp6 = function GRP6()
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};
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/**
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* op=0x0F,0x01 (GRP7 rm)
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* op=0x0F,0x01 (GRP7 mem/reg)
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*
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* @this {X86CPU}
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*/
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X86.opGrp7 = function GRP7()
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X86.opGRP7 = function GRP7()
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{
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var bModRM = this.getIPByte();
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if (!(bModRM & 0x10)) {
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@ -67,7 +67,7 @@ X86.opGrp7 = function GRP7()
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/**
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* opLAR()
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*
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* op=0x0F,0x02 (LAR reg,rm)
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* op=0x0F,0x02 (LAR reg,mem/reg)
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*
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* @this {X86CPU}
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*/
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@ -79,7 +79,7 @@ X86.opLAR = function LAR()
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/**
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* opLSL()
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*
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* op=0x0F,0x03 (LSL reg,rm)
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* op=0x0F,0x03 (LSL reg,mem/reg)
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*
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* @this {X86CPU}
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*/
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@ -311,6 +311,486 @@ X86.opMOVcrr = function MOVcrr()
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}
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};
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/**
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* opJOw()
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*
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* op=0x0F,0x80 (JO rel16/rel32)
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*
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* @this {X86CPU}
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*/
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X86.opJOw = function JOw()
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{
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var disp = this.getIPDispWord();
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if (this.getOF()) {
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this.setIP(this.getIP() + disp);
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpC;
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return;
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}
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpCFall;
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};
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/**
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* opJNOw()
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*
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* op=0x0F,0x81 (JNO rel16/rel32)
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*
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* @this {X86CPU}
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*/
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X86.opJNOw = function JNOw()
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{
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var disp = this.getIPDispWord();
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if (!this.getOF()) {
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this.setIP(this.getIP() + disp);
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpC;
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return;
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}
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpCFall;
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};
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/**
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* opJCw()
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*
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* op=0x0F,0x82 (JC rel16/rel32)
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*
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* @this {X86CPU}
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*/
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X86.opJCw = function JCw()
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{
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var disp = this.getIPDispWord();
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if (this.getCF()) {
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this.setIP(this.getIP() + disp);
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpC;
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return;
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}
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpCFall;
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};
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/**
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* opJNCw()
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*
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* op=0x0F,0x83 (JNC rel16/rel32)
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*
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* @this {X86CPU}
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*/
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X86.opJNCw = function JNCw()
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{
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var disp = this.getIPDispWord();
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if (!this.getCF()) {
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this.setIP(this.getIP() + disp);
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpC;
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return;
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}
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpCFall;
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};
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/**
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* opJZw()
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*
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* op=0x0F,0x84 (JZ rel16/rel32)
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*
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* @this {X86CPU}
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*/
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X86.opJZw = function JZw()
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{
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var disp = this.getIPDispWord();
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if (this.getZF()) {
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this.setIP(this.getIP() + disp);
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpC;
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return;
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}
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpCFall;
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};
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/**
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* opJNZw()
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*
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* op=0x0F,0x85 (JNZ rel16/rel32)
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*
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* @this {X86CPU}
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*/
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X86.opJNZw = function JNZw()
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{
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var disp = this.getIPDispWord();
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if (!this.getZF()) {
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this.setIP(this.getIP() + disp);
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpC;
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return;
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}
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpCFall;
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};
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/**
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* opJBEw()
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*
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* op=0x0F,0x86 (JBE rel16/rel32)
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*
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* @this {X86CPU}
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*/
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X86.opJBEw = function JBEw()
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{
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var disp = this.getIPDispWord();
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if (this.getCF() || this.getZF()) {
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this.setIP(this.getIP() + disp);
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpC;
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return;
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}
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpCFall;
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};
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/**
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* opJNBEw()
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*
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* op=0x0F,0x87 (JNBE rel16/rel32)
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*
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* @this {X86CPU}
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*/
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X86.opJNBEw = function JNBEw()
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{
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var disp = this.getIPDispWord();
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if (!this.getCF() && !this.getZF()) {
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this.setIP(this.getIP() + disp);
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpC;
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return;
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}
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpCFall;
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};
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/**
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* opJSw()
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*
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* op=0x0F,0x88 (JS rel16/rel32)
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*
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* @this {X86CPU}
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*/
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X86.opJSw = function JSw()
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{
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var disp = this.getIPDispWord();
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if (this.getSF()) {
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this.setIP(this.getIP() + disp);
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpC;
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return;
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}
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpCFall;
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};
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/**
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* opJNSw()
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*
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* op=0x0F,0x89 (JNS rel16/rel32)
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*
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* @this {X86CPU}
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*/
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X86.opJNSw = function JNSw()
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{
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var disp = this.getIPDispWord();
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if (!this.getSF()) {
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this.setIP(this.getIP() + disp);
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpC;
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return;
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}
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpCFall;
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};
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/**
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* opJPw()
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*
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* op=0x0F,0x8A (JP rel16/rel32)
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*
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* @this {X86CPU}
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*/
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X86.opJPw = function JPw()
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{
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var disp = this.getIPDispWord();
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if (this.getPF()) {
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this.setIP(this.getIP() + disp);
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpC;
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return;
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}
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpCFall;
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};
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/**
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* opJNPw()
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*
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* op=0x0F,0x8B (JNP rel16/rel32)
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*
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* @this {X86CPU}
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*/
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X86.opJNPw = function JNPw()
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{
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var disp = this.getIPDispWord();
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if (!this.getPF()) {
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this.setIP(this.getIP() + disp);
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpC;
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return;
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}
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpCFall;
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};
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/**
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* opJLw()
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*
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* op=0x0F,0x8C (JL rel16/rel32)
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*
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* @this {X86CPU}
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*/
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X86.opJLw = function JLw()
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{
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var disp = this.getIPDispWord();
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if (!this.getSF() != !this.getOF()) {
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this.setIP(this.getIP() + disp);
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpC;
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return;
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}
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpCFall;
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};
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/**
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* opJNLw()
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*
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* op=0x0F,0x8D (JNL rel16/rel32)
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*
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* @this {X86CPU}
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*/
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X86.opJNLw = function JNLw()
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{
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var disp = this.getIPDispWord();
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if (!this.getSF() == !this.getOF()) {
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this.setIP(this.getIP() + disp);
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpC;
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return;
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}
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpCFall;
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};
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/**
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* opJLEw()
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*
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* op=0x0F,0x8E (JLE rel16/rel32)
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*
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* @this {X86CPU}
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*/
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X86.opJLEw = function JLEw()
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{
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var disp = this.getIPDispWord();
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if (this.getZF() || !this.getSF() != !this.getOF()) {
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this.setIP(this.getIP() + disp);
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpC;
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return;
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}
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpCFall;
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};
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/**
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* opJNLEw()
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*
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* op=0x0F,0x8F (JNLE rel16/rel32)
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*
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* @this {X86CPU}
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*/
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X86.opJNLEw = function JNLEw()
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{
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var disp = this.getIPDispWord();
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if (!this.getZF() && !this.getSF() == !this.getOF()) {
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this.setIP(this.getIP() + disp);
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpC;
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return;
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}
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this.nStepCycles -= this.CYCLES.nOpCyclesJmpCFall;
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};
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/**
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* opSETO()
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*
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* op=0x0F,0x90 (SETO b)
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*
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* @this {X86CPU}
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*/
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X86.opSETO = function SETO()
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{
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X86.fnSETcc.call(this, X86.fnSETO);
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};
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/**
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* opSETNO()
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*
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* op=0x0F,0x91 (SETNO b)
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*
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* @this {X86CPU}
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*/
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X86.opSETNO = function SETNO()
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{
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X86.fnSETcc.call(this, X86.fnSETO);
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};
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/**
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* opSETC()
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*
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* op=0x0F,0x92 (SETC b)
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*
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* @this {X86CPU}
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*/
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X86.opSETC = function SETC()
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{
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X86.fnSETcc.call(this, X86.fnSETC);
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};
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/**
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* opSETNC()
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*
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* op=0x0F,0x93 (SETNC b)
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*
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* @this {X86CPU}
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*/
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X86.opSETNC = function SETNC()
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{
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X86.fnSETcc.call(this, X86.fnSETNC);
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};
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/**
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* opSETZ()
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*
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* op=0x0F,0x94 (SETZ b)
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*
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* @this {X86CPU}
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*/
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X86.opSETZ = function SETZ()
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{
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X86.fnSETcc.call(this, X86.fnSETZ);
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};
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/**
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* opSETNZ()
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*
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* op=0x0F,0x95 (SETNZ b)
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*
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* @this {X86CPU}
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*/
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X86.opSETNZ = function SETNZ()
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{
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X86.fnSETcc.call(this, X86.fnSETNZ);
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};
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/**
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* opSETBE()
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*
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* op=0x0F,0x96 (SETBE b)
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*
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* @this {X86CPU}
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*/
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X86.opSETBE = function SETBE()
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{
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X86.fnSETcc.call(this, X86.fnSETBE);
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};
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/**
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* opSETNBE()
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*
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* op=0x0F,0x97 (SETNBE b)
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*
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* @this {X86CPU}
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*/
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X86.opSETNBE = function SETNBE()
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{
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X86.fnSETcc.call(this, X86.fnSETNBE);
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};
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/**
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* opSETS()
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*
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* op=0x0F,0x98 (SETS b)
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*
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* @this {X86CPU}
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*/
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X86.opSETS = function SETS()
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{
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X86.fnSETcc.call(this, X86.fnSETS);
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};
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/**
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* opSETNS()
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*
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* op=0x0F,0x99 (SETNS b)
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*
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* @this {X86CPU}
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*/
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X86.opSETNS = function SETNS()
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{
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X86.fnSETcc.call(this, X86.fnSETNS);
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};
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/**
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* opSETP()
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*
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* op=0x0F,0x9A (SETP b)
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*
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* @this {X86CPU}
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*/
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X86.opSETP = function SETP()
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{
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X86.fnSETcc.call(this, X86.fnSETP);
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};
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/**
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* opSETNP()
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*
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* op=0x0F,0x9B (SETNP b)
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*
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* @this {X86CPU}
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*/
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X86.opSETNP = function SETNP()
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{
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X86.fnSETcc.call(this, X86.fnSETNP);
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};
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/**
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* opSETL()
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*
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* op=0x0F,0x9C (SETL b)
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*
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* @this {X86CPU}
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*/
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X86.opSETL = function SETL()
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{
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X86.fnSETcc.call(this, X86.fnSETL);
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};
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/**
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* opSETNL()
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*
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* op=0x0F,0x9D (SETNL b)
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*
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* @this {X86CPU}
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*/
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X86.opSETNL = function SETNL()
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{
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X86.fnSETcc.call(this, X86.fnSETNL);
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};
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/**
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* opSETLE()
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*
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* op=0x0F,0x9E (SETLE b)
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*
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* @this {X86CPU}
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||||
*/
|
||||
X86.opSETLE = function SETLE()
|
||||
{
|
||||
X86.fnSETcc.call(this, X86.fnSETLE);
|
||||
};
|
||||
|
||||
/**
|
||||
* opSETNLE()
|
||||
*
|
||||
* op=0x0F,0x9F (SETNLE b)
|
||||
*
|
||||
* @this {X86CPU}
|
||||
*/
|
||||
X86.opSETNLE = function SETNLE()
|
||||
{
|
||||
X86.fnSETcc.call(this, X86.fnSETNLE);
|
||||
};
|
||||
|
||||
/**
|
||||
* opPUSHFS()
|
||||
*
|
||||
|
|
@ -337,6 +817,55 @@ X86.opPOPFS = function POPFS()
|
|||
this.nStepCycles -= this.CYCLES.nOpCyclesPopReg;
|
||||
};
|
||||
|
||||
/**
|
||||
* opBT()
|
||||
*
|
||||
* op=0x0F,0xA3 (BT mem/reg,reg)
|
||||
*
|
||||
* @this {X86CPU}
|
||||
*/
|
||||
X86.opBT = function BT()
|
||||
{
|
||||
this.aOpModMemWord[this.getIPByte()].call(this, X86.fnBT);
|
||||
if (this.regEA !== X86.ADDR_INVALID) this.nStepCycles -= X86CPU.CYCLES_80386.nOpCyclesBitTestMExtra;
|
||||
};
|
||||
|
||||
/**
|
||||
* opSHLDn()
|
||||
*
|
||||
* op=0x0F,0xA4 (SHLD mem/reg,imm8)
|
||||
*
|
||||
* @this {X86CPU}
|
||||
*/
|
||||
X86.opSHLDn = function SHLDn()
|
||||
{
|
||||
/*
|
||||
* TODO: While we rely on bOpcodeBias to dispatch OPERAND-appropriate handlers for the primary opcode bytes,
|
||||
* we don't (yet) have a similar dispatch mechanism for secondary opcode bytes (ie, 0x0F), so the dispatch check
|
||||
* has to happen below.
|
||||
*/
|
||||
this.aOpModMemWord[this.getIPByte()].call(this, this.dataSize == 2? X86.fnSHLDwi : X86.fnSHLDdi);
|
||||
this.nStepCycles -= (this.regEA === X86.ADDR_INVALID? X86CPU.CYCLES_80386.nOpCyclesShiftDR : X86CPU.CYCLES_80386.nOpCyclesShiftDM);
|
||||
};
|
||||
|
||||
/**
|
||||
* opSHLDcl()
|
||||
*
|
||||
* op=0x0F,0xA5 (SHLD mem/reg,CL)
|
||||
*
|
||||
* @this {X86CPU}
|
||||
*/
|
||||
X86.opSHLDcl = function SHLDcl()
|
||||
{
|
||||
/*
|
||||
* TODO: While we rely on bOpcodeBias to dispatch OPERAND-appropriate handlers for the primary opcode bytes,
|
||||
* we don't (yet) have a similar dispatch mechanism for secondary opcode bytes (ie, 0x0F), so the dispatch check
|
||||
* has to happen below.
|
||||
*/
|
||||
this.aOpModMemWord[this.getIPByte()].call(this, this.dataSize == 2? X86.fnSHLDwCL : X86.fnSHLDdCL);
|
||||
this.nStepCycles -= (this.regEA === X86.ADDR_INVALID? X86CPU.CYCLES_80386.nOpCyclesShiftDR : X86CPU.CYCLES_80386.nOpCyclesShiftDM);
|
||||
};
|
||||
|
||||
/**
|
||||
* opPUSHGS()
|
||||
*
|
||||
|
|
@ -363,10 +892,112 @@ X86.opPOPGS = function POPGS()
|
|||
this.nStepCycles -= this.CYCLES.nOpCyclesPopReg;
|
||||
};
|
||||
|
||||
/**
|
||||
* opBTS()
|
||||
*
|
||||
* op=0x0F,0xAB (BTC mem/reg,reg)
|
||||
*
|
||||
* @this {X86CPU}
|
||||
*/
|
||||
X86.opBTS = function BTS()
|
||||
{
|
||||
this.aOpModMemWord[this.getIPByte()].call(this, X86.fnBTS);
|
||||
if (this.regEA !== X86.ADDR_INVALID) this.nStepCycles -= X86CPU.CYCLES_80386.nOpCyclesBitSetMExtra;
|
||||
};
|
||||
|
||||
/**
|
||||
* opSHRDn()
|
||||
*
|
||||
* op=0x0F,0xAC (SHRD mem/reg,imm8)
|
||||
*
|
||||
* @this {X86CPU}
|
||||
*/
|
||||
X86.opSHRDn = function SHRDn()
|
||||
{
|
||||
/*
|
||||
* TODO: While we rely on bOpcodeBias to dispatch OPERAND-appropriate handlers for the primary opcode bytes,
|
||||
* we don't (yet) have a similar dispatch mechanism for secondary opcode bytes (ie, 0x0F), so the dispatch check
|
||||
* has to happen below.
|
||||
*/
|
||||
this.aOpModMemWord[this.getIPByte()].call(this, this.dataSize == 2? X86.fnSHRDwi : X86.fnSHRDdi);
|
||||
this.nStepCycles -= (this.regEA === X86.ADDR_INVALID? X86CPU.CYCLES_80386.nOpCyclesShiftDR : X86CPU.CYCLES_80386.nOpCyclesShiftDM);
|
||||
};
|
||||
|
||||
/**
|
||||
* opSHRDcl()
|
||||
*
|
||||
* op=0x0F,0xAD (SHRD mem/reg,CL)
|
||||
*
|
||||
* @this {X86CPU}
|
||||
*/
|
||||
X86.opSHRDcl = function SHRDcl()
|
||||
{
|
||||
/*
|
||||
* TODO: While we rely on bOpcodeBias to dispatch OPERAND-appropriate handlers for the primary opcode bytes,
|
||||
* we don't (yet) have a similar dispatch mechanism for secondary opcode bytes (ie, 0x0F), so the dispatch check
|
||||
* has to happen below.
|
||||
*/
|
||||
this.aOpModMemWord[this.getIPByte()].call(this, this.dataSize == 2? X86.fnSHRDwCL : X86.fnSHRDdCL);
|
||||
this.nStepCycles -= (this.regEA === X86.ADDR_INVALID? X86CPU.CYCLES_80386.nOpCyclesShiftDR : X86CPU.CYCLES_80386.nOpCyclesShiftDM);
|
||||
};
|
||||
|
||||
/**
|
||||
* opIMUL()
|
||||
*
|
||||
* op=0x0F,0xAF (IMUL reg,mem/reg) (80386 and up)
|
||||
*
|
||||
* @this {X86CPU}
|
||||
*/
|
||||
X86.opIMUL = function IMUL()
|
||||
{
|
||||
/*
|
||||
* TODO: While we rely on bOpcodeBias to dispatch OPERAND-appropriate handlers for the primary opcode bytes,
|
||||
* we don't (yet) have a similar dispatch mechanism for secondary opcode bytes (ie, 0x0F), so the dispatch check
|
||||
* has to happen below.
|
||||
*/
|
||||
this.aOpModRegWord[this.getIPByte()].call(this, this.dataSize == 2? X86.fnIMULrw : X86.fnIMULrd);
|
||||
};
|
||||
|
||||
/**
|
||||
* opBTR()
|
||||
*
|
||||
* op=0x0F,0xB3 (BTC mem/reg,reg) (80386 and up)
|
||||
*
|
||||
* @this {X86CPU}
|
||||
*/
|
||||
X86.opBTR = function BTR()
|
||||
{
|
||||
this.aOpModMemWord[this.getIPByte()].call(this, X86.fnBTR);
|
||||
if (this.regEA !== X86.ADDR_INVALID) this.nStepCycles -= X86CPU.CYCLES_80386.nOpCyclesBitSetMExtra;
|
||||
};
|
||||
|
||||
/**
|
||||
* op=0x0F,0xBA (GRP8 mem/reg) (80386 and up)
|
||||
*
|
||||
* @this {X86CPU}
|
||||
*/
|
||||
X86.opGRP8 = function GRP8()
|
||||
{
|
||||
this.aOpModGrpWord[this.getIPByte()].call(this, X86.aOpGrp8, this.getIPByte);
|
||||
};
|
||||
|
||||
/**
|
||||
* opBTC()
|
||||
*
|
||||
* op=0x0F,0xBB (BTC mem/reg,reg)
|
||||
*
|
||||
* @this {X86CPU}
|
||||
*/
|
||||
X86.opBTC = function BTC()
|
||||
{
|
||||
this.aOpModMemWord[this.getIPByte()].call(this, X86.fnBTC);
|
||||
if (this.regEA !== X86.ADDR_INVALID) this.nStepCycles -= X86CPU.CYCLES_80386.nOpCyclesBitSetMExtra;
|
||||
};
|
||||
|
||||
X86.aOps0F = new Array(256);
|
||||
|
||||
X86.aOps0F[0x00] = X86.opGrp6;
|
||||
X86.aOps0F[0x01] = X86.opGrp7;
|
||||
X86.aOps0F[0x00] = X86.opGRP6;
|
||||
X86.aOps0F[0x01] = X86.opGRP7;
|
||||
X86.aOps0F[0x02] = X86.opLAR;
|
||||
X86.aOps0F[0x03] = X86.opLSL;
|
||||
X86.aOps0F[0x05] = X86.opLOADALL;
|
||||
|
|
@ -386,14 +1017,56 @@ if (I386) {
|
|||
X86.aOps0F386 = [];
|
||||
X86.aOps0F386[0x20] = X86.opMOVrcr;
|
||||
X86.aOps0F386[0x22] = X86.opMOVcrr;
|
||||
X86.aOps0F386[0x80] = X86.opJOw;
|
||||
X86.aOps0F386[0x81] = X86.opJNOw;
|
||||
X86.aOps0F386[0x82] = X86.opJCw;
|
||||
X86.aOps0F386[0x83] = X86.opJNCw;
|
||||
X86.aOps0F386[0x84] = X86.opJZw;
|
||||
X86.aOps0F386[0x85] = X86.opJNZw;
|
||||
X86.aOps0F386[0x86] = X86.opJBEw;
|
||||
X86.aOps0F386[0x87] = X86.opJNBEw;
|
||||
X86.aOps0F386[0x88] = X86.opJSw;
|
||||
X86.aOps0F386[0x89] = X86.opJNSw;
|
||||
X86.aOps0F386[0x8A] = X86.opJPw;
|
||||
X86.aOps0F386[0x8B] = X86.opJNPw;
|
||||
X86.aOps0F386[0x8C] = X86.opJLw;
|
||||
X86.aOps0F386[0x8D] = X86.opJNLw;
|
||||
X86.aOps0F386[0x8E] = X86.opJLEw;
|
||||
X86.aOps0F386[0x8F] = X86.opJNLEw;
|
||||
X86.aOps0F386[0x90] = X86.opSETO;
|
||||
X86.aOps0F386[0x91] = X86.opSETNO;
|
||||
X86.aOps0F386[0x92] = X86.opSETC;
|
||||
X86.aOps0F386[0x93] = X86.opSETNC;
|
||||
X86.aOps0F386[0x94] = X86.opSETZ;
|
||||
X86.aOps0F386[0x95] = X86.opSETNZ;
|
||||
X86.aOps0F386[0x96] = X86.opSETBE;
|
||||
X86.aOps0F386[0x97] = X86.opSETNBE;
|
||||
X86.aOps0F386[0x98] = X86.opSETS;
|
||||
X86.aOps0F386[0x99] = X86.opSETNS;
|
||||
X86.aOps0F386[0x9A] = X86.opSETP;
|
||||
X86.aOps0F386[0x9B] = X86.opSETNP;
|
||||
X86.aOps0F386[0x9C] = X86.opSETL;
|
||||
X86.aOps0F386[0x9D] = X86.opSETNL;
|
||||
X86.aOps0F386[0x9E] = X86.opSETLE;
|
||||
X86.aOps0F386[0x9F] = X86.opSETNLE;
|
||||
X86.aOps0F386[0xA0] = X86.opPUSHFS;
|
||||
X86.aOps0F386[0xA1] = X86.opPOPFS;
|
||||
X86.aOps0F386[0xA3] = X86.opBT;
|
||||
X86.aOps0F386[0xA4] = X86.opSHLDn;
|
||||
X86.aOps0F386[0xA5] = X86.opSHLDcl;
|
||||
X86.aOps0F386[0xA8] = X86.opPUSHGS;
|
||||
X86.aOps0F386[0xA9] = X86.opPOPGS;
|
||||
X86.aOps0F386[0xAB] = X86.opBTS;
|
||||
X86.aOps0F386[0xAC] = X86.opSHRDn;
|
||||
X86.aOps0F386[0xAD] = X86.opSHRDcl;
|
||||
X86.aOps0F386[0xAF] = X86.opIMUL;
|
||||
X86.aOps0F386[0xB3] = X86.opBTR;
|
||||
X86.aOps0F386[0xBA] = X86.opGRP8;
|
||||
X86.aOps0F386[0xBB] = X86.opBTC;
|
||||
}
|
||||
|
||||
/*
|
||||
* These instruction groups are not as orthogonal as the original 8086/8088 groups (Grp1 through Grp4): some of
|
||||
* These instruction groups are not as orthogonal as the original 8086/8088 groups (Grp1 through Grp4); some of
|
||||
* the instructions in Grp6 and Grp7 only read their dst operand (eg, LLDT), which means the ModRM helper function
|
||||
* must insure that setEAWord() is disabled, while others only write their dst operand (eg, SLDT), which means that
|
||||
* getEAWord() should be disabled *prior* to calling the ModRM helper function. This latter case requires that
|
||||
|
|
@ -410,10 +1083,15 @@ X86.aOpGrp6Real = [
|
|||
];
|
||||
|
||||
/*
|
||||
* Unlike Grp6, Grp7 does not require separate real-mode and protected-mode dispatch tables, because all Grp7
|
||||
* instructions are valid in both modes.
|
||||
* Unlike Grp6, Grp7 does not require separate real-mode and protected-mode dispatch tables,
|
||||
* because all Grp7 instructions are valid in both modes.
|
||||
*/
|
||||
X86.aOpGrp7 = [
|
||||
X86.fnSGDT, X86.fnSIDT, X86.fnLGDT, X86.fnLIDT, // 0x0F,0x01(reg=0x0-0x3)
|
||||
X86.fnSMSW, X86.fnGRPUndefined, X86.fnLMSW, X86.fnGRPUndefined // 0x0F,0x01(reg=0x4-0x7)
|
||||
];
|
||||
|
||||
X86.aOpGrp8 = [
|
||||
X86.fnGRPUndefined, X86.fnGRPUndefined, X86.fnGRPUndefined, X86.fnGRPUndefined, // 0x0F,0xBA(reg=0x0-0x3)
|
||||
X86.fnBT, X86.fnBTS, X86.fnBTR, X86.fnBTC // 0x0F,0xBA(reg=0x4-0x7)
|
||||
];
|
||||
|
|
|
|||
Loading…
Reference in a new issue