Debugger changes for improved 32-bit support
This commit is contained in:
Jeff Parsons
jeffpar
parent
9ba73970a4
commit
f50612e7ca
21 changed files with 3581 additions and 2949 deletions
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@ -40,9 +40,9 @@ if (typeof module !== 'undefined') {
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var X86Op0F = {
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/**
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* @this {X86CPU}
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* op=0x0F,0x00 (GRP6 rm)
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*
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* op=0x0F,0x00 (grp6 rm)
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* @this {X86CPU}
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*/
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opGrp6: function() {
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var bModRM = this.getIPByte();
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@ -52,9 +52,9 @@ var X86Op0F = {
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this.aOpModGrpWord[bModRM].call(this, this.aOpGrp6, X86Grps.opGrpNoSrc);
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},
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/**
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* @this {X86CPU}
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* op=0x0F,0x01 (GRP7 rm)
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*
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* op=0x0F,0x01 (grp7 rm)
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* @this {X86CPU}
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*/
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opGrp7: function() {
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var bModRM = this.getIPByte();
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@ -64,17 +64,21 @@ var X86Op0F = {
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this.aOpModGrpWord[bModRM].call(this, X86Op0F.aOpGrp7, X86Grps.opGrpNoSrc);
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},
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/**
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* @this {X86CPU}
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* opLAR()
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*
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* op=0x0F,0x02 (lar reg,rm)
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* op=0x0F,0x02 (LAR reg,rm)
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*
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* @this {X86CPU}
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*/
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opLAR: function() {
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this.aOpModRegWord[this.getIPByte()].call(this, X86Help.opHelpLAR);
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},
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/**
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* @this {X86CPU}
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* opLSL()
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*
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* op=0x0F,0x03 (lsl reg,rm)
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* op=0x0F,0x03 (LSL reg,rm)
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*
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* @this {X86CPU}
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*/
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opLSL: function() {
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this.aOpModRegWord[this.getIPByte()].call(this, X86Help.opHelpLSL);
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@ -82,6 +86,8 @@ var X86Op0F = {
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/**
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* opLOADALL()
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*
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* op=0x0F,0x05 (LOADALL)
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*
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* From the "Undocumented iAPX 286 Test Instruction" document at http://www.pcjs.org/pubs/pc/reference/intel/80286/loadall/:
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*
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* Physical Address (Hex) Associated CPU Register
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@ -117,8 +123,6 @@ var X86Op0F = {
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* no particular reason.
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*
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* @this {X86CPU}
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*
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* op=0x0F,0x05 (loadall)
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*/
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opLOADALL: function() {
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if (this.segCS.cpl) {
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@ -168,9 +172,11 @@ var X86Op0F = {
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if (DEBUG && DEBUGGER && (this.regCR0 & X86.CR0.MSW.PE)) this.stopCPU();
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},
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/**
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* @this {X86CPU}
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* opCLTS()
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*
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* op=0x0F,0x06 (clts)
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* op=0x0F,0x06 (CLTS)
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*
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* @this {X86CPU}
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*/
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opCLTS: function() {
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if (this.segCS.cpl) {
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@ -181,6 +187,10 @@ var X86Op0F = {
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this.nStepCycles -= 2;
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},
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/**
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* opSLDT(dst, src)
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*
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* op=0x0F,0x00,reg=0x0 (GRP6:SLDT)
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*
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* @this {X86CPU}
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* @param {number} dst
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* @param {number} src (null)
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@ -191,6 +201,10 @@ var X86Op0F = {
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return this.segLDT.sel;
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},
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/**
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* opSTR(dst, src)
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*
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* op=0x0F,0x00,reg=0x1 (GRP6:STR)
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*
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* @this {X86CPU}
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* @param {number} dst
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* @param {number} src (null)
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@ -201,6 +215,10 @@ var X86Op0F = {
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return this.segTSS.sel;
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},
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/**
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* opLLDT(dst, src)
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*
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* op=0x0F,0x00,reg=0x2 (GRP6:LLDT)
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*
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* @this {X86CPU}
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* @param {number} dst
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* @param {number} src (null)
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@ -213,6 +231,10 @@ var X86Op0F = {
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return dst;
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},
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/**
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* opLTR(dst, src)
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*
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* op=0x0F,0x00,reg=0x3 (GRP6:LTR)
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*
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* @this {X86CPU}
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* @param {number} dst
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* @param {number} src (null)
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@ -228,6 +250,10 @@ var X86Op0F = {
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return dst;
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},
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/**
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* opVERR(dst, src)
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*
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* op=0x0F,0x00,reg=0x4 (GRP6:VERR)
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*
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* @this {X86CPU}
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* @param {number} dst
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* @param {number} src (null)
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@ -264,6 +290,10 @@ var X86Op0F = {
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return dst;
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},
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/**
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* opVERW(dst, src)
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*
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* op=0x0F,0x00,reg=0x5 (GRP6:VERW)
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*
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* @this {X86CPU}
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* @param {number} dst
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* @param {number} src (null)
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@ -295,6 +325,10 @@ var X86Op0F = {
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return dst;
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},
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/**
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* opSGDT(dst, src)
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*
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* op=0x0F,0x01,reg=0x0 (GRP7:SGDT)
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*
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* @this {X86CPU}
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* @param {number} dst
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* @param {number} src (null)
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@ -349,6 +383,10 @@ var X86Op0F = {
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return dst;
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},
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/**
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* opSIDT(dst, src)
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*
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* op=0x0F,0x01,reg=0x1 (GRP7:SIDT)
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*
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* @this {X86CPU}
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* @param {number} dst
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* @param {number} src (null)
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@ -378,6 +416,8 @@ var X86Op0F = {
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/**
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* opLGDT(dst, src)
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*
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* op=0x0F,0x01,reg=0x2 (GRP7:LGDT)
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*
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* The 80286 LGDT instruction expects a 40-bit operand: a 16-bit limit, followed by a 24-bit address;
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* the ModRM decoder has already supplied the first word of the operand (in dst), which corresponds to the
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* limit, so we must fetch the remaining 24 bits ourselves.
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@ -401,6 +441,8 @@ var X86Op0F = {
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/**
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* opLIDT(dst, src)
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*
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* op=0x0F,0x01,reg=0x3 (GRP7:LIDT)
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*
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* The 80286 LIDT instruction expects a 40-bit operand: a 16-bit limit, followed by a 24-bit address;
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* the ModRM decoder has already supplied the first word of the operand (in dst), which corresponds to the
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* limit, so we must fetch the remaining 24 bits ourselves.
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@ -422,6 +464,10 @@ var X86Op0F = {
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return dst;
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},
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/**
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* opSMSW(dst, src)
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*
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* op=0x0F,0x01,reg=0x4 (GRP7:SMSW)
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*
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* @this {X86CPU}
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* @param {number} dst
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* @param {number} src (null)
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@ -432,6 +478,10 @@ var X86Op0F = {
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return this.regCR0;
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},
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/**
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* opLMSW(dst, src)
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*
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* op=0x0F,0x01,reg=0x6 (GRP7:LMSW)
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*
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* @this {X86CPU}
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* @param {number} dst
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* @param {number} src (null)
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@ -442,6 +492,118 @@ var X86Op0F = {
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this.nStepCycles -= (this.regEA < 0? 3 : 6);
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this.opFlags |= X86.OPFLAG.NOWRITE;
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return dst;
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},
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/**
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* opMOVrcr()
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*
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* op=0x0F,0x20 (MOV reg,cr)
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*
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* NOTE: Since the ModRM decoders deal only with general-purpose registers, we must move
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* the appropriate control register into a special variable (regMD16), which our helper function
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* (opHelpMOVMD16) will use to replace the decoder's src operand.
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*
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* @this {X86CPU}
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*/
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opMOVrcr: function() {
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var bModRM = this.getIPByte() | 0xc0;
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/*
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* Unlike, say, opcode 0x8C (MOV word,sr), this opcode supports only registers, not memory;
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* however, the 80386 apparently ignores the mod bits, treating any combination as if it was 0xc0.
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*
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if ((bModRM & 0xc0) != 0xc0) {
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X86Help.opHelpInvalid.call(this);
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return;
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}
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*/
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var reg = (bModRM & 0x38) >> 3;
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switch (reg) {
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case 0x0:
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this.regMD16 = this.regCR0;
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break;
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case 0x1:
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this.regMD16 = this.regCR1;
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break;
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case 0x2:
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this.regMD16 = this.regCR2;
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break;
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case 0x3:
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this.regMD16 = this.regCR3;
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break;
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default:
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X86Help.opHelpUndefined.call(this);
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return;
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}
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/*
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* Like other MOV operations, the destination does not need to be read, just written;
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* however, it's moot, because we've already restricted this opcode to registers only.
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*
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* this.opFlags |= X86.OPFLAG.NOREAD;
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*/
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this.aOpModRegWord[bModRM].call(this, X86Help.opHelpMOVMD16);
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},
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/**
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* opMOVcrr()
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*
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* op=0x0F,0x22 (MOV cr,reg)
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*
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* NOTE: Since the ModRM decoders deal only with general-purpose registers, we have to
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* make a note of which general-purpose register will be overwritten, so that we can restore it
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* after moving the modified value to the correct control register.
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*
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* @this {X86CPU}
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*/
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opMOVcrr: function() {
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var temp;
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var bModRM = this.getIPByte() | 0xc0;
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/*
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* Unlike, say, opcode 0x8E (MOV sr,word), this opcode supports only registers, not memory;
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* however, the 80386 apparently ignores the mod bits, treating any combination as if it was 0xc0.
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*
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if ((bModRM & 0xc0) != 0xc0) {
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X86Help.opHelpInvalid.call(this);
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return;
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}
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*/
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var reg = (bModRM & 0x38) >> 3;
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switch(reg) {
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case 0x0:
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temp = this.regEAX;
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break;
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case 0x1:
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temp = this.regECX; // TODO: Is setting CR1 actually allowed on an 80386?
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break;
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case 0x2:
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temp = this.regEDX;
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break;
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case 0x3:
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temp = this.regEBX;
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break;
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default:
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X86Help.opHelpInvalid.call(this);
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return;
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}
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this.aOpModRegWord[bModRM].call(this, X86Help.opHelpMOV);
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switch (reg) {
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case 0x0:
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reg = this.regEAX;
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this.regEAX = temp;
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X86Help.opHelpLCR0.call(this, reg);
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break;
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case 0x1:
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this.regCR1 = this.regECX;
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this.regECX = temp;
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break;
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case 0x2:
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this.regCR2 = this.regEDX;
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this.regEDX = temp;
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break;
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case 0x3:
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this.regCR3 = this.regEBX;
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this.regEBX = temp;
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break;
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default:
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break; // there IS no other case, but JavaScript inspections don't know that
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}
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}
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};
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