Debugger must use CPU memory functions now, in preparation for paging
This commit is contained in:
Jeff Parsons
jeffpar
parent
380db6ef7d
commit
f36b79cd25
4 changed files with 138 additions and 31 deletions
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@ -1513,10 +1513,10 @@ if (DEBUGGER) {
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{
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this.println("id physaddr blkaddr used size type");
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this.println("-------- --------- -------- ------ ------ ----");
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for (var i = 0; i < this.bus.aMemBlocks.length; i++) {
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var block = this.bus.aMemBlocks[i];
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for (var i = 0; i < this.cpu.aMemBlocks.length; i++) {
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var block = this.cpu.aMemBlocks[i];
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if (block.type === Memory.TYPE.NONE) continue;
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this.println(str.toHex(block.id) + " %" + str.toHex(i << this.bus.blockShift) + ": " + str.toHex(block.addr) + " " + str.toHexWord(block.used) + " " + str.toHexWord(block.size) + " " + Memory.TYPE.NAMES[block.type]);
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this.println(str.toHex(block.id) + " %" + str.toHex(i << this.cpu.blockShift) + ": " + str.toHex(block.addr) + " " + str.toHexWord(block.used) + " " + str.toHexWord(block.size) + " " + Memory.TYPE.NAMES[block.type]);
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}
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};
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@ -1636,7 +1636,7 @@ if (DEBUGGER) {
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for (var sField in Debugger.aTSSFields) {
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var off = Debugger.aTSSFields[sField];
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var ch = (sField.length < 8? ' ' : '');
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var w = this.bus.getShortDirect(seg.base + off);
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var w = this.cpu.getShort(seg.base + off);
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if (sDump) sDump += '\n';
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sDump += str.toHexWord(off) + " " + sField + ": " + ch + str.toHexWord(w);
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}
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@ -2450,7 +2450,7 @@ if (DEBUGGER) {
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*/
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if (nState >= 0 && this.aaOpcodeCounts.length) {
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this.cInstructions++;
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var bOpcode = this.bus.getByteDirect(addr);
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var bOpcode = this.cpu.getByte(addr);
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this.aaOpcodeCounts[bOpcode][1]++;
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var a = this.aOpcodeHistory[this.iOpcodeHistory];
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a[0] = this.cpu.getIP();
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@ -2602,8 +2602,7 @@ if (DEBUGGER) {
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/**
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* getByte(aAddr, inc)
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*
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* getByte() should be used for all Debugger memory reads (eg, doDump, doUnassemble), to ensure
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* all notification handlers are bypassed for physical addresses.
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* We must route all our memory requests through the CPU now, in case paging is enabled.
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*
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* @this {Debugger}
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* @param {Array} aAddr
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@ -2615,8 +2614,9 @@ if (DEBUGGER) {
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var b = 0xff;
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var addr = this.getAddr(aAddr, false, 1);
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if (addr !== X86.ADDR_INVALID) {
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b = this.bus.getByteDirect(addr);
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this.assert((b == (b & 0xff)), "invalid byte (" + b + ") at address: " + this.hexAddr(aAddr));
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this.nSuppress++;
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b = this.cpu.getByte(addr);
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this.nSuppress--;
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if (inc !== undefined) this.incAddr(aAddr, inc);
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}
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return b;
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@ -2651,8 +2651,9 @@ if (DEBUGGER) {
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var w = 0xffff;
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var addr = this.getAddr(aAddr, false, 2);
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if (addr !== X86.ADDR_INVALID) {
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w = this.bus.getShortDirect(addr);
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this.assert((w == (w & 0xffff)), "invalid word (" + w + ") at address: " + this.hexAddr(aAddr));
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this.nSuppress++;
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w = this.cpu.getShort(addr);
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this.nSuppress--;
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if (inc !== undefined) this.incAddr(aAddr, inc);
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}
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return w;
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@ -2671,7 +2672,9 @@ if (DEBUGGER) {
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var l = -1;
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var addr = this.getAddr(aAddr, false, 4);
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if (addr !== X86.ADDR_INVALID) {
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l = this.bus.getLongDirect(addr);
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this.nSuppress++;
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l = this.cpu.getLong(addr);
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this.nSuppress--;
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if (inc !== undefined) this.incAddr(aAddr, inc);
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}
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return l;
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@ -2680,10 +2683,6 @@ if (DEBUGGER) {
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/**
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* setByte(aAddr, b, inc)
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*
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* setByte() should be used for all Debugger memory writes (eg, doAssemble, doEdit), to insure
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* all memory notification handlers are bypassed; in addition, we want the Debugger to be able to
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* change the contents of the simulated ROM images.
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*
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* @this {Debugger}
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* @param {Array} aAddr
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* @param {number} b
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@ -2693,7 +2692,9 @@ if (DEBUGGER) {
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{
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var addr = this.getAddr(aAddr, true, 1);
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if (addr !== X86.ADDR_INVALID) {
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this.bus.setByteDirect(addr, b);
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this.nSuppress++;
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this.cpu.setByte(addr, b);
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this.nSuppress--;
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if (inc !== undefined) this.incAddr(aAddr, inc);
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this.cpu.updateCPU();
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}
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@ -2711,7 +2712,9 @@ if (DEBUGGER) {
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{
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var addr = this.getAddr(aAddr, true, 2);
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if (addr !== X86.ADDR_INVALID) {
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this.bus.setShortDirect(addr, w);
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this.nSuppress++;
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this.cpu.setShort(addr, w);
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this.nSuppress--;
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if (inc !== undefined) this.incAddr(aAddr, inc);
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this.cpu.updateCPU();
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}
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@ -2738,6 +2741,7 @@ if (DEBUGGER) {
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}
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}
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this.aBreakWrite = ["write"];
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this.nSuppress = 0;
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};
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/**
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@ -2921,6 +2925,8 @@ if (DEBUGGER) {
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*/
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Debugger.prototype.checkBreakpoint = function(addr, aBreak, fTemp)
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{
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if (this.nSuppress) return false;
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/*
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* Time to check for execution breakpoints; note that this should be done BEFORE updating frequency
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* or history data (see checkInstruction), since we might not actually execute the current instruction.
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@ -3536,8 +3542,8 @@ if (DEBUGGER) {
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*/
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Debugger.prototype.parseAddr = function(sAddr, type)
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{
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var aAddr;
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var aAddrNext = (type == Debugger.ADDR_DATA? this.aAddrNextData : this.aAddrNextCode);
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var off = aAddrNext[0], seg = aAddrNext[1], addr = aAddrNext[2];
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if (sAddr !== undefined) {
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@ -3549,7 +3555,7 @@ if (DEBUGGER) {
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addr = 0;
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}
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var aAddr = this.findSymbolAddr(sAddr);
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aAddr = this.findSymbolAddr(sAddr);
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if (aAddr && aAddr.length) return aAddr;
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var iColon = sAddr.indexOf(":");
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@ -3567,7 +3573,8 @@ if (DEBUGGER) {
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addr = null;
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}
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}
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var aAddr = [off, seg, addr];
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aAddr = [off, seg, addr];
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this.checkLimit(aAddr);
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return aAddr;
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};
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@ -3643,7 +3643,7 @@ X86.fnPageFault = function(addr, fPresent, fWrite)
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X86.fnFaultMessage = function(nFault, nError, fHalt)
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{
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var bitsMessage = Messages.FAULT;
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var bOpcode = this.bus.getByteDirect(this.regLIP);
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var bOpcode = this.getByte(this.regLIP);
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/*
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* OS/2 1.0 uses an INT3 (0xCC) opcode in conjunction with an invalid IDT to trigger a triple-fault
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@ -605,6 +605,13 @@ X86Seg.prototype.loadDesc8 = function(addrDesc, sel, fSuppress)
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var fGate, regPSMask, nFaultError, regSP;
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var rpl = sel & X86.SEL.RPL;
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var dpl = (acc & X86.DESC.ACC.DPL.MASK) >> X86.DESC.ACC.DPL.SHIFT;
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if (selMasked && !(acc & X86.DESC.ACC.PRESENT)) {
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if (!fSuppress) X86.fnFault.call(cpu, X86.EXCEPTION.NP_FAULT, sel);
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base = X86.ADDR_INVALID;
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break;
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}
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/*
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* Since we are X86Seg.ID.CODE, we can use this.cpl instead of the more generic cpu.segCS.cpl
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*/
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@ -713,7 +720,12 @@ X86Seg.prototype.loadDesc8 = function(addrDesc, sel, fSuppress)
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}
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else if (this.id == X86Seg.ID.DATA) {
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if (selMasked) {
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if (type < X86.DESC.ACC.TYPE.DATA_READONLY || (type & (X86.DESC.ACC.TYPE.CODE | X86.DESC.ACC.TYPE.READABLE)) == X86.DESC.ACC.TYPE.CODE) {
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if (!(acc & X86.DESC.ACC.PRESENT)) {
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if (!fSuppress) X86.fnFault.call(cpu, X86.EXCEPTION.NP_FAULT, sel);
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base = X86.ADDR_INVALID;
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break;
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}
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if (type < X86.DESC.ACC.TYPE.SEG || (type & (X86.DESC.ACC.TYPE.CODE | X86.DESC.ACC.TYPE.READABLE)) == X86.DESC.ACC.TYPE.CODE) {
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/*
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* OS/2 1.0 triggers this "Empty Descriptor" GP_FAULT multiple times during boot; eg:
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*
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@ -742,7 +754,12 @@ X86Seg.prototype.loadDesc8 = function(addrDesc, sel, fSuppress)
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}
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}
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else if (this.id == X86Seg.ID.STACK) {
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if (!selMasked || type < X86.DESC.ACC.TYPE.DATA_READONLY || (type & (X86.DESC.ACC.TYPE.CODE | X86.DESC.ACC.TYPE.READABLE)) == X86.DESC.ACC.TYPE.CODE) {
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if (!(acc & X86.DESC.ACC.PRESENT)) {
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if (!fSuppress) X86.fnFault.call(cpu, X86.EXCEPTION.SS_FAULT, sel);
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base = X86.ADDR_INVALID;
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break;
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}
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if (!selMasked || type < X86.DESC.ACC.TYPE.SEG || (type & (X86.DESC.ACC.TYPE.CODE | X86.DESC.ACC.TYPE.WRITABLE)) != X86.DESC.ACC.TYPE.WRITABLE) {
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if (!fSuppress) X86.fnFault.call(cpu, X86.EXCEPTION.GP_FAULT, sel, true);
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base = X86.ADDR_INVALID;
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break;
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@ -14,14 +14,32 @@ DPL2 equ 2
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DPL3 equ 3
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ACC_TYPE_SEG equ 0x1000
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ACC_PRESENT equ 0x8000
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ACC_TYPE_CODE equ 0x0800
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ACC_TYPE_READABLE equ 0x0200
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ACC_TYPE_WRITABLE equ 0x0200
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ACC_TYPE_CODE_READABLE equ 0x1a00
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ACC_TYPE_DATA_WRITABLE equ 0x1200
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ACC_TYPE_CODE_READABLE equ (0x1a00 | ACC_PRESENT)
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ACC_TYPE_DATA_WRITABLE equ (0x1200 | ACC_PRESENT)
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EXT_BIG equ 0x0040
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;
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; We build some data structures in the first page (0x0000-0x0fff) of RAM:
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;
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; 0x0000-0x03ff Real-mode IDT (256*4)
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; 0x0400-0x0bff Prot-mode IDT (256*8)
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; 0x0c00-0x0cff GDT (enough room for 32 selectors)
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; 0x0d00-0x0d07 IDTR
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; 0x0d08-0x0d0f GDTR
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; 0x0d10-0x0fff reserved
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;
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; And in the second page (0x1000-0x1fff), let's build a page directory, followed by a single page table that
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; will allow us to map up to 4Mb (although we'll only create entries for the first 1Mb).
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;
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RAM_GDT equ 0x0c00
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RAM_IDTR equ 0x0d00
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RAM_GDTR equ 0x0d08
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CSEG_REAL equ 0xf000
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CSEG_PROT equ 0x0008
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DSEG_PROT equ 0x0010
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@ -29,22 +47,77 @@ DSEG_PROT equ 0x0010
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CR0_MSW_PE equ 0x0001
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;
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; descDT defines a descriptor, given a base (%1), limit (%2), type (%3), dpl (%4), and ext (%5)
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; set initializes a register to the specified value (eg, "set eax,0")
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;
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%macro defDesc 1-5 0,0,0,0
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%macro set 2
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%if %2 = 0
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sub %1,%1
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%else
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mov %1,%2
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%endif
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%endmacro
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;
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; defDesc defines a descriptor, given a base (%1), limit (%2), type (%3), dpl (%4), and ext (%5)
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;
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%macro defDesc 1-4 0,0,0,0
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dw (%2 & 0x0000ffff)
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dw (%1 & 0x0000ffff)
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dw ((%1 & 0x00ff0000) >> 16) | %3 | (%4 << 13)
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dw ((%2 & 0x000f0000) >> 16) | %5 | ((%1 & 0xff000000) >> 16)
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%endmacro
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;
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; setDesc creates a descriptor, given a base (%1), limit (%2), type (%3), dpl (%4), and ext (%5)
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;
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%assign selDesc 0
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%macro setDesc 1-4 0,0,0,none
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set ebx,%1
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set ecx,%2
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set edx,%3
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call storeDesc
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%assign %4 selDesc
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%assign selDesc selDesc+8
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%endmacro
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start: mov eax,0x44332211
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start: cli ; disable all interrupts
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mov al,0xff ; and ensure that no hardware interrupts can sneak in
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out 0x21,al ; if interrupts become enabled later
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out 0xa1,al
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sub ax,ax
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mov ds,ax
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mov es,ax
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mov ss,ax
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mov sp,0x1000
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mov eax,0x44332211
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mov ebx,eax
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mov ecx,0x88776655
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mul ecx
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div ecx
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jnz near goProt ; apparently we have to tell NASM "near" because this is a forward reference
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cmp eax,ebx
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je near initRAM ; apparently we have to tell NASM "near" because this is a forward reference
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times 32768 nop ; lots of NOPs to force a 16-bit conditional jump
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;
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; storeDesc(EBX=base, ECX=limit, EDX=type, EDI=target)
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;
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storeDesc:
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cld
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mov ax,cx
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stosw ; store the low 16 bits of limit from ECX
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mov ax,bx
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stosw ; store the low 16 bits of base from EBX
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mov ax,dx
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shr ebx,16
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mov al,bl
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stosw
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shr ecx,16
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mov al,cl
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and al,0xf
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mov ah,bh
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stosw
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ret
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addrGDT:dw romGDTEnd - romGDT - 1 ; 16-bit limit of romGDT
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dw romGDT, 0xffff ; 32-bit base address of romGDT (works as long as we're aliased at 0xffff0000)
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@ -54,7 +127,17 @@ romGDT: defDesc 0 ; the first descriptor in any descriptor table is always a d
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defDesc 0x00000000,0x000fffff,ACC_TYPE_DATA_WRITABLE
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romGDTEnd:
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goProt: o32 lgdt [cs:addrGDT]
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initRAM:
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set edi,RAM_GDT
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mov [RAM_GDTR+2],edi
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setDesc 0,0,0,NULL
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setDesc 0x000f0000,0x0000ffff,ACC_TYPE_CODE_READABLE,CSEG_PROT
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setDesc 0x00000000,0x000fffff,ACC_TYPE_DATA_WRITABLE,DSEG_PROT
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sub edi,RAM_GDT
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dec edi
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mov [RAM_GDTR],di
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goProt: o32 lgdt [RAM_GDTR]
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mov eax,cr0
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or eax,CR0_MSW_PE
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mov cr0,eax
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