Implemented INC/DEC opcodes
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b2294e2293
commit
e322c5f912
3 changed files with 133 additions and 50 deletions
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@ -3140,38 +3140,44 @@ if (DEBUGGER) {
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return;
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}
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var fValid = false;
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var w = this.parseExpression(sValue);
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if (w === undefined) return;
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if (w !== undefined) {
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fValid = true;
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var sRegMatch = sReg.toUpperCase();
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switch (sRegMatch) {
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case "PC":
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cpu.setPC(w);
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this.dbgAddrNextCode = this.newAddr(cpu.getPC());
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break;
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case "NF":
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if (w) cpu.setNF(); else cpu.clearNF();
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break;
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case "ZF":
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if (w) cpu.setZF(); else cpu.clearZF();
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break;
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case "VF":
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if (w) cpu.setVF(); else cpu.clearVF();
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break;
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case "CF":
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if (w) cpu.setCF(); else cpu.clearCF();
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break;
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default:
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this.println("unknown register: " + sReg);
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return;
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var sRegMatch = sReg.toUpperCase();
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switch (sRegMatch) {
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case "SP":
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case "R6":
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cpu.setSP(w);
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break;
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case "PC":
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case "R7":
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cpu.setPC(w);
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this.dbgAddrNextCode = this.newAddr(cpu.getPC());
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break;
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case "N":
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if (w) cpu.setNF(); else cpu.clearNF();
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break;
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case "Z":
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if (w) cpu.setZF(); else cpu.clearZF();
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break;
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case "V":
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if (w) cpu.setVF(); else cpu.clearVF();
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break;
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case "C":
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if (w) cpu.setCF(); else cpu.clearCF();
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break;
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default:
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if (sRegMatch.charAt(0) == 'R') {
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var iReg = +sRegMatch.charAt(1);
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if (iReg >= 0 && iReg < 6) {
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cpu.regsGen[iReg] = w & 0xffff;
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break;
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}
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}
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}
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if (!fValid) {
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this.println("invalid value: " + sValue);
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this.println("unknown register: " + sReg);
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return;
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}
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cpu.updateCPU();
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this.println("updated registers:");
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}
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