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Some corrections as to what features are available on the 11/40 vs. 11/45

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This commit is contained in:
Jeff Parsons 2016-12-31 11:23:25 -08:00 • committed by Jeff Parsons
commit dd628148ef
8 changed files with 396 additions and 367 deletions
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129
modules/pdp11/lib/cpuops.js
View file

@ -35,7 +35,11 @@
var PDP11 = require("./defines");
/*
* Decoding starts at the bottom of this file, in op1120() and op1145().
* Decoding starts near the bottom of this file, in op1120() and op1140(). Obviously, there are
* MANY more PDP-11 models than the 11/20 and 11/40, but for the broad model categories that PDPjs
* supports (ie, MODEL_1120, MODEL_1140, MODEL_1145, and MODEL_1170), the biggest differences are
* between MODEL_1120 and MODEL_1140, so decoding is divided into those two categories, and all
* other differences are handled inside the opcode handlers.
*
* The basic decoding approach is to dispatch on the top 4 bits of the opcode, and if further
* decoding is required, the dispatched function will dispatch on the next 4 bits, and so on
@ -51,6 +55,11 @@ var PDP11 = require("./defines");
* For example, opADD() passes the helper function fnADD() to the appropriate update method. This
* allows the update method to perform the entire read/modify/write operation, because the modify
* step is performed internally, via the fnXXX() helper function.
*
* For the handful of instructions in the 1140 tables that actually exist only on the 11/45 and
* 11/70 (ie, MFPD, MTPD, and SPL), those opcode handlers perform their own model checks. That's
* simpler than creating additional tables, and seems fine for instructions that are not commonly
* executed.
*/
/**
@ -1729,7 +1738,7 @@ PDP11.opSOB = function(opCode)
*/
PDP11.opSPL = function(opCode)
{
if (!(opCode & 0x08)) {
if (!(opCode & 0x08) || this.model < PDP11.MODEL_1145) {
PDP11.opUndefined.call(this, opCode);
return;
}
@ -2217,103 +2226,107 @@ PDP11.aOp8CXn_1120 = [
];
/**
* op1145(opCode)
* op1140(opCode)
*
* @this {CPUStatePDP11}
* @param {number} opCode
*/
PDP11.op1145 = function(opCode)
PDP11.op1140 = function(opCode)
{
PDP11.aOpXnnn_1145[opCode >> 12].call(this, opCode);
PDP11.aOpXnnn_1140[opCode >> 12].call(this, opCode);
};
/**
* op0Xnn_1145(opCode)
* op0Xnn_1140(opCode)
*
* @this {CPUStatePDP11}
* @param {number} opCode
*/
PDP11.op0Xnn_1145 = function(opCode)
PDP11.op0Xnn_1140 = function(opCode)
{
PDP11.aOp0Xnn_1145[(opCode >> 8) & 0xf].call(this, opCode);
PDP11.aOp0Xnn_1140[(opCode >> 8) & 0xf].call(this, opCode);
};
/**
* op0DXn_1145(opCode)
* op0DXn_1140(opCode)
*
* @this {CPUStatePDP11}
* @param {number} opCode
*/
PDP11.op0DXn_1145 = function(opCode)
PDP11.op0DXn_1140 = function(opCode)
{
PDP11.aOp0DXn_1145[(opCode >> 6) & 0x3].call(this, opCode);
PDP11.aOp0DXn_1140[(opCode >> 6) & 0x3].call(this, opCode);
};
/**
* op00Xn_1145(opCode)
* op00Xn_1140(opCode)
*
* @this {CPUStatePDP11}
* @param {number} opCode
*/
PDP11.op00Xn_1145 = function(opCode)
PDP11.op00Xn_1140 = function(opCode)
{
PDP11.aOp00Xn_1145[(opCode >> 4) & 0xf].call(this, opCode);
PDP11.aOp00Xn_1140[(opCode >> 4) & 0xf].call(this, opCode);
};
/**
* op000X_1145(opCode)
* op000X_1140(opCode)
*
* @this {CPUStatePDP11}
* @param {number} opCode
*/
PDP11.op000X_1145 = function(opCode)
PDP11.op000X_1140 = function(opCode)
{
PDP11.aOp000X_1145[opCode & 0xf].call(this, opCode);
PDP11.aOp000X_1140[opCode & 0xf].call(this, opCode);
};
/**
* op7Xnn_1145(opCode)
* op7Xnn_1140(opCode)
*
* @this {CPUStatePDP11}
* @param {number} opCode
*/
PDP11.op7Xnn_1145 = function(opCode)
PDP11.op7Xnn_1140 = function(opCode)
{
PDP11.aOp7Xnn_1145[(opCode >> 8) & 0xf].call(this, opCode);
PDP11.aOp7Xnn_1140[(opCode >> 8) & 0xf].call(this, opCode);
};
/**
* op8Xnn_1145(opCode)
* op8Xnn_1140(opCode)
*
* @this {CPUStatePDP11}
* @param {number} opCode
*/
PDP11.op8Xnn_1145 = function(opCode)
PDP11.op8Xnn_1140 = function(opCode)
{
PDP11.aOp8Xnn_1145[(opCode >> 8) & 0xf].call(this, opCode);
PDP11.aOp8Xnn_1140[(opCode >> 8) & 0xf].call(this, opCode);
};
/**
* op8DXn_1145(opCode)
* op8DXn_1140(opCode)
*
* @this {CPUStatePDP11}
* @param {number} opCode
*/
PDP11.op8DXn_1145 = function(opCode)
PDP11.op8DXn_1140 = function(opCode)
{
PDP11.aOp8DXn_1145[(opCode >> 6) & 0x3].call(this, opCode);
if (this.model < PDP11.MODEL_1145) {
PDP11.opUndefined.call(this, opCode);
return;
}
PDP11.aOp8DXn_1140[(opCode >> 6) & 0x3].call(this, opCode);
};
PDP11.aOpXnnn_1145 = [
PDP11.op0Xnn_1145, // 0x0nnn
PDP11.aOpXnnn_1140 = [
PDP11.op0Xnn_1140, // 0x0nnn
PDP11.opMOV, // 0x1nnn 01SSDD 11/20+ 2.3
PDP11.opCMP, // 0x2nnn 02SSDD 11/20+ 2.3*
PDP11.opBIT, // 0x3nnn 03SSDD 11/20+ 2.9*
PDP11.opBIC, // 0x4nnn 04SSDD 11/20+ 2.9
PDP11.opBIS, // 0x5nnn 05SSDD 11/20+ 2.3
PDP11.opADD, // 0x6nnn 06SSDD 11/20+ 2.3
PDP11.op7Xnn_1145, // 0x7nnn
PDP11.op8Xnn_1145, // 0x8nnn
PDP11.op7Xnn_1140, // 0x7nnn
PDP11.op8Xnn_1140, // 0x8nnn
PDP11.opMOVB, // 0x9nnn 11SSDD 11/20+ 2.3
PDP11.opCMPB, // 0xAnnn 12SSDD 11/20+ 2.3
PDP11.opBITB, // 0xBnnn 13SSDD 11/20+ 2.9
@ -2323,8 +2336,8 @@ PDP11.aOpXnnn_1145 = [
PDP11.opUndefined // 0xFnnn
];
PDP11.aOp0Xnn_1145 = [
PDP11.op00Xn_1145, // 0x00nn
PDP11.aOp0Xnn_1140 = [
PDP11.op00Xn_1140, // 0x00nn
PDP11.opBR, // 0x01nn 0004XX 11/20+ 2.6
PDP11.opBNE, // 0x02nn 0010XX 11/20+ 2.6**
PDP11.opBEQ, // 0x03nn 0014XX 11/20+ 2.6**
@ -2337,20 +2350,20 @@ PDP11.aOp0Xnn_1145 = [
PDP11.op0AXn_1120, // 0x0Ann
PDP11.op0BXn_1120, // 0x0Bnn
PDP11.op0CXn_1120, // 0x0Cnn
PDP11.op0DXn_1145, // 0x0Dnn
PDP11.op0DXn_1140, // 0x0Dnn
PDP11.opUndefined, // 0x0Enn
PDP11.opUndefined // 0x0Fnn
];
PDP11.aOp0DXn_1145 = [
PDP11.opMARK, // 0x0D0n 11/45+
PDP11.opMFPI, // 0x0D4n 11/45+
PDP11.opMTPI, // 0x0D8n 11/45+
PDP11.opSXT // 0x0DCn 11/45+
PDP11.aOp0DXn_1140 = [
PDP11.opMARK, // 0x0D0n 11/40+ LEIS
PDP11.opMFPI, // 0x0D4n 11/40+
PDP11.opMTPI, // 0x0D8n 11/40+
PDP11.opSXT // 0x0DCn 11/40+ LEIS
];
PDP11.aOp00Xn_1145 = [
PDP11.op000X_1145, // 0x000n 000000-000017
PDP11.aOp00Xn_1140 = [
PDP11.op000X_1140, // 0x000n 000000-000017
PDP11.opUndefined, // 0x001n 000020-000037
PDP11.opUndefined, // 0x002n 000040-000057
PDP11.opUndefined, // 0x003n 000060-000077
@ -2368,14 +2381,14 @@ PDP11.aOp00Xn_1145 = [
PDP11.opSWAB // 0x00Fn 0003DD 11/20+ 2.3
];
PDP11.aOp000X_1145 = [
PDP11.aOp000X_1140 = [
PDP11.opHALT, // 0x0000 000000 11/20+ 1.8
PDP11.opWAIT, // 0x0001 000001 11/20+ 1.8
PDP11.opRTI, // 0x0002 000002 11/20+ 4.8
PDP11.opBPT, // 0x0003 000003
PDP11.opIOT, // 0x0004 000004 11/20+ 9.3
PDP11.opRESET, // 0x0005 000005 11/20+ 20ms
PDP11.opRTT, // 0x0006 000006 11/45+
PDP11.opRTT, // 0x0006 000006 11/40+ LEIS
PDP11.opMFPT, // 0x0007 000007 TBD
PDP11.opUndefined, // 0x0008
PDP11.opUndefined, // 0x0009
@ -2387,26 +2400,26 @@ PDP11.aOp000X_1145 = [
PDP11.opUndefined // 0x000F
];
PDP11.aOp7Xnn_1145 = [
PDP11.opMUL, // 0x70nn 11/45+
PDP11.opMUL, // 0x71nn 11/45+
PDP11.opDIV, // 0x72nn 11/45+
PDP11.opDIV, // 0x73nn 11/45+
PDP11.opASH, // 0x74nn 11/45+
PDP11.opASH, // 0x75nn 11/45+
PDP11.opASHC, // 0x76nn 11/45+
PDP11.opASHC, // 0x77nn 11/45+
PDP11.opXOR, // 0x78nn 11/45+
PDP11.opXOR, // 0x79nn 11/45+
PDP11.aOp7Xnn_1140 = [
PDP11.opMUL, // 0x70nn 11/40+ EIS
PDP11.opMUL, // 0x71nn 11/40+ EIS
PDP11.opDIV, // 0x72nn 11/40+ EIS
PDP11.opDIV, // 0x73nn 11/40+ EIS
PDP11.opASH, // 0x74nn 11/40+ EIS
PDP11.opASH, // 0x75nn 11/40+ EIS
PDP11.opASHC, // 0x76nn 11/40+ EIS
PDP11.opASHC, // 0x77nn 11/40+ EIS
PDP11.opXOR, // 0x78nn 11/40+ LEIS
PDP11.opXOR, // 0x79nn 11/40+ LEIS
PDP11.opUndefined, // 0x7Ann
PDP11.opUndefined, // 0x7Bnn
PDP11.opUndefined, // 0x7Cnn
PDP11.opUndefined, // 0x7Dnn
PDP11.opSOB, // 0x7Enn 11/45+
PDP11.opSOB // 0x7Fnn 11/45+
PDP11.opSOB, // 0x7Enn 11/40+ LEIS
PDP11.opSOB // 0x7Fnn 11/40+ LEIS
];
PDP11.aOp8Xnn_1145 = [
PDP11.aOp8Xnn_1140 = [
PDP11.opBPL, // 0x80nn 1000XX 11/20+ 2.6**
PDP11.opBMI, // 0x81nn 1004XX 11/20+ 2.6**
PDP11.opBHI, // 0x82nn 1010XX 11/20+ 2.6**
@ -2420,12 +2433,12 @@ PDP11.aOp8Xnn_1145 = [
PDP11.op8AXn_1120, // 0x8Ann
PDP11.op8BXn_1120, // 0x8Bnn
PDP11.op8CXn_1120, // 0x8Cnn
PDP11.op8DXn_1145, // 0x8Dnn
PDP11.op8DXn_1140, // 0x8Dnn
PDP11.opUndefined, // 0x8Enn
PDP11.opUndefined // 0x8Fnn
];
PDP11.aOp8DXn_1145 = [
PDP11.aOp8DXn_1140 = [
PDP11.opUndefined, // 0x8D0n
PDP11.opMFPD, // 0x8D4n 11/45+
PDP11.opMTPD, // 0x8D8n 11/45+

16
modules/pdp11/lib/cpustate.js
View file

@ -154,10 +154,14 @@ class CPUStatePDP11 extends CPUPDP11 {
this.pswUsed = ~(PDP11.PSW.UNUSED | PDP11.PSW.REGSET | PDP11.PSW.PMODE | PDP11.PSW.CMODE) & 0xffff;
this.pswRegSet = 0;
} else {
this.decode = PDP11.op1145.bind(this);
this.checkStackLimit = this.checkStackLimit1145;
this.pswUsed = ~(PDP11.PSW.UNUSED | (this.model < PDP11.MODEL_1145? PDP11.PSW.REGSET : 0)) & 0xffff;
this.pswRegSet = (this.model >= PDP11.MODEL_1145? PDP11.PSW.REGSET : 0);
this.decode = PDP11.op1140.bind(this);
this.checkStackLimit = this.checkStackLimit1140;
/*
* The alternate register set (REGSET) doesn't exist on the 11/20 or 11/40; it's available on the 11/45 and 11/70.
* Ditto for separate I/D spaces, SUPER mode, and the instructions MFPD, MTPD, and SPL.
*/
this.pswUsed = ~(PDP11.PSW.UNUSED | (this.model <= PDP11.MODEL_1140? PDP11.PSW.REGSET : 0)) & 0xffff;
this.pswRegSet = (this.model > PDP11.MODEL_1140? PDP11.PSW.REGSET : 0);
}
this.nDisableTraps = 0;
@ -2146,14 +2150,14 @@ class CPUStatePDP11 extends CPUPDP11 {
}
/**
* checkStackLimit1145(access, step, addr)
* checkStackLimit1140(access, step, addr)
*
* @this {CPUStatePDP11}
* @param {number} access
* @param {number} step
* @param {number} addr
*/
checkStackLimit1145(access, step, addr)
checkStackLimit1140(access, step, addr)
{
if (!this.pswMode) {
/*

21
modules/pdp11/lib/debugger.js
View file

@ -304,7 +304,12 @@ class DebuggerPDP11 extends Debugger {
var sMessages = cmp.getMachineParm('messages');
if (sMessages) this.messageInit(sMessages);
if (this.cpu.model < PDP11.MODEL_1145) this.aOpReserved = DebuggerPDP11.OP1145;
if (this.cpu.model < PDP11.MODEL_1140) {
this.aOpReserved = this.aOpReserved.concat(DebuggerPDP11.OP1140);
}
if (this.cpu.model < PDP11.MODEL_1145) {
this.aOpReserved = this.aOpReserved.concat(DebuggerPDP11.OP1145);
}
this.messageDump(MessagesPDP11.BUS, function onDumpBus(asArgs) { dbg.dumpBus(asArgs); });
@ -4348,21 +4353,27 @@ if (DEBUGGER) {
DebuggerPDP11.OPNONE = [DebuggerPDP11.OPS.NONE];
/*
* Table of opcodes specific to the 11/45 and newer
* Table of opcodes added to the 11/40 and newer
*/
DebuggerPDP11.OP1145 = [
DebuggerPDP11.OP1140 = [
DebuggerPDP11.OPS.MARK,
DebuggerPDP11.OPS.MFPI,
DebuggerPDP11.OPS.MTPI,
DebuggerPDP11.OPS.SXT,
DebuggerPDP11.OPS.SPL,
DebuggerPDP11.OPS.RTT,
DebuggerPDP11.OPS.MUL,
DebuggerPDP11.OPS.DIV,
DebuggerPDP11.OPS.ASH,
DebuggerPDP11.OPS.ASHC,
DebuggerPDP11.OPS.XOR,
DebuggerPDP11.OPS.SOB,
DebuggerPDP11.OPS.SOB
];
/*
* Table of opcodes added to the 11/45 and newer
*/
DebuggerPDP11.OP1145 = [
DebuggerPDP11.OPS.SPL,
DebuggerPDP11.OPS.MFPD,
DebuggerPDP11.OPS.MTPD
];

29
modules/pdp11/lib/defines.js
View file

@ -131,8 +131,9 @@ var PDP11 = {
* The 11/40 added the MODE bits to the PSW (but only KERNEL=00 and USER=11) and 18-bit
* addressing via an MMU; there was still only one register set.
*
* The 11/45 added REGSET bit to the PSW (along with the second register set), and added
* SUPERVISOR=01 to the set of modes.
* The 11/45 added REGSET bit to the PSW (to support a second register set), SUPER=01
* mode to the existing KERNEL=00 and USER=11 modes, separate I/D spaces, and other MMU
* extensions (eg, MMR1 and MMR3).
*
* The 11/70 added 22-bit addressing and corresponding extensions to the MMU.
*/
@ -163,10 +164,10 @@ var PDP11 = {
* Processor modes
*/
MODE: {
KERNEL: 0x0, // 11/40 and higher only
SUPER: 0x1, // 11/45 and higher only
KERNEL: 0x0, // 11/40 and higher
SUPER: 0x1, // 11/45 and higher
UNUSED: 0x2,
USER: 0x3, // 11/40 and higher only
USER: 0x3, // 11/40 and higher
MASK: 0x3
},
/*
@ -364,14 +365,14 @@ var PDP11 = {
MMR0: { // 177572
ENABLED: 0x0001, // 000001 address relocation enabled
PAGE_NUM: 0x000E, // 000016 page number of last fault
PAGE_D: 0x0010, // 000020 last fault occurred in D space (11/44 and 11/70 only)
PAGE_D: 0x0010, // 000020 last fault occurred in D space (11/45 and 11/70)
PAGE: 0x001E, // 000176 (all of the PAGE bits)
MODE: 0x0060, // 000140 processor mode as of last fault
COMPLETED: 0x0080, // 000200 last instruction completed (R/O) (11/70 only)
COMPLETED: 0x0080, // 000200 last instruction completed (R/O) (11/70)
MAINT: 0x0100, // 000400 only destination mode references will be relocated
MMU_TRAPS: 0x0200, // 001000 enable MMU traps (11/70 only)
MMU_TRAPS: 0x0200, // 001000 enable MMU traps (11/70)
UNUSED: 0x0C00, // 006000
TRAP_MMU: 0x1000, // 010000 trap: MMU (11/70 only)
TRAP_MMU: 0x1000, // 010000 trap: MMU (11/70)
ABORT_RO: 0x2000, // 020000 abort: read-only
ABORT_PL: 0x4000, // 040000 abort: page length
ABORT_NR: 0x8000, // 100000 abort: non-resident
@ -382,7 +383,7 @@ var PDP11 = {
MODE: 5
}
},
MMR1: { // 177574: general purpose auto-inc/auto-dec register (11/44 and 11/70 only)
MMR1: { // 177574: general purpose auto-inc/auto-dec register (11/45 and 11/70)
REG1_NUM: 0x0007, //
REG1_DELTA: 0x00F8, //
REG2_NUM: 0x0700, //
@ -390,7 +391,7 @@ var PDP11 = {
},
MMR2: { // 177576: virtual program counter register
},
MMR3: { // 172516: mapping register (11/44 and 11/70 only)
MMR3: { // 172516: mapping register (11/45 and 11/70)
USER_D: 0x0001, // (000001)
SUPER_D: 0x0002, // (000002)
KERNEL_D: 0x0004, // (000004)
@ -400,11 +401,11 @@ var PDP11 = {
PDR: {
ACF: {
NR: 0x0, // non-resident, abort all accesses
RO1: 0x1, // read-only, abort on write attempt, memory management trap on read (11/70 only)
RO1: 0x1, // read-only, abort on write attempt, memory management trap on read (11/70)
RO: 0x2, // read-only, abort on write attempt
U1: 0x3, // unused, abort all accesses--reserved for future use
RW1: 0x4, // read/write, memory management trap upon completion of a read or write
RW2: 0x5, // read/write, memory management trap upon completion of a write (11/70 only)
RW2: 0x5, // read/write, memory management trap upon completion of a write (11/70)
RW: 0x6, // read/write, no system trap/abort action
U2: 0x7, // unused, abort all accesses--reserved for future use
MASK: 0x7
@ -412,7 +413,7 @@ var PDP11 = {
ED: 0x0008, // expansion direction (if set, the page expands downward from block number 127)
UNUSED: 0x0030,
MODIFIED: 0x0040, // page has been written (bit cleared when either PDR or PAR is written)
ACCESSED: 0x0080, // page has been accessed (bit cleared when either PDR or PAR is written) (11/70 only)
ACCESSED: 0x0080, // page has been accessed (bit cleared when either PDR or PAR is written) (11/70)
PLF: 0x7F00, // page length field
BC: 0x8000 // bypass cache (11/44 only)
},

12
modules/pdp11/lib/device.js
View file

@ -1143,18 +1143,18 @@ DevicePDP11.UNIBUS_IOTABLE = {
[PDP11.UNIBUS.SDPDR0]: /* 172220 */ [null, null, DevicePDP11.prototype.readSDPDR, DevicePDP11.prototype.writeSDPDR, "SDPDR", 8, PDP11.MODEL_1145, MessagesPDP11.MMU],
[PDP11.UNIBUS.SIPAR0]: /* 172240 */ [null, null, DevicePDP11.prototype.readSIPAR, DevicePDP11.prototype.writeSIPAR, "SIPAR", 8, PDP11.MODEL_1145, MessagesPDP11.MMU],
[PDP11.UNIBUS.SDPAR0]: /* 172260 */ [null, null, DevicePDP11.prototype.readSDPAR, DevicePDP11.prototype.writeSDPAR, "SDPAR", 8, PDP11.MODEL_1145, MessagesPDP11.MMU],
[PDP11.UNIBUS.KIPDR0]: /* 172300 */ [null, null, DevicePDP11.prototype.readKIPDR, DevicePDP11.prototype.writeKIPDR, "KIPDR", 8, PDP11.MODEL_1145, MessagesPDP11.MMU],
[PDP11.UNIBUS.KIPDR0]: /* 172300 */ [null, null, DevicePDP11.prototype.readKIPDR, DevicePDP11.prototype.writeKIPDR, "KIPDR", 8, PDP11.MODEL_1140, MessagesPDP11.MMU],
[PDP11.UNIBUS.KDPDR0]: /* 172320 */ [null, null, DevicePDP11.prototype.readKDPDR, DevicePDP11.prototype.writeKDPDR, "KDPDR", 8, PDP11.MODEL_1145, MessagesPDP11.MMU],
[PDP11.UNIBUS.KIPAR0]: /* 172340 */ [null, null, DevicePDP11.prototype.readKIPAR, DevicePDP11.prototype.writeKIPAR, "KIPAR", 8, PDP11.MODEL_1145, MessagesPDP11.MMU],
[PDP11.UNIBUS.KIPAR0]: /* 172340 */ [null, null, DevicePDP11.prototype.readKIPAR, DevicePDP11.prototype.writeKIPAR, "KIPAR", 8, PDP11.MODEL_1140, MessagesPDP11.MMU],
[PDP11.UNIBUS.KDPAR0]: /* 172360 */ [null, null, DevicePDP11.prototype.readKDPAR, DevicePDP11.prototype.writeKDPAR, "KDPAR", 8, PDP11.MODEL_1145, MessagesPDP11.MMU],
[PDP11.UNIBUS.MMR3]: /* 172516 */ [null, null, DevicePDP11.prototype.readMMR3, DevicePDP11.prototype.writeMMR3, "MMR3", 1, PDP11.MODEL_1145, MessagesPDP11.MMU],
[PDP11.UNIBUS.LKS]: /* 177546 */ [null, null, DevicePDP11.prototype.readLKS, DevicePDP11.prototype.writeLKS, "LKS"],
[PDP11.UNIBUS.MMR0]: /* 177572 */ [null, null, DevicePDP11.prototype.readMMR0, DevicePDP11.prototype.writeMMR0, "MMR0", 1, PDP11.MODEL_1145, MessagesPDP11.MMU],
[PDP11.UNIBUS.MMR0]: /* 177572 */ [null, null, DevicePDP11.prototype.readMMR0, DevicePDP11.prototype.writeMMR0, "MMR0", 1, PDP11.MODEL_1140, MessagesPDP11.MMU],
[PDP11.UNIBUS.MMR1]: /* 177574 */ [null, null, DevicePDP11.prototype.readMMR1, DevicePDP11.prototype.writeIgnored, "MMR1", 1, PDP11.MODEL_1145, MessagesPDP11.MMU],
[PDP11.UNIBUS.MMR2]: /* 177576 */ [null, null, DevicePDP11.prototype.readMMR2, DevicePDP11.prototype.writeIgnored, "MMR2", 1, PDP11.MODEL_1145, MessagesPDP11.MMU],
[PDP11.UNIBUS.UIPDR0]: /* 177600 */ [null, null, DevicePDP11.prototype.readUIPDR, DevicePDP11.prototype.writeUIPDR, "UIPDR", 8, PDP11.MODEL_1145, MessagesPDP11.MMU],
[PDP11.UNIBUS.MMR2]: /* 177576 */ [null, null, DevicePDP11.prototype.readMMR2, DevicePDP11.prototype.writeIgnored, "MMR2", 1, PDP11.MODEL_1140, MessagesPDP11.MMU],
[PDP11.UNIBUS.UIPDR0]: /* 177600 */ [null, null, DevicePDP11.prototype.readUIPDR, DevicePDP11.prototype.writeUIPDR, "UIPDR", 8, PDP11.MODEL_1140, MessagesPDP11.MMU],
[PDP11.UNIBUS.UDPDR0]: /* 177620 */ [null, null, DevicePDP11.prototype.readUDPDR, DevicePDP11.prototype.writeUDPDR, "UDPDR", 8, PDP11.MODEL_1145, MessagesPDP11.MMU],
[PDP11.UNIBUS.UIPAR0]: /* 177640 */ [null, null, DevicePDP11.prototype.readUIPAR, DevicePDP11.prototype.writeUIPAR, "UIPAR", 8, PDP11.MODEL_1145, MessagesPDP11.MMU],
[PDP11.UNIBUS.UIPAR0]: /* 177640 */ [null, null, DevicePDP11.prototype.readUIPAR, DevicePDP11.prototype.writeUIPAR, "UIPAR", 8, PDP11.MODEL_1140, MessagesPDP11.MMU],
[PDP11.UNIBUS.UDPAR0]: /* 177660 */ [null, null, DevicePDP11.prototype.readUDPAR, DevicePDP11.prototype.writeUDPAR, "UDPAR", 8, PDP11.MODEL_1145, MessagesPDP11.MMU],
[PDP11.UNIBUS.R0SET0]: /* 177700 */ [null, null, DevicePDP11.prototype.readRSET0, DevicePDP11.prototype.writeRSET0, "R0SET0"],
[PDP11.UNIBUS.R1SET0]: /* 177701 */ [null, null, DevicePDP11.prototype.readRSET0, DevicePDP11.prototype.writeRSET0, "R1SET0"],

2
modules/pdp11/lib/panel.js
View file

@ -845,7 +845,7 @@ class PanelPDP11 extends Component {
*/
advanceAddr()
{
var nRegs = this.cpu.model < PDP11.MODEL_1145? 8 : 16;
var nRegs = this.cpu.model <= PDP11.MODEL_1140? 8 : 16;
var fGenRegs = (this.regAddr >= PDP11.UNIBUS.R0SET0 /*177700*/ && this.regAddr < PDP11.UNIBUS.R0SET0 + nRegs);
var inc = fGenRegs? 1 : 2;
var mask = fGenRegs? 0xf : this.bus.nBusMask;