Attempted to clean up mapUnibus() and bus-related faults; how well or ill-advised these changes are remains to be seen
This commit is contained in:
Jeff
Jeff Parsons
parent
96ad4ec37e
commit
daefc2992c
41 changed files with 1454 additions and 1476 deletions
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@ -84,39 +84,19 @@ function BusPDP11(parmsBus, cpu, dbg)
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this.realIOPageBlocks = null; // this saves the memory blocks allocated for IOPAGE, so we can reuse them
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/*
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* Compute all BusPDP11 memory block parameters, based on the width of the bus. The entire
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* address space is divided into blocks, using a block size that is (hopefully) appropriate to
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* the bus width. The following table summarizes our (original) simplistic calculations:
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* Compute all BusPDP11 memory block parameters now, based on the width of the bus.
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*
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* Bus Width Block Shift Block Size
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* --------- ----------- ----------
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* 16 bits (64Kb address space): 10 1Kb (64 maximum blocks)
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* 18 bits (256Kb address space): 11 2Kb (128 maximum blocks)
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* 20 bits (1Mb address space): 12 4Kb (256 maximum blocks)
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* 22 bits (4Mb address space): 13 8Kb (512 maximum blocks)
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* 24 bits (16Mb address space): 14 16Kb (1K maximum blocks)
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* 32 bits (4Gb address space); 15 32Kb (128K maximum blocks)
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* Note that all PCjs machines divide their address space into blocks, using a block size appropriate for
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* the machine's bus width. This allows us to efficiently allocate the entire address space, by reusing blocks
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* as appropriate, and to define to different address behaviors on a block-granular level.
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*
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* The coarser block granularities (ie, 16Kb and 32Kb) may cause problems for certain RAM and/or ROM
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* allocations that are contiguous but are allocated out of order, or that have different controller
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* requirements. Your choices, for the moment, are either to ensure the allocations are performed in
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* order, or to choose smaller nBlockShift values (at the expense of a generating a larger block array).
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* For PDPjs machines, the ideal block size is 8Kb (IOPAGE_LENGTH), the size of the IOPAGE on all PDP-11 machines;
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* as a result, our IOController functions assume that all incoming offsets are within a single 8Kb block.
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*/
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this.addrTotal = Math.pow(2, this.nBusWidth);
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this.nBusLimit = this.nBusMask = (this.addrTotal - 1) | 0;
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/*
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* WARNING: Instead of dynamically calculating nBlockShift based on nBusWidth, as described above, we
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* now force nBlockSize to IOPAGE_LENGTH, because that's what our IOController functions currently assume.
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*
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* this.nBlockShift = (this.nBusWidth >> 1) + 2;
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* if (this.nBlockShift < 10) this.nBlockShift = 10;
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* if (this.nBlockShift > 15) this.nBlockShift = 15;
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* this.nBlockSize = 1 << this.nBlockShift;
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*/
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this.nBlockSize = BusPDP11.IOPAGE_LENGTH;
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this.nBlockShift = Math.log2(this.nBlockSize); // ES6 ALERT (alternatively: Math.log(this.nBlockSize) / Math.LN2)
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this.nBlockLen = this.nBlockSize >> 2;
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this.nBlockLimit = this.nBlockSize - 1;
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this.nBlockTotal = (this.addrTotal / this.nBlockSize) | 0;
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@ -209,8 +189,8 @@ BusPDP11.IOHANDLER = {
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/*
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* These are our custom IOController functions for all IOPAGE accesses. They look up the IOPAGE
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* offset in the aIOHandlers table, and if an entry exists, they use the appropriate IOHANDLER indexes
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* (above) to locate the registered read/write handlers. If no handler is found, then unknownAccess()
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* is called, triggering a trap -- unless traps are disabled because direct access was requested
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* (above) to locate the registered read/write handlers. If no handler is found, then fault() will
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* be called, triggering a trap -- unless traps are disabled because direct access was requested
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* (eg, by the Debugger).
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*
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* Handlers receive the original IOPAGE address that was used, although in most cases, it's ignored,
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@ -282,7 +262,8 @@ BusPDP11.IOController = {
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}
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return b;
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}
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b = bus.unknownAccess(addr, true);
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bus.fault(addr, PDP11.CPUERR.TIMEOUT, PDP11.ACCESS.READ_BYTE);
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b = 0xff;
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if (DEBUGGER && this.dbg && this.dbg.messageEnabled(MessagesPDP11.BUS)) {
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this.dbg.printMessage("warning: unconverted read access to byte @" + this.dbg.toStrBase(addr) + ": " + this.dbg.toStrBase(b), true, true);
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}
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@ -355,7 +336,7 @@ BusPDP11.IOController = {
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}
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return;
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}
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bus.unknownAccess(addr, true, b);
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bus.fault(addr, PDP11.CPUERR.TIMEOUT, PDP11.ACCESS.WRITE_BYTE);
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if (DEBUGGER && this.dbg && this.dbg.messageEnabled(MessagesPDP11.BUS)) {
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this.dbg.printMessage("warning: unconverted write access to byte @" + this.dbg.toStrBase(addr) + ": " + this.dbg.toStrBase(b), true, true);
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}
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@ -387,7 +368,8 @@ BusPDP11.IOController = {
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}
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return w;
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}
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w = bus.unknownAccess(addr, false);
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bus.fault(addr, PDP11.CPUERR.TIMEOUT, PDP11.ACCESS.READ_WORD);
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w = 0xffff;
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if (DEBUGGER && this.dbg && this.dbg.messageEnabled(MessagesPDP11.BUS)) {
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this.dbg.printMessage("warning: unconverted read access to word @" + this.dbg.toStrBase(addr) + ": " + this.dbg.toStrBase(w), true, true);
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}
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@ -423,7 +405,7 @@ BusPDP11.IOController = {
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}
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return;
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}
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bus.unknownAccess(addr, false, w);
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bus.fault(addr, PDP11.CPUERR.TIMEOUT, PDP11.ACCESS.WRITE_WORD);
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if (DEBUGGER && this.dbg && this.dbg.messageEnabled(MessagesPDP11.BUS)) {
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this.dbg.printMessage("warning: unconverted write access to word @" + this.dbg.toStrBase(addr) + ": " + this.dbg.toStrBase(w), true, true);
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}
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@ -495,7 +477,7 @@ BusPDP11.prototype.setIOPageRange = function(nRange)
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BusPDP11.prototype.getControllerBuffer = function(addr)
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{
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/*
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* No buffer is required for the IOPAGE; all accesses go to registered I/O handlers or to unknownAccess().
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* No buffer is required for the IOPAGE; all accesses go to registered I/O handlers or to fault().
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*/
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return [null, 0];
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};
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@ -539,30 +521,6 @@ BusPDP11.prototype.reset = function()
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this.setIOPageRange(16);
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};
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/**
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* unknownAccess(addr, fByte, data)
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*
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* This is our default I/O handler, called when there's an IOPAGE access without a corresponding entry in aIOHandlers.
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*
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* @this {BusPDP11}
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* @param {number} addr (ie, an IOPAGE address)
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* @param {boolean} [fByte] (true if byte access, otherwise word)
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* @param {number} [data] (undefined if read, otherwise write)
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* @return {number}
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*/
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BusPDP11.prototype.unknownAccess = function(addr, fByte, data)
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{
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if (DEBUGGER && this.dbg && this.dbg.messageEnabled(MessagesPDP11.WARN)) {
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this.dbg.printMessage("warning: unknown I/O access (" + this.dbg.toStrBase(addr) + "," + this.dbg.toStrBase(data, fByte?1:2) + ")", true, true);
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this.dbg.stopInstruction();
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}
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if (!this.nDisableFaults) {
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this.cpu.regErr |= PDP11.CPUERR.TIMEOUT;
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this.cpu.trap(PDP11.TRAP.BUS_ERROR, addr);
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}
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return 0;
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};
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/**
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* powerUp(data, fRepower)
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*
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@ -910,13 +868,21 @@ BusPDP11.prototype.setMemoryBlocks = function(addr, size, aBlocks, type)
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*/
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BusPDP11.prototype.getByte = function(addr)
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{
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/*
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* If bits 18-21 of addr are all set (which is implied by addr >= BusPDP11.IOPAGE_UNIBUS aka 0x3C0000),
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* then we have a 22-bit address pointing to the top 256Kb range, so we must pass the address through the
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* UNIBUS relocation map.
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*/
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if (addr >= BusPDP11.IOPAGE_UNIBUS) {
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addr = this.cpu.mapUnibus(addr);
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}
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return this.aMemBlocks[(addr & this.nBusMask) >>> this.nBlockShift].readByte(addr & this.nBlockLimit, addr);
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};
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/**
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* getByteDirect(addr)
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*
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* This is useful for the Debugger and other components that want to bypass getByte() breakpoint detection.
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* This is useful for the Debugger and other components that want to access physical memory without side-effects.
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*
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* @this {BusPDP11}
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* @param {number} addr is a physical address
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@ -940,6 +906,14 @@ BusPDP11.prototype.getByteDirect = function(addr)
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*/
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BusPDP11.prototype.getWord = function(addr)
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{
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/*
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* If bits 18-21 of addr are all set (which is implied by addr >= BusPDP11.IOPAGE_UNIBUS aka 0x3C0000),
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* then we have a 22-bit address pointing to the top 256Kb range, so we must pass the address through the
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* UNIBUS relocation map.
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*/
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if (addr >= BusPDP11.IOPAGE_UNIBUS) {
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addr = this.cpu.mapUnibus(addr);
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}
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var off = addr & this.nBlockLimit;
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var iBlock = (addr & this.nBusMask) >>> this.nBlockShift;
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if (!PDP11.WORDBUS && off == this.nBlockLimit) {
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@ -982,6 +956,14 @@ BusPDP11.prototype.getWordDirect = function(addr)
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*/
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BusPDP11.prototype.setByte = function(addr, b)
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{
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/*
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* If bits 18-21 of addr are all set (which is implied by addr >= BusPDP11.IOPAGE_UNIBUS aka 0x3C0000),
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* then we have a 22-bit address pointing to the top 256Kb range, so we must pass the address through the
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* UNIBUS relocation map.
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*/
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if (addr >= BusPDP11.IOPAGE_UNIBUS) {
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addr = this.cpu.mapUnibus(addr);
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}
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this.aMemBlocks[(addr & this.nBusMask) >>> this.nBlockShift].writeByte(addr & this.nBlockLimit, b & 0xff, addr);
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};
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@ -1012,6 +994,14 @@ BusPDP11.prototype.setByteDirect = function(addr, b)
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*/
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BusPDP11.prototype.setWord = function(addr, w)
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{
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/*
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* If bits 18-21 of addr are all set (which is implied by addr >= BusPDP11.IOPAGE_UNIBUS aka 0x3C0000),
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* then we have a 22-bit address pointing to the top 256Kb range, so we must pass the address through the
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* UNIBUS relocation map.
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*/
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if (addr >= BusPDP11.IOPAGE_UNIBUS) {
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addr = this.cpu.mapUnibus(addr);
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}
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var off = addr & this.nBlockLimit;
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var iBlock = (addr & this.nBusMask) >>> this.nBlockShift;
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if (!PDP11.WORDBUS && off == this.nBlockLimit) {
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@ -1215,12 +1205,13 @@ BusPDP11.prototype.addIOTable = function(component, table)
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* Don't install (ie, ignore) handlers for I/O addresses that are defined with a model number
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* that is "greater than" than the current model.
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*/
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if (afn[5] && afn[5] > this.cpu.model) continue;
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if (afn[6] && afn[6] > this.cpu.model) continue;
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var fnReadByte = afn[0]? afn[0].bind(component) : null;
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var fnWriteByte = afn[1]? afn[1].bind(component) : null;
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var fnReadWord = afn[2]? afn[2].bind(component) : null;
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var fnWriteWord = afn[3]? afn[3].bind(component) : null;
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var nRegs = afn[5] || 1;
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/*
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* As discussed in the IOController comments above, when handlers are being registered for the following
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@ -1242,7 +1233,12 @@ BusPDP11.prototype.addIOTable = function(component, table)
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}(fnWriteWord);
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}
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}
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this.addIOHandlers(addr, addr, fnReadByte, fnWriteByte, fnReadWord, fnWriteWord, afn[4]);
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var sReg = afn[4];
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for (var iReg = 0; iReg < nRegs; iReg++, addr += 2) {
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if (sReg && nRegs > 1) sReg = afn[4] + iReg;
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this.addIOHandlers(addr, addr, fnReadByte, fnWriteByte, fnReadWord, fnWriteWord, sReg);
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}
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}
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};
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@ -1258,24 +1254,26 @@ BusPDP11.prototype.addResetHandler = function(fnReset)
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};
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/**
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* fault(addr, access)
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* fault(addr, err, access)
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*
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* Memory interface for signaling alignment errors, invalid memory
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* Bus interface for signaling alignment errors, invalid memory, etc.
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*
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* @this {BusPDP11}
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* @param {number} addr
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* @param {number} [err]
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* @param {number} [access] (for diagnostic purposes only)
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*/
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BusPDP11.prototype.fault = function(addr, access)
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BusPDP11.prototype.fault = function(addr, err, access)
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{
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this.fFault = true;
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if (!this.nDisableFaults) {
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if (DEBUGGER && this.dbg && this.dbg.messageEnabled(MessagesPDP11.BUS)) {
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this.dbg.printMessage("memory fault (" + access + ") on address " + this.dbg.toStrBase(addr), true, true);
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this.dbg.stopInstruction();
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}
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if (err) this.cpu.regErr |= err;
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this.cpu.trap(PDP11.TRAP.BUS_ERROR, addr);
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}
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this.fFault = true;
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};
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/**
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@ -200,7 +200,6 @@ CPUStatePDP11.prototype.initRegs = function()
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[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] // user 3
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];
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this.unibusMap = [ // 32 unibus map registers
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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];
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this.regsControl = [ // various control registers (177740-177756) we don't really care about
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@ -242,10 +241,7 @@ CPUStatePDP11.prototype.resetRegs = function()
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this.regMMR3 = 0; // 172516
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this.mmuEnable = 0; // MMU enabled for PDP11.ACCESS.READ or PDP11.ACCESS.WRITE
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this.mmuLastMode = 0;
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this.mmuMask = 0x3ffff;
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this.mmuMemorySize = BusPDP11.IOPAGE_18BIT;
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this.resetTriggers();
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if (this.bus) this.setMemoryAccess();
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@ -359,13 +355,7 @@ CPUStatePDP11.prototype.setMMR3 = function(newMMR3)
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}
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if (this.regMMR3 != newMMR3) {
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this.regMMR3 = newMMR3;
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if (newMMR3 & PDP11.MMR3.MMU_22BIT) {
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this.mmuMask = 0x3fffff;
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this.mmuMemorySize = BusPDP11.MAX_MEMORY;
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} else {
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this.mmuMask = 0x3ffff;
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this.mmuMemorySize = BusPDP11.IOPAGE_18BIT;
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}
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this.mmuMask = (newMMR3 & PDP11.MMR3.MMU_22BIT)? 0x3fffff : 0x3ffff;
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this.setMemoryAccess();
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}
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};
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@ -1242,24 +1232,45 @@ CPUStatePDP11.prototype.getTrapStatus = function()
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};
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/**
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* mapUnibus(unibusAddress)
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* mapUnibus(addr)
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*
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* If bits 18-21 of addr are all set (which is implied by addr >= BusPDP11.IOPAGE_UNIBUS aka 0x3C0000),
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* then we have a 22-bit address pointing to the top 256Kb range, so if the UNIBUS relocation map is enabled,
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* we must pass the lower 18 bits of that address through the map.
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*
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* Since mapUnibus() only looks at the low 18 bits of addr, there's no need to mask addr first. Note that
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* if bits 13-17 are all set, then the 18-bit address points to the top 8Kb of its 256Kb range, and mapUnibus()
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* will return addr unchanged, since it should already be pointing to the top 8Kb of the 4Mb 22-bit range.
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*
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* From the PDP-11/70 Handbook:
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*
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* On the 11/44 and 11/70, there are a total of 31 mapping registers for address relocation. Each register is
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* composed of a double 16-bit PDP-11 word (in consecutive locations) that holds the 22-bit base address. These
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* registers have UNIBUS addresses in the range 770200 to 770372.
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*
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* If the UNIBUS map relocation is not enabled, an incoming 18-bit UNIBUS address has 4 leading zeroes added for
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* referencing a 22-bit physical address. The lower 18 bits are the same. No relocation is performed.
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*
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* If UNIBUS map relocation is enabled, the five high order bits of the UNIBUS address are used to select one of the
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* 31 mapping registers. The low-order 13 bits of the incoming address are used as an offset from the base address
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* contained in the 22-bit mapping register. To form the physical address, the 13 low-order bits of the UNIBUS
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* address are added to 22 bits of the selected mapping register to produce the 22-bit physical address. The lowest
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* order bit of all mapping registers is always a zero, since relocation is always on word boundaries.
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*
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* @this {CPUStatePDP11}
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* @param {number} unibusAddress
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* @param {number} addr
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* @return {number}
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*/
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CPUStatePDP11.prototype.mapUnibus = function(unibusAddress)
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CPUStatePDP11.prototype.mapUnibus = function(addr)
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{
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var idx = (unibusAddress >> 13) & 0x1f;
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var idx = (addr >> 13) & 0x1f;
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if (idx < 31) {
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if (this.regMMR3 & PDP11.MMR3.UNIBUS_MAP) {
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unibusAddress = (this.unibusMap[idx] + (unibusAddress & 0x1ffe)) & 0x3ffffe;
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if (unibusAddress >= BusPDP11.IOPAGE_UNIBUS && unibusAddress < BusPDP11.IOPAGE_22BIT) this.panic(898);
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addr = (this.unibusMap[idx] + (addr & 0x1ffe)) & 0x3ffffe;
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if (addr >= BusPDP11.IOPAGE_UNIBUS && addr < BusPDP11.IOPAGE_22BIT) this.panic(898);
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}
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} else {
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unibusAddress |= BusPDP11.IOPAGE_22BIT;
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}
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return unibusAddress;
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return addr;
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};
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/**
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@ -1287,8 +1298,8 @@ CPUStatePDP11.prototype.mapUnibus = function(unibusAddress)
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* A PDP 11/70 is different to other PDP 11's in that the highest 18 bit space (017000000 & above)
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* maps directly to UNIBUS space - including low memory. This doesn't appear to be particularly
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* useful as it restricts maximum system memory - although it does appear to allow software
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* testing of the unibus map. This feature also appears to confuse some OSes which test consecutive
|
||||
* memory locations to find maximum memory - and on a full memory system find themselves accessing
|
||||
* testing of the unibus map. This feature also appears to confuse some OSes which test consecutive
|
||||
* memory locations to find maximum memory -- and on a full memory system find themselves accessing
|
||||
* low memory again at high addresses.
|
||||
*
|
||||
* 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 MMR0
|
||||
|
|
@ -1318,26 +1329,6 @@ CPUStatePDP11.prototype.mapVirtualToPhysical = function(virtualAddress, accessFl
|
|||
pdr = this.mmuPDR[this.mmuMode][page];
|
||||
physicalAddress = ((this.mmuPAR[this.mmuMode][page] << 6) + (virtualAddress & 0x1fff)) & this.mmuMask;
|
||||
|
||||
if (physicalAddress < this.mmuMemorySize) {
|
||||
if ((physicalAddress & 1) && !(accessFlags & PDP11.ACCESS.BYTE)) {
|
||||
this.regErr |= PDP11.CPUERR.ODDADDR;
|
||||
this.trap(PDP11.TRAP.BUS_ERROR, PDP11.REASON.ODDMEMADDR);
|
||||
}
|
||||
} else {
|
||||
if (!(this.regMMR3 & 0x10)) {
|
||||
if (physicalAddress >= BusPDP11.IOPAGE_18BIT) physicalAddress |= BusPDP11.IOPAGE_22BIT;
|
||||
}
|
||||
if (physicalAddress < BusPDP11.IOPAGE_22BIT) {
|
||||
if (physicalAddress >= BusPDP11.IOPAGE_UNIBUS) {
|
||||
physicalAddress = this.mapUnibus(physicalAddress & 0x3ffff); // 18bit unibus space
|
||||
}
|
||||
if (physicalAddress >= this.mmuMemorySize && physicalAddress < BusPDP11.IOPAGE_22BIT) {
|
||||
this.regErr |= PDP11.CPUERR.NOMEMORY;
|
||||
this.trap(PDP11.TRAP.BUS_ERROR, PDP11.REASON.NOMEMORY); // KB11-EM does this after ABORT handling - KB11-CM before
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
switch (pdr & 0x7) {
|
||||
case 1: // read-only with trap
|
||||
errorMask = 0x1000; // MMU trap
|
||||
|
|
@ -1365,18 +1356,19 @@ CPUStatePDP11.prototype.mapVirtualToPhysical = function(virtualAddress, accessFl
|
|||
}
|
||||
|
||||
if ((pdr & 0x7f08) !== 0x7f00) { // skip checking most common case (hopefully)
|
||||
if (pdr & 0x8) { // expand downwards
|
||||
if (pdr & 0x8) { // expand downwards
|
||||
if (pdr & 0x7f00) {
|
||||
if ((virtualAddress & 0x1fc0) < ((pdr >> 2) & 0x1fc0)) {
|
||||
errorMask |= 0x4000; // page length error abort
|
||||
}
|
||||
}
|
||||
} else { // expand upwards
|
||||
} else { // expand upwards
|
||||
if ((virtualAddress & 0x1fc0) > ((pdr >> 2) & 0x1fc0)) {
|
||||
errorMask |= 0x4000; // page length error abort
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// aborts and traps: log FIRST trap and MOST RECENT abort
|
||||
|
||||
this.mmuPDR[this.mmuMode][page] = pdr;
|
||||
|
|
@ -1384,13 +1376,15 @@ CPUStatePDP11.prototype.mapVirtualToPhysical = function(virtualAddress, accessFl
|
|||
this.mmuLastMode = this.mmuMode;
|
||||
this.mmuLastPage = page;
|
||||
}
|
||||
|
||||
var fTrap = false;
|
||||
if (errorMask) {
|
||||
if (errorMask & 0xe000) {
|
||||
if (this.trapPSW >= 0) errorMask |= 0x80; // Instruction complete
|
||||
if (!(this.regMMR0 & 0xe000)) {
|
||||
this.regMMR0 |= errorMask | (this.mmuLastMode << 5) | (this.mmuLastPage << 1);
|
||||
}
|
||||
this.trap(PDP11.TRAP.MMU, PDP11.REASON.MAPERROR);
|
||||
fTrap = true;
|
||||
}
|
||||
if (!(this.regMMR0 & 0xf000)) {
|
||||
//if (physicalAddress < 017772200 || physicalAddress > 017777677) {
|
||||
|
|
@ -1401,6 +1395,9 @@ CPUStatePDP11.prototype.mapVirtualToPhysical = function(virtualAddress, accessFl
|
|||
}
|
||||
}
|
||||
}
|
||||
if (fTrap) { // don't trap until the end, because it throws an exception
|
||||
this.trap(PDP11.TRAP.MMU, PDP11.REASON.MAPERROR);
|
||||
}
|
||||
}
|
||||
return physicalAddress;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -364,6 +364,7 @@ var PDP11 = {
|
|||
* For more details: https://github.com/google/closure-compiler/wiki/ECMAScript6
|
||||
*/
|
||||
UNIBUS: { //16-bit 18-bit 22-bit Hex Description
|
||||
UNIMAP: 0o170200, // UNIBUS Mapping Registers (0-31) 64 words (ends at 0o170372)
|
||||
SISDR0: 0o172200, // Supervisor I Space Descriptor Register 0
|
||||
SISDR1: 0o172202, // Supervisor I Space Descriptor Register 1
|
||||
SISDR2: 0o172204, // Supervisor I Space Descriptor Register 2
|
||||
|
|
|
|||
|
|
@ -321,6 +321,41 @@ DevicePDP11.prototype.updateConsoleMode = function()
|
|||
this.console.misc = (this.console.misc & ~7) | bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* readUNIMAP(addr)
|
||||
*
|
||||
* NOTE: The UNIBUS map is 32 registers spread across 64 words, so we first calculate the word index.
|
||||
*
|
||||
* @this {DevicePDP11}
|
||||
* @param {number} addr (eg, PDP11.UNIBUS.UNIMAP)
|
||||
* @return {number}
|
||||
*/
|
||||
DevicePDP11.prototype.readUNIMAP = function(addr)
|
||||
{
|
||||
var word = (addr >> 1) & 0x3f, reg = word >> 1;
|
||||
var data = this.cpu.unibusMap[reg];
|
||||
return (word & 1)? (data >> 16) : (data & 0xffff);
|
||||
};
|
||||
|
||||
/**
|
||||
* writeUNIMAP(data, addr)
|
||||
*
|
||||
* NOTE: The UNIBUS map is 32 registers spread across 64 words, so we first calculate the word index.
|
||||
*
|
||||
* @this {DevicePDP11}
|
||||
* @param {number} data
|
||||
* @param {number} addr (eg, PDP11.UNIBUS.UNIMAP)
|
||||
*/
|
||||
DevicePDP11.prototype.writeUNIMAP = function(data, addr)
|
||||
{
|
||||
var word = (addr >> 1) & 0x3f, reg = word >> 1;
|
||||
if (word & 1) {
|
||||
this.cpu.unibusMap[reg] = (this.cpu.unibusMap[reg] & 0xffff) | ((data & 0x003f) << 16);
|
||||
} else {
|
||||
this.cpu.unibusMap[reg] = (this.cpu.unibusMap[reg] & ~0xffff) | (data & 0xfffe);
|
||||
}
|
||||
};
|
||||
|
||||
/**
|
||||
* readSISDR(addr)
|
||||
*
|
||||
|
|
@ -1059,24 +1094,25 @@ DevicePDP11.prototype.writeIgnored = function(data, addr)
|
|||
* ES6 ALERT: As you can see below, I've finally started using computed property names.
|
||||
*/
|
||||
DevicePDP11.UNIBUS_IOTABLE = {
|
||||
[PDP11.UNIBUS.SISDR0]: /* 172200 */ [null, null, DevicePDP11.prototype.readSISDR, DevicePDP11.prototype.writeSISDR, "SISDR", PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.SDSDR0]: /* 172220 */ [null, null, DevicePDP11.prototype.readSDSDR, DevicePDP11.prototype.writeSDSDR, "SDSDR", PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.SISAR0]: /* 172240 */ [null, null, DevicePDP11.prototype.readSISAR, DevicePDP11.prototype.writeSISAR, "SISAR", PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.SDSAR0]: /* 172260 */ [null, null, DevicePDP11.prototype.readSDSAR, DevicePDP11.prototype.writeSDSAR, "SDSAR", PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.KISDR0]: /* 172300 */ [null, null, DevicePDP11.prototype.readKISDR, DevicePDP11.prototype.writeKISDR, "KISDR", PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.KDSDR0]: /* 172320 */ [null, null, DevicePDP11.prototype.readKDSDR, DevicePDP11.prototype.writeKDSDR, "KDSDR", PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.KISAR0]: /* 172340 */ [null, null, DevicePDP11.prototype.readKISAR, DevicePDP11.prototype.writeKISAR, "KISAR", PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.KDSAR0]: /* 172360 */ [null, null, DevicePDP11.prototype.readKDSAR, DevicePDP11.prototype.writeKDSAR, "KDSAR", PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.MMR3]: /* 172516 */ [null, null, DevicePDP11.prototype.readMMR3, DevicePDP11.prototype.writeMMR3, "MMR3", PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.UNIMAP]: /* 170200 */ [null, null, DevicePDP11.prototype.readUNIMAP, DevicePDP11.prototype.writeUNIMAP, "UNIMAP", 64, PDP11.MODEL_1170],
|
||||
[PDP11.UNIBUS.SISDR0]: /* 172200 */ [null, null, DevicePDP11.prototype.readSISDR, DevicePDP11.prototype.writeSISDR, "SISDR", 8, PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.SDSDR0]: /* 172220 */ [null, null, DevicePDP11.prototype.readSDSDR, DevicePDP11.prototype.writeSDSDR, "SDSDR", 8, PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.SISAR0]: /* 172240 */ [null, null, DevicePDP11.prototype.readSISAR, DevicePDP11.prototype.writeSISAR, "SISAR", 8, PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.SDSAR0]: /* 172260 */ [null, null, DevicePDP11.prototype.readSDSAR, DevicePDP11.prototype.writeSDSAR, "SDSAR", 8, PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.KISDR0]: /* 172300 */ [null, null, DevicePDP11.prototype.readKISDR, DevicePDP11.prototype.writeKISDR, "KISDR", 8, PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.KDSDR0]: /* 172320 */ [null, null, DevicePDP11.prototype.readKDSDR, DevicePDP11.prototype.writeKDSDR, "KDSDR", 8, PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.KISAR0]: /* 172340 */ [null, null, DevicePDP11.prototype.readKISAR, DevicePDP11.prototype.writeKISAR, "KISAR", 8, PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.KDSAR0]: /* 172360 */ [null, null, DevicePDP11.prototype.readKDSAR, DevicePDP11.prototype.writeKDSAR, "KDSAR", 8, PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.MMR3]: /* 172516 */ [null, null, DevicePDP11.prototype.readMMR3, DevicePDP11.prototype.writeMMR3, "MMR3", 1, PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.LKS]: /* 177546 */ [null, null, DevicePDP11.prototype.readLKS, DevicePDP11.prototype.writeLKS, "LKS"],
|
||||
[PDP11.UNIBUS.CNSL]: /* 177570 */ [null, null, DevicePDP11.prototype.readCNSL, DevicePDP11.prototype.writeCNSL, "CNSL"],
|
||||
[PDP11.UNIBUS.MMR0]: /* 177572 */ [null, null, DevicePDP11.prototype.readMMR0, DevicePDP11.prototype.writeMMR0, "MMR0", PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.MMR1]: /* 177574 */ [null, null, DevicePDP11.prototype.readMMR1, DevicePDP11.prototype.writeIgnored, "MMR1", PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.MMR2]: /* 177576 */ [null, null, DevicePDP11.prototype.readMMR2, DevicePDP11.prototype.writeIgnored, "MMR2", PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.UISDR0]: /* 177600 */ [null, null, DevicePDP11.prototype.readUISDR, DevicePDP11.prototype.writeUISDR, "UISDR", PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.UDSDR0]: /* 177620 */ [null, null, DevicePDP11.prototype.readUDSDR, DevicePDP11.prototype.writeUDSDR, "UDSDR", PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.UISAR0]: /* 177640 */ [null, null, DevicePDP11.prototype.readUISAR, DevicePDP11.prototype.writeUISAR, "UISAR", PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.UDSAR0]: /* 177660 */ [null, null, DevicePDP11.prototype.readUDSAR, DevicePDP11.prototype.writeUDSAR, "UDSAR", PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.MMR0]: /* 177572 */ [null, null, DevicePDP11.prototype.readMMR0, DevicePDP11.prototype.writeMMR0, "MMR0", 1, PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.MMR1]: /* 177574 */ [null, null, DevicePDP11.prototype.readMMR1, DevicePDP11.prototype.writeIgnored, "MMR1", 1, PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.MMR2]: /* 177576 */ [null, null, DevicePDP11.prototype.readMMR2, DevicePDP11.prototype.writeIgnored, "MMR2", 1, PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.UISDR0]: /* 177600 */ [null, null, DevicePDP11.prototype.readUISDR, DevicePDP11.prototype.writeUISDR, "UISDR", 8, PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.UDSDR0]: /* 177620 */ [null, null, DevicePDP11.prototype.readUDSDR, DevicePDP11.prototype.writeUDSDR, "UDSDR", 8, PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.UISAR0]: /* 177640 */ [null, null, DevicePDP11.prototype.readUISAR, DevicePDP11.prototype.writeUISAR, "UISAR", 8, PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.UDSAR0]: /* 177660 */ [null, null, DevicePDP11.prototype.readUDSAR, DevicePDP11.prototype.writeUDSAR, "UDSAR", 8, PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.R0SET0]: /* 177700 */ [null, null, DevicePDP11.prototype.readRSET0, DevicePDP11.prototype.writeRSET0, "R0SET0"],
|
||||
[PDP11.UNIBUS.R1SET0]: /* 177701 */ [null, null, DevicePDP11.prototype.readRSET0, DevicePDP11.prototype.writeRSET0, "R1SET0"],
|
||||
[PDP11.UNIBUS.R2SET0]: /* 177702 */ [null, null, DevicePDP11.prototype.readRSET0, DevicePDP11.prototype.writeRSET0, "R2SET0"],
|
||||
|
|
@ -1085,121 +1121,25 @@ DevicePDP11.UNIBUS_IOTABLE = {
|
|||
[PDP11.UNIBUS.R5SET0]: /* 177705 */ [null, null, DevicePDP11.prototype.readRSET0, DevicePDP11.prototype.writeRSET0, "R5SET0"],
|
||||
[PDP11.UNIBUS.R6KERNEL]:/* 177706 */ [null, null, DevicePDP11.prototype.readR6KERNEL,DevicePDP11.prototype.writeR6KERNEL,"R6KERNEL"],
|
||||
[PDP11.UNIBUS.R7KERNEL]:/* 177707 */ [null, null, DevicePDP11.prototype.readR7KERNEL,DevicePDP11.prototype.writeR7KERNEL,"R7KERNEL"],
|
||||
[PDP11.UNIBUS.R0SET1]: /* 177710 */ [null, null, DevicePDP11.prototype.readRSET1, DevicePDP11.prototype.writeRSET1, "R0SET1", PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.R1SET1]: /* 177711 */ [null, null, DevicePDP11.prototype.readRSET1, DevicePDP11.prototype.writeRSET1, "R1SET1", PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.R2SET1]: /* 177712 */ [null, null, DevicePDP11.prototype.readRSET1, DevicePDP11.prototype.writeRSET1, "R2SET1", PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.R3SET1]: /* 177713 */ [null, null, DevicePDP11.prototype.readRSET1, DevicePDP11.prototype.writeRSET1, "R3SET1", PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.R4SET1]: /* 177714 */ [null, null, DevicePDP11.prototype.readRSET1, DevicePDP11.prototype.writeRSET1, "R4SET1", PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.R5SET1]: /* 177715 */ [null, null, DevicePDP11.prototype.readRSET1, DevicePDP11.prototype.writeRSET1, "R5SET1", PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.R6SUPER]: /* 177716 */ [null, null, DevicePDP11.prototype.readR6SUPER, DevicePDP11.prototype.writeR6SUPER, "R6SUPER", PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.R6USER]: /* 177717 */ [null, null, DevicePDP11.prototype.readR6USER, DevicePDP11.prototype.writeR6USER, "R6USER", PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.LAERR]: /* 177740 */ [null, null, DevicePDP11.prototype.readCTRL, DevicePDP11.prototype.writeCTRL, "CTRL", PDP11.MODEL_1170],
|
||||
[PDP11.UNIBUS.LSIZE]: /* 177760 */ [null, null, DevicePDP11.prototype.readSIZE, DevicePDP11.prototype.writeSIZE, "LSIZE", PDP11.MODEL_1170],
|
||||
[PDP11.UNIBUS.HSIZE]: /* 177762 */ [null, null, DevicePDP11.prototype.readSIZE, DevicePDP11.prototype.writeSIZE, "HSIZE", PDP11.MODEL_1170],
|
||||
[PDP11.UNIBUS.SYSID]: /* 177764 */ [null, null, DevicePDP11.prototype.readSYSID, DevicePDP11.prototype.writeSYSID, "SYSID", PDP11.MODEL_1170],
|
||||
[PDP11.UNIBUS.CPUERR]: /* 177766 */ [null, null, DevicePDP11.prototype.readCPUERR, DevicePDP11.prototype.writeCPUERR, "CPUERR", PDP11.MODEL_1170],
|
||||
[PDP11.UNIBUS.MB]: /* 177770 */ [null, null, DevicePDP11.prototype.readMB, DevicePDP11.prototype.writeMB, "MB", PDP11.MODEL_1170],
|
||||
[PDP11.UNIBUS.R0SET1]: /* 177710 */ [null, null, DevicePDP11.prototype.readRSET1, DevicePDP11.prototype.writeRSET1, "R0SET1", 1, PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.R1SET1]: /* 177711 */ [null, null, DevicePDP11.prototype.readRSET1, DevicePDP11.prototype.writeRSET1, "R1SET1", 1, PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.R2SET1]: /* 177712 */ [null, null, DevicePDP11.prototype.readRSET1, DevicePDP11.prototype.writeRSET1, "R2SET1", 1, PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.R3SET1]: /* 177713 */ [null, null, DevicePDP11.prototype.readRSET1, DevicePDP11.prototype.writeRSET1, "R3SET1", 1, PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.R4SET1]: /* 177714 */ [null, null, DevicePDP11.prototype.readRSET1, DevicePDP11.prototype.writeRSET1, "R4SET1", 1, PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.R5SET1]: /* 177715 */ [null, null, DevicePDP11.prototype.readRSET1, DevicePDP11.prototype.writeRSET1, "R5SET1", 1, PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.R6SUPER]: /* 177716 */ [null, null, DevicePDP11.prototype.readR6SUPER, DevicePDP11.prototype.writeR6SUPER, "R6SUPER", 1, PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.R6USER]: /* 177717 */ [null, null, DevicePDP11.prototype.readR6USER, DevicePDP11.prototype.writeR6USER, "R6USER", 1, PDP11.MODEL_1145],
|
||||
[PDP11.UNIBUS.LAERR]: /* 177740 */ [null, null, DevicePDP11.prototype.readCTRL, DevicePDP11.prototype.writeCTRL, "CTRL", 1, PDP11.MODEL_1170],
|
||||
[PDP11.UNIBUS.LSIZE]: /* 177760 */ [null, null, DevicePDP11.prototype.readSIZE, DevicePDP11.prototype.writeSIZE, "LSIZE", 1, PDP11.MODEL_1170],
|
||||
[PDP11.UNIBUS.HSIZE]: /* 177762 */ [null, null, DevicePDP11.prototype.readSIZE, DevicePDP11.prototype.writeSIZE, "HSIZE", 1, PDP11.MODEL_1170],
|
||||
[PDP11.UNIBUS.SYSID]: /* 177764 */ [null, null, DevicePDP11.prototype.readSYSID, DevicePDP11.prototype.writeSYSID, "SYSID", 1, PDP11.MODEL_1170],
|
||||
[PDP11.UNIBUS.CPUERR]: /* 177766 */ [null, null, DevicePDP11.prototype.readCPUERR, DevicePDP11.prototype.writeCPUERR, "CPUERR", 1, PDP11.MODEL_1170],
|
||||
[PDP11.UNIBUS.MB]: /* 177770 */ [null, null, DevicePDP11.prototype.readMB, DevicePDP11.prototype.writeMB, "MB", 1, PDP11.MODEL_1170],
|
||||
[PDP11.UNIBUS.PIR]: /* 177772 */ [null, null, DevicePDP11.prototype.readPIR, DevicePDP11.prototype.writePIR, "PIR"],
|
||||
[PDP11.UNIBUS.SL]: /* 177774 */ [null, null, DevicePDP11.prototype.readSL, DevicePDP11.prototype.writeSL, "SL"],
|
||||
[PDP11.UNIBUS.PSW]: /* 177776 */ [null, null, DevicePDP11.prototype.readPSW, DevicePDP11.prototype.writePSW, "PSW"]
|
||||
};
|
||||
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISDR1] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISDR2] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISDR3] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISDR4] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISDR5] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISDR6] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISDR7] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISDR0];
|
||||
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSDR1] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSDR2] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSDR3] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSDR4] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSDR5] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSDR6] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSDR7] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSDR0];
|
||||
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISAR1] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISAR2] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISAR3] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISAR4] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISAR5] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISAR6] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISAR7] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SISAR0];
|
||||
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSAR1] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSAR2] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSAR3] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSAR4] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSAR5] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSAR6] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSAR7] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.SDSAR0];
|
||||
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISDR1] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISDR2] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISDR3] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISDR4] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISDR5] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISDR6] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISDR7] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISDR0];
|
||||
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSDR1] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSDR2] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSDR3] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSDR4] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSDR5] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSDR6] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSDR7] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSDR0];
|
||||
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISAR1] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISAR2] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISAR3] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISAR4] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISAR5] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISAR6] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISAR7] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KISAR0];
|
||||
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSAR1] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSAR2] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSAR3] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSAR4] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSAR5] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSAR6] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSAR7] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.KDSAR0];
|
||||
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISDR1] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISDR2] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISDR3] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISDR4] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISDR5] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISDR6] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISDR7] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISDR0];
|
||||
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSDR1] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSDR2] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSDR3] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSDR4] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSDR5] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSDR6] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSDR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSDR7] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSDR0];
|
||||
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISAR1] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISAR2] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISAR3] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISAR4] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISAR5] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISAR6] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISAR7] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UISAR0];
|
||||
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSAR1] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSAR2] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSAR3] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSAR4] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSAR5] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSAR6] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSAR0];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSAR7] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.UDSAR0];
|
||||
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.HAERR] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.LAERR];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.MEMERR] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.LAERR];
|
||||
DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.CACHEC] = DevicePDP11.UNIBUS_IOTABLE[PDP11.UNIBUS.LAERR];
|
||||
|
|
|
|||
|
|
@ -575,7 +575,9 @@ MemoryPDP11.prototype = {
|
|||
*
|
||||
* TODO: Determine if we should have separate readByteNone(), readWordNone() and readLongNone() functions
|
||||
* to return 0xff, 0xffff and 0xffffffff|0, respectively. This seems sufficient for now, as it seems unlikely
|
||||
* that a system would require nonexistent memory locations to return ALL bits set.
|
||||
* that a system would require nonexistent memory locations to return ALL bits set. However, another factor
|
||||
* is whether or not ODDADDR faults take precedence over NOMEMORY faults; if they do, then we need separate
|
||||
* interfaces.
|
||||
*
|
||||
* Also, I'm reluctant to address that potential issue by simply returning -1, because to date, the above
|
||||
* Memory interfaces have always returned values that are properly masked to 8, 16 or 32 bits, respectively.
|
||||
|
|
@ -590,7 +592,7 @@ MemoryPDP11.prototype = {
|
|||
this.dbg.printMessage("attempt to read invalid address " + this.dbg.toStrBase(addr), true);
|
||||
this.dbg.stopInstruction();
|
||||
}
|
||||
this.bus.fault(addr, PDP11.ACCESS.READ);
|
||||
this.bus.fault(addr, PDP11.CPUERR.NOMEMORY, PDP11.ACCESS.READ);
|
||||
return 0xff;
|
||||
},
|
||||
/**
|
||||
|
|
@ -606,7 +608,7 @@ MemoryPDP11.prototype = {
|
|||
this.dbg.printMessage("attempt to write " + this.dbg.toStrBase(v) + " to invalid addresses " + this.dbg.toStrBase(addr), true);
|
||||
this.dbg.stopInstruction();
|
||||
}
|
||||
this.bus.fault(addr, PDP11.ACCESS.WRITE);
|
||||
this.bus.fault(addr, PDP11.CPUERR.NOMEMORY, PDP11.ACCESS.WRITE);
|
||||
},
|
||||
/**
|
||||
* readWordDefault(off, addr)
|
||||
|
|
@ -655,7 +657,7 @@ MemoryPDP11.prototype = {
|
|||
*/
|
||||
readWordMemory: function readWordMemory(off, addr) {
|
||||
if (PDP11.MEMFAULT && (off & 0x1)) {
|
||||
this.bus.fault(addr, PDP11.ACCESS.READ_WORD);
|
||||
this.bus.fault(addr, PDP11.CPUERR.ODDADDR, PDP11.ACCESS.READ_WORD);
|
||||
}
|
||||
if (BYTEARRAYS) {
|
||||
return this.ab[off] | (this.ab[off + 1] << 8);
|
||||
|
|
@ -699,7 +701,7 @@ MemoryPDP11.prototype = {
|
|||
*/
|
||||
writeWordMemory: function writeWordMemory(off, w, addr) {
|
||||
if (PDP11.MEMFAULT && (off & 0x1)) {
|
||||
this.bus.fault(addr, PDP11.ACCESS.WRITE_WORD);
|
||||
this.bus.fault(addr, PDP11.CPUERR.ODDADDR, PDP11.ACCESS.WRITE_WORD);
|
||||
}
|
||||
if (BYTEARRAYS) {
|
||||
this.ab[off] = (w & 0xff);
|
||||
|
|
@ -809,7 +811,7 @@ MemoryPDP11.prototype = {
|
|||
*/
|
||||
readWordBE: function readWordBE(off, addr) {
|
||||
if (PDP11.MEMFAULT && (off & 0x1)) {
|
||||
this.bus.fault(addr, PDP11.ACCESS.READ_WORD);
|
||||
this.bus.fault(addr, PDP11.CPUERR.ODDADDR, PDP11.ACCESS.READ_WORD);
|
||||
}
|
||||
return this.dv.getUint16(off, true);
|
||||
},
|
||||
|
|
@ -824,7 +826,7 @@ MemoryPDP11.prototype = {
|
|||
readWordLE: function readWordLE(off, addr) {
|
||||
var w;
|
||||
if (PDP11.MEMFAULT && (off & 0x1)) {
|
||||
this.bus.fault(addr, PDP11.ACCESS.READ_WORD);
|
||||
this.bus.fault(addr, PDP11.CPUERR.ODDADDR, PDP11.ACCESS.READ_WORD);
|
||||
}
|
||||
/*
|
||||
* TODO: For non-WORDBUS machines, it remains to be seen if there's any advantage to checking the offset
|
||||
|
|
@ -877,7 +879,7 @@ MemoryPDP11.prototype = {
|
|||
*/
|
||||
writeWordBE: function writeWordBE(off, w, addr) {
|
||||
if (PDP11.MEMFAULT && (off & 0x1)) {
|
||||
this.bus.fault(addr, PDP11.ACCESS.WRITE_WORD);
|
||||
this.bus.fault(addr, PDP11.CPUERR.ODDADDR, PDP11.ACCESS.WRITE_WORD);
|
||||
}
|
||||
this.dv.setUint16(off, w, true);
|
||||
this.fDirty = true;
|
||||
|
|
@ -892,7 +894,7 @@ MemoryPDP11.prototype = {
|
|||
*/
|
||||
writeWordLE: function writeWordLE(off, w, addr) {
|
||||
if (PDP11.MEMFAULT && (off & 0x1)) {
|
||||
this.bus.fault(addr, PDP11.ACCESS.WRITE_WORD);
|
||||
this.bus.fault(addr, PDP11.CPUERR.ODDADDR, PDP11.ACCESS.WRITE_WORD);
|
||||
}
|
||||
/*
|
||||
* TODO: For non-WORDBUS machines, it remains to be seen if there's any advantage to checking the offset
|
||||
|
|
|
|||
|
|
@ -176,20 +176,20 @@ RAMPDP11.prototype.doneLoad = function(sURL, sData, nErrorCode)
|
|||
{
|
||||
if (nErrorCode) {
|
||||
this.notice("Unable to load RAM resource (error " + nErrorCode + ": " + sURL + ")");
|
||||
return;
|
||||
}
|
||||
|
||||
Component.addMachineResource(this.idMachine, sURL, sData);
|
||||
|
||||
var resource = web.parseMemoryResource(sURL, sData);
|
||||
if (resource) {
|
||||
this.abInit = resource.aBytes;
|
||||
this.aSymbols = resource.aSymbols;
|
||||
if (this.addrLoad == null) this.addrLoad = resource.addrLoad;
|
||||
if (this.addrExec == null) this.addrExec = resource.addrExec;
|
||||
} else {
|
||||
this.sFilePath = null;
|
||||
}
|
||||
else {
|
||||
Component.addMachineResource(this.idMachine, sURL, sData);
|
||||
var resource = web.parseMemoryResource(sURL, sData);
|
||||
if (resource) {
|
||||
this.abInit = resource.aBytes;
|
||||
this.aSymbols = resource.aSymbols;
|
||||
if (this.addrLoad == null) this.addrLoad = resource.addrLoad;
|
||||
if (this.addrExec == null) this.addrExec = resource.addrExec;
|
||||
} else {
|
||||
this.sFilePath = null;
|
||||
}
|
||||
}
|
||||
this.initRAM();
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -856,7 +856,6 @@ RL11.prototype.initDrive = function(drive, iDrive, data)
|
|||
* The next group of properties are set by various controller command sequences.
|
||||
*/
|
||||
drive.bHead = 0;
|
||||
drive.bCylinderSeek = 0;
|
||||
drive.bCylinder = 0;
|
||||
drive.bSector = 1;
|
||||
drive.bSectorEnd = drive.nSectors; // aka EOT
|
||||
|
|
@ -1010,7 +1009,7 @@ RL11.prototype.readData = function(drive, iCylinder, iHead, iSector, nWords, add
|
|||
|
||||
while (nWords--) {
|
||||
if (!sector) {
|
||||
sector = drive.disk.seek(iCylinder, iHead, iSector, true);
|
||||
sector = drive.disk.seek(iCylinder, iHead, iSector + 1);
|
||||
if (!sector) {
|
||||
err = PDP11.RL11.ERRC.HNF;
|
||||
break;
|
||||
|
|
@ -1022,7 +1021,7 @@ RL11.prototype.readData = function(drive, iCylinder, iHead, iSector, nWords, add
|
|||
err = PDP11.RL11.ERRC.HNF;
|
||||
break;
|
||||
}
|
||||
var data = this.bus.setWordDirect(this.cpu.mapUnibus(addr), b0 | (b1 << 8));
|
||||
var data = this.bus.setWord(addr, b0 | (b1 << 8));
|
||||
if (this.bus.checkFault()) {
|
||||
err = PDP11.RL11.ERRC.NXM;
|
||||
break;
|
||||
|
|
@ -1065,14 +1064,14 @@ RL11.prototype.writeData = function(drive, iCylinder, iHead, iSector, nWords, ad
|
|||
var sector = null, ibSector;
|
||||
|
||||
while (nWords--) {
|
||||
var data = this.bus.getWordDirect(this.cpu.mapUnibus(addr));
|
||||
var data = this.bus.getWord(addr);
|
||||
if (this.bus.checkFault()) {
|
||||
err = PDP11.RL11.ERRC.NXM;
|
||||
break;
|
||||
}
|
||||
addr += 2;
|
||||
if (!sector) {
|
||||
sector = drive.disk.seek(iCylinder, iHead, iSector, true);
|
||||
sector = drive.disk.seek(iCylinder, iHead, iSector + 1, true);
|
||||
if (!sector) {
|
||||
err = PDP11.RL11.ERRC.HNF;
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -191,18 +191,18 @@ ROMPDP11.prototype.doneLoad = function(sURL, sData, nErrorCode)
|
|||
{
|
||||
if (nErrorCode) {
|
||||
this.notice("Unable to load ROM resource (error " + nErrorCode + ": " + sURL + ")");
|
||||
return;
|
||||
}
|
||||
|
||||
Component.addMachineResource(this.idMachine, sURL, sData);
|
||||
|
||||
var resource = web.parseMemoryResource(sURL, sData);
|
||||
if (resource) {
|
||||
this.abInit = resource.aBytes;
|
||||
this.aSymbols = resource.aSymbols;
|
||||
} else {
|
||||
this.sFilePath = null;
|
||||
}
|
||||
else {
|
||||
Component.addMachineResource(this.idMachine, sURL, sData);
|
||||
var resource = web.parseMemoryResource(sURL, sData);
|
||||
if (resource) {
|
||||
this.abInit = resource.aBytes;
|
||||
this.aSymbols = resource.aSymbols;
|
||||
} else {
|
||||
this.sFilePath = null;
|
||||
}
|
||||
}
|
||||
this.initROM();
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue