Added scaffolding for PC8080 SerialPort
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11 changed files with 1075 additions and 445 deletions
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@ -6,7 +6,7 @@
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<cpu id="cpu8080" model="8080" cycles="2764800"/>
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<rom id="rom" addr="0x0000" size="0x2000" file="/devices/pc8080/rom/vt100/VT100.json"/>
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<ram id="ram" addr="0x2000" size="0x0C00"/>
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<video id="video" screenWidth="1600" screenHeight="960" smoothing="false"
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<video id="video" screenWidth="1600" screenHeight="960" smoothing="false" interruptRate="60"
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fontROM="/devices/pc8080/rom/vt100/23-018E2.json" fontColor="white" cellWidth="10" cellHeight="10"
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bufferAddr="0x2000" bufferRAM="true" bufferFormat="vt100" bufferCols="80" bufferRows="24" pos="left" padding="8px">
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<menu>
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@ -25,6 +25,7 @@
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</video>
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<chipset id="chipset" model="VT100"/>
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<keyboard id="keyboard" model="VT100"/>
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<serial id="serial0" adapter="0"/>
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<panel ref="/devices/pc8080/panel/wide.xml"/>
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<debugger id="debugger" messages="mem" commands="s 8086"/>
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<debugger id="debugger" messages="mem|port|keyboard" commands="s 8086"/>
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</machine>
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@ -6,7 +6,7 @@
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<cpu id="cpu8080" model="8080" cycles="2764800"/>
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<rom id="rom" addr="0x0000" size="0x2000" file="/devices/pc8080/rom/vt100/VT100.json"/>
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<ram id="ram" addr="0x2000" size="0x0C00"/>
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<video id="video" screenWidth="1600" screenHeight="960" smoothing="false"
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<video id="video" screenWidth="1600" screenHeight="960" smoothing="false" interruptRate="60"
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fontROM="/devices/pc8080/rom/vt100/23-018E2.json" fontColor="white" cellWidth="10" cellHeight="10"
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bufferAddr="0x2000" bufferRAM="true" bufferFormat="vt100" bufferCols="80" bufferRows="24" padding="8px">
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<menu>
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@ -15,8 +15,9 @@ The combined contents of those ROMs have been stored as an 8Kb JSON image in [VT
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As Trammell Hudson's [VT100 Page](https://trmm.net/VT100) explains:
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There are four 8316E ROM chips for the 8080 CPU on the logic board. Since they are custom mask ROMs,
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Digital was able to have a different chip-select bit pattern and avoided having separate NOT gates on the inputs.
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Note that the schematic appears to be incorrect -- E56 is the low order, and E40 is the high order address bits.
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Digital was able to have a different chip-select bit pattern and avoided having separate NOT gates on
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the inputs. Note that the schematic appears to be incorrect -- E56 is the low order, and E40 is the
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high order address bits.
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He then describes the memory map as follows:
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@ -67,8 +68,8 @@ and passed on to the PC8080 Debugger. Here are the rebuild steps:
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grep -E "[0-9]+ [0-9A-D]+.*;;" VT100.lst | sed -E "s/ *[0-9]+ ([0-9A-F]+).*;(;.*)/ \1 . \2/" > VT100.map
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filedump --file=VT100.bin --format=bytes --output=VT100.json --comments --overwrite
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You can omit `--comments` to reduce the size of the [VT100.json](VT100.json) file.
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You can omit `--comments` from the filedump command to reduce the size of the [VT100.json](VT100.json) file.
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Some [VT100.asm](VT100.asm) clean-up remains, because there are still chunks of data that were incorrectly disassembled as code.
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From a reassembly standpoint, it doesn't matter too much, because such instructions get reassembled into the same original binary
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patterns, but from a readability standpoint, it's a nuisance.
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From a reassembly standpoint, it doesn't matter too much, because all the 8080 instructions unambiguously reassemble into their
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original binary patterns, but from a readability standpoint, it's a nuisance.
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@ -212,9 +212,19 @@ X00f5: push d
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pop d
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jmp X0875
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;;
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;; Keyboard interrupt handler
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;;
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;
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; Keyboard interrupt handler
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;
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; The "Keys Flag Byte/Buffer" at 0x2068 contains the following bits:
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;
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; 0-1 Key counter
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; 2 Key counter overflow bit
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; 3 Setup
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; 4 Control
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; 5 Shift
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; 6 Caps Lock
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; 7 Last Key
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;
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X00fd: push psw
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in 82h ;; Read from keyboard port
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push h
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