Added scaffolding for PC8080 SerialPort

This commit is contained in:
Jeff Parsons 2016-08-08 15:25:57 -07:00
commit d31bfb0e6e
11 changed files with 1075 additions and 445 deletions

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@ -6,7 +6,7 @@
<cpu id="cpu8080" model="8080" cycles="2764800"/>
<rom id="rom" addr="0x0000" size="0x2000" file="/devices/pc8080/rom/vt100/VT100.json"/>
<ram id="ram" addr="0x2000" size="0x0C00"/>
<video id="video" screenWidth="1600" screenHeight="960" smoothing="false"
<video id="video" screenWidth="1600" screenHeight="960" smoothing="false" interruptRate="60"
fontROM="/devices/pc8080/rom/vt100/23-018E2.json" fontColor="white" cellWidth="10" cellHeight="10"
bufferAddr="0x2000" bufferRAM="true" bufferFormat="vt100" bufferCols="80" bufferRows="24" pos="left" padding="8px">
<menu>
@ -25,6 +25,7 @@
</video>
<chipset id="chipset" model="VT100"/>
<keyboard id="keyboard" model="VT100"/>
<serial id="serial0" adapter="0"/>
<panel ref="/devices/pc8080/panel/wide.xml"/>
<debugger id="debugger" messages="mem" commands="s 8086"/>
<debugger id="debugger" messages="mem|port|keyboard" commands="s 8086"/>
</machine>

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@ -6,7 +6,7 @@
<cpu id="cpu8080" model="8080" cycles="2764800"/>
<rom id="rom" addr="0x0000" size="0x2000" file="/devices/pc8080/rom/vt100/VT100.json"/>
<ram id="ram" addr="0x2000" size="0x0C00"/>
<video id="video" screenWidth="1600" screenHeight="960" smoothing="false"
<video id="video" screenWidth="1600" screenHeight="960" smoothing="false" interruptRate="60"
fontROM="/devices/pc8080/rom/vt100/23-018E2.json" fontColor="white" cellWidth="10" cellHeight="10"
bufferAddr="0x2000" bufferRAM="true" bufferFormat="vt100" bufferCols="80" bufferRows="24" padding="8px">
<menu>

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@ -15,8 +15,9 @@ The combined contents of those ROMs have been stored as an 8Kb JSON image in [VT
As Trammell Hudson's [VT100 Page](https://trmm.net/VT100) explains:
There are four 8316E ROM chips for the 8080 CPU on the logic board. Since they are custom mask ROMs,
Digital was able to have a different chip-select bit pattern and avoided having separate NOT gates on the inputs.
Note that the schematic appears to be incorrect -- E56 is the low order, and E40 is the high order address bits.
Digital was able to have a different chip-select bit pattern and avoided having separate NOT gates on
the inputs. Note that the schematic appears to be incorrect -- E56 is the low order, and E40 is the
high order address bits.
He then describes the memory map as follows:
@ -67,8 +68,8 @@ and passed on to the PC8080 Debugger. Here are the rebuild steps:
grep -E "[0-9]+ [0-9A-D]+.*;;" VT100.lst | sed -E "s/ *[0-9]+ ([0-9A-F]+).*;(;.*)/ \1 . \2/" > VT100.map
filedump --file=VT100.bin --format=bytes --output=VT100.json --comments --overwrite
You can omit `--comments` to reduce the size of the [VT100.json](VT100.json) file.
You can omit `--comments` from the filedump command to reduce the size of the [VT100.json](VT100.json) file.
Some [VT100.asm](VT100.asm) clean-up remains, because there are still chunks of data that were incorrectly disassembled as code.
From a reassembly standpoint, it doesn't matter too much, because such instructions get reassembled into the same original binary
patterns, but from a readability standpoint, it's a nuisance.
From a reassembly standpoint, it doesn't matter too much, because all the 8080 instructions unambiguously reassemble into their
original binary patterns, but from a readability standpoint, it's a nuisance.

View file

@ -212,9 +212,19 @@ X00f5: push d
pop d
jmp X0875
;;
;; Keyboard interrupt handler
;;
;
; Keyboard interrupt handler
;
; The "Keys Flag Byte/Buffer" at 0x2068 contains the following bits:
;
; 0-1 Key counter
; 2 Key counter overflow bit
; 3 Setup
; 4 Control
; 5 Shift
; 6 Caps Lock
; 7 Last Key
;
X00fd: push psw
in 82h ;; Read from keyboard port
push h