diff --git a/devices/pc/bios/compaq/deskpro386/1988-01-28.nasm b/devices/pc/bios/compaq/deskpro386/1988-01-28.nasm
index 71141b695..d0fe10142 100644
--- a/devices/pc/bios/compaq/deskpro386/1988-01-28.nasm
+++ b/devices/pc/bios/compaq/deskpro386/1988-01-28.nasm
@@ -1,5 +1,7 @@
 	org	0x8000
 
+CMD8042_WRITE_OUTPORT	equ	0xD1
+
 	xchg	bh,bl			; 00008000  86FB  '..'
 	xor	bh,bh			; 00008002  32FF  '2.'
 	shl	bx,1			; 00008004  D1E3  '..'
@@ -808,6 +810,9 @@ x86db:	mov	word [0x50],0xffff	; 000086DB  C7065000FFFF  '..P...'
 	or	al,0x8			; 00008706  0C08  '..'
 	out	0x61,al			; 00008708  E661  '.a'
 	out	0x84,al			; 0000870A  E684  '..'
+	;
+	; Read the memory-mapped settings/diagnostic register at 0x80C00000 into BX
+	;
 	mov	bx,[0x0]		; 0000870C  8B1E0000  '....'
 	mov	byte [0x0],0xff		; 00008710  C6060000FF  '.....'
 	out	0x84,al			; 00008715  E684  '..'
@@ -3923,19 +3928,19 @@ xa3b6:	mov	al,0x80			; 0000A3B6  B080  '..'
 	jmp	short xa43c		; 0000A3DE  EB5C  '.\'
 
 xa3e0:	cli				; 0000A3E0  FA  '.'
-	call	xec2e			; 0000A3E1  E84A48  '.JH'
+	call	xec2e_wait_8042_ready	; 0000A3E1  E84A48  '.JH'
 	jnz	xa3ff			; 0000A3E4  7519  'u.'
 	mov	al,0xd1			; 0000A3E6  B0D1  '..'
 	out	0x64,al			; 0000A3E8  E664  '.d'
-	call	xec2e			; 0000A3EA  E84148  '.AH'
+	call	xec2e_wait_8042_ready	; 0000A3EA  E84148  '.AH'
 	jnz	xa3ff			; 0000A3ED  7510  'u.'
 	mov	al,0xdf			; 0000A3EF  B0DF  '..'
 	out	0x60,al			; 0000A3F1  E660  '.`'
-	call	xec2e			; 0000A3F3  E83848  '.8H'
+	call	xec2e_wait_8042_ready	; 0000A3F3  E83848  '.8H'
 	jnz	xa3ff			; 0000A3F6  7507  'u.'
 	mov	al,0xff			; 0000A3F8  B0FF  '..'
 	out	0x64,al			; 0000A3FA  E664  '.d'
-	call	xec2e			; 0000A3FC  E82F48  './H'
+	call	xec2e_wait_8042_ready	; 0000A3FC  E82F48  './H'
 xa3ff:	ret				; 0000A3FF  C3  '.'
 
 	mov	ah,0x2			; 0000A400  B402  '..'
@@ -3999,19 +4004,19 @@ xa46c:	and	word [bp+0x6],0xffbf	; 0000A46C  816606BFFF  '.f...'
 xa476:	pop	bp			; 0000A476  5D  ']'
 	iret				; 0000A477  CF  '.'
 
-xa478:	call	xec2e			; 0000A478  E8B347  '..G'
+xa478:	call	xec2e_wait_8042_ready	; 0000A478  E8B347  '..G'
 	jnz	xa498			; 0000A47B  751B  'u.'
-	mov	al,0xd1			; 0000A47D  B0D1  '..'
+	mov	al,CMD8042_WRITE_OUTPORT; 0000A47D  B0D1  '..'
 	out	0x64,al			; 0000A47F  E664  '.d'
-	call	xec2e			; 0000A481  E8AA47  '..G'
+	call	xec2e_wait_8042_ready	; 0000A481  E8AA47  '..G'
 	jnz	xa498			; 0000A484  7512  'u.'
 	mov	al,0xdd			; 0000A486  B0DD  '..'
 	out	0x60,al			; 0000A488  E660  '.`'
-	call	xec2e			; 0000A48A  E8A147  '..G'
+	call	xec2e_wait_8042_ready	; 0000A48A  E8A147  '..G'
 	jnz	xa498			; 0000A48D  7509  'u.'
 	mov	al,0xff			; 0000A48F  B0FF  '..'
 	out	0x64,al			; 0000A491  E664  '.d'
-	call	xec2e			; 0000A493  E89847  '..G'
+	call	xec2e_wait_8042_ready	; 0000A493  E89847  '..G'
 	jz	xa49c			; 0000A496  7404  't.'
 xa498:	mov	al,0x3			; 0000A498  B003  '..'
 	out	0x80,al			; 0000A49A  E680  '..'
@@ -6357,8 +6362,19 @@ xbc71:	call	xa3e0			; 0000BC71  E86CE7  '.l.'
 	mov	al,0x20			; 0000BCA8  B020  '. '
 	out	0x84,al			; 0000BCAA  E684  '..'
 	call	xd6dd			; 0000BCAC  E82E1A  '...'
+
+	;
+	; Enable copy of ROM in "shadow RAM"?
+	;
 	call	xc825			; 0000BCAF  E8730B  '.s.'
+
+	;
+	; This function loads the GDTR with [00FF0730,0047], but since the previous call
+	; turned A20 off, the first selector load crashes, because physical address %FF0730
+	; requires A20 on.
+	;
 	call	xf480			; 0000BCB2  E8CB37
+
 	call	xe7df			; 0000BCB5  E8272B  '.',0x27,'+'
 	sti				; 0000BCB8  FB  '.'
 	mov	al,0x21			; 0000BCB9  B021  '.!'
@@ -6457,7 +6473,7 @@ xbd6e:	in	al,0xa1			; 0000BD6E  E4A1  '..'
 	or	byte [0x96],0x80	; 0000BD84  800E960080  '.....'
 	or	byte [0x96],0x20	; 0000BD89  800E960020  '.... '
 	cli				; 0000BD8E  FA  '.'
-	call	xec2e			; 0000BD8F  E89C2E  '...'
+	call	xec2e_wait_8042_ready	; 0000BD8F  E89C2E  '...'
 	mov	al,0xf2			; 0000BD92  B0F2  '..'
 	out	0x60,al			; 0000BD94  E660  '.`'
 	sti				; 0000BD96  FB  '.'
@@ -7762,6 +7778,11 @@ xc817:	mov	al,[bx]			; 0000C817  8A07  '..'
 	pop	es			; 0000C823  07  '.'
 	ret				; 0000C824  C3  '.'
 
+	;
+	; Copy ROM into reserved extended RAM?
+	;
+	; This function ends by disabling A20 and zeroing all conventional memory.
+	;
 xc825:	pusha				; 0000C825  60  '`'
 	push	ds			; 0000C826  1E  '.'
 	push	es			; 0000C827  06  '.'
@@ -7809,16 +7830,23 @@ xc845:	mov	al,0xd2			; 0000C845  B0D2  '..'
 	mov	eax,cr0			; 0000C88C  0F2000
 	and	eax,0x7ffffffe		; 0000C88F  6625FEFFFF7F  'f%....'
 	mov	cr0,eax			; 0000C895  0F2200
-	jmp	0xf000:0xc89d		; 0000C898  EA9DC800F0  '.....'
+	jmp	0xf000:xc89d		; 0000C898  EA9DC800F0  '.....'
 
-	lidt	[cs:0xa151]		; 0000C89D  2E0F011E51A1  '....Q.'
+xc89d:	lidt	[cs:0xa151]		; 0000C89D  2E0F011E51A1  '....Q.'
 	mov	al,0xd4			; 0000C8A3  B0D4  '..'
 	out	0x84,al			; 0000C8A5  E684  '..'
 	mov	ax,0x40			; 0000C8A7  B84000  '.@.'
 	mov	ds,ax			; 0000C8AA  8ED8  '..'
 	mov	ss,[0x69]		; 0000C8AC  8E166900  '..i.'
 	mov	sp,[0x67]		; 0000C8B0  8B266700  '.&g.'
+	;
+	; Disable A20
+	;
 	call	xa478			; 0000C8B4  E8C1DB  '...'
+	;
+	; Get the (conventional) memory size in Kb from 0x40:0x0013, divide by 64 (0x40) to yield
+	; the number of 64Kb blocks of RAM below 1Mb, and then zero each 64Kb block with "rep stosd".
+	;
 	mov	ax,[0x13]		; 0000C8B7  A11300  '...'
 	xor	dx,dx			; 0000C8BA  33D2  '3.'
 	mov	bx,0x40			; 0000C8BC  BB4000  '.@.'
@@ -9845,7 +9873,7 @@ xd994:	mov	al,0x8f			; 0000D994  B08F  '..'
 	in	al,0x60			; 0000D99D  E460  '.`'
 	mov	al,0x20			; 0000D99F  B020  '. '
 	out	0x64,al			; 0000D9A1  E664  '.d'
-	call	xec2e			; 0000D9A3  E88812  '...'
+	call	xec2e_wait_8042_ready	; 0000D9A3  E88812  '...'
 xd9a6:	in	al,0x64			; 0000D9A6  E464  '.d'
 	test	al,0x1			; 0000D9A8  A801  '..'
 	jz	xd9a6			; 0000D9AA  74FA  't.'
@@ -9855,11 +9883,11 @@ xd9a6:	in	al,0x64			; 0000D9A6  E464  '.d'
 	mov	al,0x60			; 0000D9B3  B060  '.`'
 	out	0x64,al			; 0000D9B5  E664  '.d'
 	push	ax			; 0000D9B7  50  'P'
-	call	xec2e			; 0000D9B8  E87312  '.s.'
+	call	xec2e_wait_8042_ready	; 0000D9B8  E87312  '.s.'
 	pop	ax			; 0000D9BB  58  'X'
 	mov	al,ah			; 0000D9BC  8AC4  '..'
 	out	0x60,al			; 0000D9BE  E660  '.`'
-	call	xec2e			; 0000D9C0  E86B12  '.k.'
+	call	xec2e_wait_8042_ready	; 0000D9C0  E86B12  '.k.'
 	mov	al,0xfe			; 0000D9C3  B0FE  '..'
 	out	0x64,al			; 0000D9C5  E664  '.d'
 xd9c7:	hlt				; 0000D9C7  F4  '.'
@@ -10263,20 +10291,20 @@ xdd28:	cmp	al,0x5			; 0000DD28  3C05  '<.'
 xdd37:	call	xec1e			; 0000DD37  E8E40E  '...'
 	jnz	xdd37			; 0000DD3A  75FB  'u.'
 	and	byte [0x97],0xef	; 0000DD3C  80269700EF  '.&...'
-	call	xec2e			; 0000DD41  E8EA0E  '...'
+	call	xec2e_wait_8042_ready	; 0000DD41  E8EA0E  '...'
 	mov	al,0xf3			; 0000DD44  B0F3  '..'
 	out	0x60,al			; 0000DD46  E660  '.`'
 	mov	cx,0xffff		; 0000DD48  B9FFFF  '...'
 xdd4b:	test	byte [0x97],0x10	; 0000DD4B  F606970010  '.....'
 	jnz	xdd5d			; 0000DD50  750B  'u.'
 	loop	xdd4b			; 0000DD52  E2F7  '..'
-	call	xec2e			; 0000DD54  E8D70E  '...'
+	call	xec2e_wait_8042_ready	; 0000DD54  E8D70E  '...'
 	mov	al,0xf4			; 0000DD57  B0F4  '..'
 	out	0x60,al			; 0000DD59  E660  '.`'
 	jmp	short xdd81		; 0000DD5B  EB24  '.$'
 
 xdd5d:	and	byte [0x97],0xef	; 0000DD5D  80269700EF  '.&...'
-	call	xec2e			; 0000DD62  E8C90E  '...'
+	call	xec2e_wait_8042_ready	; 0000DD62  E8C90E  '...'
 	mov	al,bh			; 0000DD65  8AC7  '..'
 	shl	al,0x5			; 0000DD67  C0E005  '...'
 	or	al,bl			; 0000DD6A  0AC3  0x0A,'.'
@@ -10285,7 +10313,7 @@ xdd5d:	and	byte [0x97],0xef	; 0000DD5D  80269700EF  '.&...'
 xdd71:	test	byte [0x97],0x10	; 0000DD71  F606970010  '.....'
 	jnz	xdd81			; 0000DD76  7509  'u.'
 	loop	xdd71			; 0000DD78  E2F7  '..'
-	call	xec2e			; 0000DD7A  E8B10E  '...'
+	call	xec2e_wait_8042_ready	; 0000DD7A  E8B10E  '...'
 	mov	al,0xf4			; 0000DD7D  B0F4  '..'
 	out	0x60,al			; 0000DD7F  E660  '.`'
 xdd81:	and	byte [0x97],0xbf	; 0000DD81  80269700BF  '.&...'
@@ -11608,10 +11636,10 @@ xe964:	call	xbfc3			; 0000E964  E85CD6  '.\.'
 	call	xd215			; 0000E978  E89AE8
 xe97b:	ret				; 0000E97B  C3  '.'
 
-xe97c:	call	xec2e			; 0000E97C  E8AF02  '...'
+xe97c:	call	xec2e_wait_8042_ready	; 0000E97C  E8AF02  '...'
 	mov	al,0xad			; 0000E97F  B0AD  '..'
 	out	0x64,al			; 0000E981  E664  '.d'
-	call	xec2e			; 0000E983  E8A802  '...'
+	call	xec2e_wait_8042_ready	; 0000E983  E8A802  '...'
 	ret				; 0000E986  C3  '.'
 
 	cld				; 0000E987  FC  '.'
@@ -11775,7 +11803,7 @@ xeb0a:	pop	ax			; 0000EB0A  58  'X'
 	ret				; 0000EB0B  C3  '.'
 
 xeb0c:	push	ax			; 0000EB0C  50  'P'
-	call	xec2e			; 0000EB0D  E81E01  '...'
+	call	xec2e_wait_8042_ready	; 0000EB0D  E81E01  '...'
 	mov	al,0xae			; 0000EB10  B0AE  '..'
 	out	0x64,al			; 0000EB12  E664  '.d'
 	pop	ax			; 0000EB14  58  'X'
@@ -11871,20 +11899,20 @@ xebc7:	push	ax			; 0000EBC7  50  'P'
 	call	xec1e			; 0000EBC9  E85200  '.R.'
 	jnz	xec1b			; 0000EBCC  754D  'uM'
 	and	byte [0x97],0xef	; 0000EBCE  80269700EF  '.&...'
-	call	xec2e			; 0000EBD3  E85800  '.X.'
+	call	xec2e_wait_8042_ready	; 0000EBD3  E85800  '.X.'
 	mov	al,0xed			; 0000EBD6  B0ED  '..'
 	out	0x60,al			; 0000EBD8  E660  '.`'
 	mov	cx,0xffff		; 0000EBDA  B9FFFF  '...'
 xebdd:	test	byte [0x97],0x10	; 0000EBDD  F606970010  '.....'
 	jnz	xebef			; 0000EBE2  750B  'u.'
 	loop	xebdd			; 0000EBE4  E2F7  '..'
-	call	xec2e			; 0000EBE6  E84500  '.E.'
+	call	xec2e_wait_8042_ready	; 0000EBE6  E84500  '.E.'
 	mov	al,0xf4			; 0000EBE9  B0F4  '..'
 	out	0x60,al			; 0000EBEB  E660  '.`'
 	jmp	short xec16		; 0000EBED  EB27  '.',0x27
 
 xebef:	and	byte [0x97],0xef	; 0000EBEF  80269700EF  '.&...'
-	call	xec2e			; 0000EBF4  E83700  '.7.'
+	call	xec2e_wait_8042_ready	; 0000EBF4  E83700  '.7.'
 	mov	al,[0x17]		; 0000EBF7  A01700  '...'
 	shr	al,0x4			; 0000EBFA  C0E804  '...'
 	and	al,0x7			; 0000EBFD  2407  '$.'
@@ -11910,6 +11938,8 @@ xec1e:	push	ax			; 0000EC1E  50  'P'
 	pop	ax			; 0000EC2C  58  'X'
 	ret				; 0000EC2D  C3  '.'
 
+xec2e_wait_8042_ready:
+
 xec2e:	push	cx			; 0000EC2E  51  'Q'
 	mov	cx,0x2710		; 0000EC2F  B91027  '..',0x27
 xec32:	in	al,0x64			; 0000EC32  E464  '.d'
@@ -12680,7 +12710,7 @@ xf326:	mov	al,ah			; 0000F326  8AC4  '..'
 
 xf32b:	push	ax			; 0000F32B  50  'P'
 	cli				; 0000F32C  FA  '.'
-	call	xec2e			; 0000F32D  E8FEF8  '...'
+	call	xec2e_wait_8042_ready	; 0000F32D  E8FEF8  '...'
 	mov	al,0xa3			; 0000F330  B0A3  '..'
 	out	0x64,al			; 0000F332  E664  '.d'
 	sti				; 0000F334  FB  '.'
@@ -12688,7 +12718,7 @@ xf32b:	push	ax			; 0000F32B  50  'P'
 	ret				; 0000F336  C3  '.'
 
 xf337:	cli				; 0000F337  FA  '.'
-	call	xec2e			; 0000F338  E8F3F8  '...'
+	call	xec2e_wait_8042_ready	; 0000F338  E8F3F8  '...'
 	mov	al,0xad			; 0000F33B  B0AD  '..'
 	out	0x64,al			; 0000F33D  E664  '.d'
 xf33f:	in	al,0x64			; 0000F33F  E464  '.d'
@@ -12697,10 +12727,10 @@ xf33f:	in	al,0x64			; 0000F33F  E464  '.d'
 	in	al,0x60			; 0000F345  E460  '.`'
 	jmp	short xf33f		; 0000F347  EBF6  '..'
 
-xf349:	call	xec2e			; 0000F349  E8E2F8  '...'
+xf349:	call	xec2e_wait_8042_ready	; 0000F349  E8E2F8  '...'
 	mov	al,0xa5			; 0000F34C  B0A5  '..'
 	out	0x64,al			; 0000F34E  E664  '.d'
-	call	xec2e			; 0000F350  E8DBF8  '...'
+	call	xec2e_wait_8042_ready	; 0000F350  E8DBF8  '...'
 	push	cx			; 0000F353  51  'Q'
 	mov	cx,0x2710		; 0000F354  B91027  '..',0x27
 xf357:	in	al,0x64			; 0000F357  E464  '.d'
@@ -12711,7 +12741,7 @@ xf357:	in	al,0x64			; 0000F357  E464  '.d'
 	in	al,0x60			; 0000F360  E460  '.`'
 xf362:	push	ax			; 0000F362  50  'P'
 	pushf				; 0000F363  9C  '.'
-	call	xec2e			; 0000F364  E8C7F8  '...'
+	call	xec2e_wait_8042_ready	; 0000F364  E8C7F8  '...'
 	mov	al,0xae			; 0000F367  B0AE  '..'
 	out	0x64,al			; 0000F369  E664  '.d'
 	push	cs			; 0000F36B  0E  '.'
@@ -13214,7 +13244,7 @@ xf78e:	mov	al,0x78			; 0000F78E  B078  '.x'
 	in	al,0x60			; 0000F793  E460  '.`'
 	mov	al,0x20			; 0000F795  B020  '. '
 	out	0x64,al			; 0000F797  E664  '.d'
-	call	xec2e			; 0000F799  E892F4  '...'
+	call	xec2e_wait_8042_ready	; 0000F799  E892F4  '...'
 xf79c:	in	al,0x64			; 0000F79C  E464  '.d'
 	test	al,0x1			; 0000F79E  A801  '..'
 	jz	xf79c			; 0000F7A0  74FA  't.'
@@ -13222,19 +13252,19 @@ xf79c:	in	al,0x64			; 0000F79C  E464  '.d'
 	mov	ah,al			; 0000F7A4  8AE0  '..'
 	or	ah,0x4			; 0000F7A6  80CC04  '...'
 	push	ax			; 0000F7A9  50  'P'
-	call	xec2e			; 0000F7AA  E881F4  '...'
+	call	xec2e_wait_8042_ready	; 0000F7AA  E881F4  '...'
 	pop	ax			; 0000F7AD  58  'X'
 	mov	al,0x60			; 0000F7AE  B060  '.`'
 	out	0x64,al			; 0000F7B0  E664  '.d'
 	push	ax			; 0000F7B2  50  'P'
-	call	xec2e			; 0000F7B3  E878F4  '.x.'
+	call	xec2e_wait_8042_ready	; 0000F7B3  E878F4  '.x.'
 	pop	ax			; 0000F7B6  58  'X'
 	mov	al,ah			; 0000F7B7  8AC4  '..'
 	out	0x60,al			; 0000F7B9  E660  '.`'
 	pop	ax			; 0000F7BB  58  'X'
 	mov	al,0x8f			; 0000F7BC  B08F  '..'
 	call	xb549			; 0000F7BE  E888BD  '...'
-	call	xec2e			; 0000F7C1  E86AF4  '.j.'
+	call	xec2e_wait_8042_ready	; 0000F7C1  E86AF4  '.j.'
 	mov	al,0xfe			; 0000F7C4  B0FE  '..'
 	out	0x64,al			; 0000F7C6  E664  '.d'
 xf7c8:	hlt				; 0000F7C8  F4  '.'
diff --git a/devices/pc/bios/compaq/deskpro386/notes.md b/devices/pc/bios/compaq/deskpro386/notes.md
index 4b283e1a5..95de5f734 100644
--- a/devices/pc/bios/compaq/deskpro386/notes.md
+++ b/devices/pc/bios/compaq/deskpro386/notes.md
@@ -230,3 +230,208 @@ But when we stopped here next, it was no longer good:
 	 
 	%00FF0730  0000  0000  0000  0000 - 0000  0000  0000  0000   ................
 	%00FF0740  0000  0000  0000  0000 - 0000  0000  0000  0000   ................
+
+Here's a fresher run:
+
+	id       physaddr   blkaddr   used    size    type		id       physaddr   blkaddr   used    size    type
+	-------- ---------  --------  ------  ------  ----		-------- ---------  --------  ------  ------  ----
+	00040006 %00000000: 00000000  0x8000  0x8000  RAM		00040006 %00000000: 00000000  0x8000  0x8000  RAM
+	00040008 %00008000: 00008000  0x8000  0x8000  RAM		00040008 %00008000: 00008000  0x8000  0x8000  RAM
+	0004000A %00010000: 00010000  0x8000  0x8000  RAM		0004000A %00010000: 00010000  0x8000  0x8000  RAM
+	0004000C %00018000: 00018000  0x8000  0x8000  RAM		0004000C %00018000: 00018000  0x8000  0x8000  RAM
+	0004000E %00020000: 00020000  0x8000  0x8000  RAM		0004000E %00020000: 00020000  0x8000  0x8000  RAM
+	00040010 %00028000: 00028000  0x8000  0x8000  RAM		00040010 %00028000: 00028000  0x8000  0x8000  RAM
+	00040012 %00030000: 00030000  0x8000  0x8000  RAM		00040012 %00030000: 00030000  0x8000  0x8000  RAM
+	00040014 %00038000: 00038000  0x8000  0x8000  RAM		00040014 %00038000: 00038000  0x8000  0x8000  RAM
+	00040016 %00040000: 00040000  0x8000  0x8000  RAM		00040016 %00040000: 00040000  0x8000  0x8000  RAM
+	00040018 %00048000: 00048000  0x8000  0x8000  RAM		00040018 %00048000: 00048000  0x8000  0x8000  RAM
+	0004001A %00050000: 00050000  0x8000  0x8000  RAM		0004001A %00050000: 00050000  0x8000  0x8000  RAM
+	0004001C %00058000: 00058000  0x8000  0x8000  RAM		0004001C %00058000: 00058000  0x8000  0x8000  RAM
+	0004001E %00060000: 00060000  0x8000  0x8000  RAM		0004001E %00060000: 00060000  0x8000  0x8000  RAM
+	00040020 %00068000: 00068000  0x8000  0x8000  RAM		00040020 %00068000: 00068000  0x8000  0x8000  RAM
+	00040022 %00070000: 00070000  0x8000  0x8000  RAM		00040022 %00070000: 00070000  0x8000  0x8000  RAM
+	00040024 %00078000: 00078000  0x8000  0x8000  RAM		00040024 %00078000: 00078000  0x8000  0x8000  RAM
+	00040026 %00080000: 00080000  0x8000  0x8000  RAM		00040026 %00080000: 00080000  0x8000  0x8000  RAM
+	00040028 %00088000: 00088000  0x8000  0x8000  RAM		00040028 %00088000: 00088000  0x8000  0x8000  RAM
+	0004002A %00090000: 00090000  0x8000  0x8000  RAM		0004002A %00090000: 00090000  0x8000  0x8000  RAM
+	0004002C %00098000: 00098000  0x8000  0x8000  RAM		0004002C %00098000: 00098000  0x8000  0x8000  RAM
+	00040088 %000B8000: 000B8000  0x8000  0x8000  VIDEO		000400A0 %000B8000: 000B8000  0x8000  0x8000  VIDEO
+	00040002 %000C0000: 000C0000  0x4000  0x8000  ROM		00040002 %000C0000: 000C0000  0x4000  0x8000  ROM
+															0004003F %000E0000: 000E0000  0x????  0x8000  ROM
+															00040041 %000E8000: 000E0000  0x????  0x8000  ROM
+	00040004 %000F0000: 000F8000  0x8000  0x8000  ROM		00040043 %000F0000: 000E0000  0x????  0x8000  ROM
+	00040004 %000F8000: 000F8000  0x8000  0x8000  ROM		00040045 %000F8000: 000E0000  0x????  0x8000  ROM
+	00040048 %00100000: 00100000  0x8000  0x8000  RAM		00040048 %00100000: 00100000  0x8000  0x8000  RAM
+	0004004A %00108000: 00108000  0x8000  0x8000  RAM		0004004A %00108000: 00108000  0x8000  0x8000  RAM
+	0004004C %00110000: 00110000  0x8000  0x8000  RAM		0004004C %00110000: 00110000  0x8000  0x8000  RAM
+	0004004E %00118000: 00118000  0x8000  0x8000  RAM		0004004E %00118000: 00118000  0x8000  0x8000  RAM
+	00040050 %00120000: 00120000  0x8000  0x8000  RAM		00040050 %00120000: 00120000  0x8000  0x8000  RAM
+	00040052 %00128000: 00128000  0x8000  0x8000  RAM		00040052 %00128000: 00128000  0x8000  0x8000  RAM
+	00040054 %00130000: 00130000  0x8000  0x8000  RAM		00040054 %00130000: 00130000  0x8000  0x8000  RAM
+	00040056 %00138000: 00138000  0x8000  0x8000  RAM		00040056 %00138000: 00138000  0x8000  0x8000  RAM
+	00040058 %00140000: 00140000  0x8000  0x8000  RAM		00040058 %00140000: 00140000  0x8000  0x8000  RAM
+	0004005A %00148000: 00148000  0x8000  0x8000  RAM		0004005A %00148000: 00148000  0x8000  0x8000  RAM
+	0004005C %00150000: 00150000  0x8000  0x8000  RAM		0004005C %00150000: 00150000  0x8000  0x8000  RAM
+	0004005E %00158000: 00158000  0x8000  0x8000  RAM		0004005E %00158000: 00158000  0x8000  0x8000  RAM
+	00040060 %00160000: 00160000  0x8000  0x8000  RAM		00040060 %00160000: 00160000  0x8000  0x8000  RAM
+	00040062 %00168000: 00168000  0x8000  0x8000  RAM		00040062 %00168000: 00168000  0x8000  0x8000  RAM
+	00040064 %00170000: 00170000  0x8000  0x8000  RAM		00040064 %00170000: 00170000  0x8000  0x8000  RAM
+	00040066 %00178000: 00178000  0x8000  0x8000  RAM		00040066 %00178000: 00178000  0x8000  0x8000  RAM
+	00040068 %00180000: 00180000  0x8000  0x8000  RAM		00040068 %00180000: 00180000  0x8000  0x8000  RAM
+	0004006A %00188000: 00188000  0x8000  0x8000  RAM		0004006A %00188000: 00188000  0x8000  0x8000  RAM
+	0004006C %00190000: 00190000  0x8000  0x8000  RAM		0004006C %00190000: 00190000  0x8000  0x8000  RAM
+	0004006E %00198000: 00198000  0x8000  0x8000  RAM		0004006E %00198000: 00198000  0x8000  0x8000  RAM
+	00040070 %001A0000: 001A0000  0x8000  0x8000  RAM		00040070 %001A0000: 001A0000  0x8000  0x8000  RAM
+	00040072 %001A8000: 001A8000  0x8000  0x8000  RAM		00040072 %001A8000: 001A8000  0x8000  0x8000  RAM
+	00040074 %001B0000: 001B0000  0x8000  0x8000  RAM		00040074 %001B0000: 001B0000  0x8000  0x8000  RAM
+	00040076 %001B8000: 001B8000  0x8000  0x8000  RAM		00040076 %001B8000: 001B8000  0x8000  0x8000  RAM
+	00040078 %001C0000: 001C0000  0x8000  0x8000  RAM		00040078 %001C0000: 001C0000  0x8000  0x8000  RAM
+	0004007A %001C8000: 001C8000  0x8000  0x8000  RAM		0004007A %001C8000: 001C8000  0x8000  0x8000  RAM
+	0004007C %001D0000: 001D0000  0x8000  0x8000  RAM		0004007C %001D0000: 001D0000  0x8000  0x8000  RAM
+	0004007E %001D8000: 001D8000  0x8000  0x8000  RAM		0004007E %001D8000: 001D8000  0x8000  0x8000  RAM
+	00040080 %001E0000: 001E0000  0x8000  0x8000  RAM		00040080 %001E0000: 001E0000  0x8000  0x8000  RAM
+	00040082 %001E8000: 001E8000  0x8000  0x8000  RAM		00040082 %001E8000: 001E8000  0x8000  0x8000  RAM
+	00040084 %001F0000: 001F0000  0x8000  0x8000  RAM		00040084 %001F0000: 001F0000  0x8000  0x8000  RAM
+	00040086 %001F8000: 001F8000  0x8000  0x8000  RAM		00040086 %001F8000: 001F8000  0x8000  0x8000  RAM
+	0004002E %00FA0000: 00FA0000  0x8000  0x8000  RAM		0004002E %00FA0000: 00FA0000  0x8000  0x8000  RAM
+	00040030 %00FA8000: 00FA8000  0x8000  0x8000  RAM		00040030 %00FA8000: 00FA8000  0x8000  0x8000  RAM
+	00040032 %00FB0000: 00FB0000  0x8000  0x8000  RAM		00040032 %00FB0000: 00FB0000  0x8000  0x8000  RAM
+	00040034 %00FB8000: 00FB8000  0x8000  0x8000  RAM		00040034 %00FB8000: 00FB8000  0x8000  0x8000  RAM
+	00040036 %00FC0000: 00FC0000  0x8000  0x8000  RAM		00040036 %00FC0000: 00FC0000  0x8000  0x8000  RAM
+	00040038 %00FC8000: 00FC8000  0x8000  0x8000  RAM		00040038 %00FC8000: 00FC8000  0x8000  0x8000  RAM
+	0004003A %00FD0000: 00FD0000  0x8000  0x8000  RAM		0004003A %00FD0000: 00FD0000  0x8000  0x8000  RAM
+	0004003C %00FD8000: 00FD8000  0x8000  0x8000  RAM		0004003C %00FD8000: 00FD8000  0x8000  0x8000  RAM
+	0004003E %00FE0000: 00FE0000  0x8000  0x8000  RAM		0004003E %00FE0000: 00FE0000  0x8000  0x8000  RAM
+	00040040 %00FE8000: 00FE8000  0x8000  0x8000  RAM		00040040 %00FE8000: 00FE8000  0x8000  0x8000  RAM
+	00040042 %00FF0000: 00FF0000  0x8000  0x8000  RAM		00040042 %00FF0000: 00FF0000  0x8000  0x8000  RAM
+	00040044 %00FF8000: 00FF8000  0x8000  0x8000  RAM		00040044 %00FF8000: 00FF8000  0x8000  0x8000  RAM
+	00040046 %80C00000: 80C00000  0x0001  0x8000  H/W		00040046 %80C00000: 80C00000  0x0001  0x8000  H/W
+	00040004 %FFFF0000: 000F8000  0x8000  0x8000  ROM		00040004 %FFFF0000: 000F8000  0x8000  0x8000  ROM
+	00040004 %FFFF8000: 000F8000  0x8000  0x8000  ROM		00040004 %FFFF8000: 000F8000  0x8000  0x8000  ROM
+																
+	running											 		
+	notice: PIC0(0x20): unsupported OCW2 automatic EOI command: 0x00
+	stopped (149 ops, 622 cycles, 20 ms, 31100 hz)
+	EAX=0000F000 EBX=00000000 ECX=00000008 EDX=00000020 
+	ESP=00000000 EBP=00000000 ESI=0000F8E7 EDI=00000000 
+	SS=0000 DS=F000 ES=0000 FS=0000 GS=0304 PS=00000046 V0 D0 I0 T0 S0 Z1 A0 P1 C0 
+	F000:F9ED E6A0          OUT      A0,AL
+	running
+	notice: PIC1(0xA0): unsupported OCW2 automatic EOI command: 0x00
+	stopped (150 ops, 5 cycles, 17 ms, 294 hz)
+	EAX=0000F000 EBX=00000000 ECX=00000008 EDX=00000020 
+	ESP=00000000 EBP=00000000 ESI=0000F8E7 EDI=00000000 
+	SS=0000 DS=F000 ES=0000 FS=0000 GS=0304 PS=00000046 V0 D0 I0 T0 S0 Z1 A0 P1 C0 
+	F000:F9EF B009          MOV      AL,09
+	running
+	notice: PIC0(0x20): unsupported OCW2 automatic EOI command: 0x00
+	stopped (19729382 ops, 89821236 cycles, 6351 ms, 14142849 hz)
+	EAX=0000F000 EBX=00000006 ECX=00000008 EDX=00000020 
+	ESP=00000000 EBP=00000000 ESI=0000F8E7 EDI=00000000 
+	SS=0000 DS=F000 ES=0000 FS=0000 GS=0000 PS=00000046 V0 D0 I0 T0 S0 Z1 A0 P1 C0 
+	F000:F9ED E6A0          OUT      A0,AL
+	running
+	notice: PIC1(0xA0): unsupported OCW2 automatic EOI command: 0x00
+	stopped (19729383 ops, 5 cycles, 15 ms, 333 hz)
+	EAX=0000F000 EBX=00000006 ECX=00000008 EDX=00000020 
+	ESP=00000000 EBP=00000000 ESI=0000F8E7 EDI=00000000 
+	SS=0000 DS=F000 ES=0000 FS=0000 GS=0000 PS=00000046 V0 D0 I0 T0 S0 Z1 A0 P1 C0 
+	F000:F9EF B009          MOV      AL,09
+	running
+	notice: PIC0(0x20): unsupported OCW2 automatic EOI command: 0x00
+	stopped (25359063 ops, 12731563 cycles, 1260 ms, 10104415 hz)
+	EAX=0000F000 EBX=00000003 ECX=00000008 EDX=00000020 
+	ESP=00000000 EBP=00000000 ESI=0000F8E7 EDI=00000000 
+	SS=0000 DS=F000 ES=0000 FS=0000 GS=0000 PS=00000046 V0 D0 I0 T0 S0 Z1 A0 P1 C0 
+	F000:F9ED E6A0          OUT      A0,AL
+	running
+	notice: PIC1(0xA0): unsupported OCW2 automatic EOI command: 0x00
+	stopped (25359064 ops, 5 cycles, 17 ms, 294 hz)
+	EAX=0000F000 EBX=00000003 ECX=00000008 EDX=00000020 
+	ESP=00000000 EBP=00000000 ESI=0000F8E7 EDI=00000000 
+	SS=0000 DS=F000 ES=0000 FS=0000 GS=0000 PS=00000046 V0 D0 I0 T0 S0 Z1 A0 P1 C0 
+	F000:F9EF B009          MOV      AL,09
+	running
+	stopped (27129586 ops, 2209813 cycles, 382 ms, 5784851 hz)
+	EAX=000098FC EBX=0000E000 ECX=00000000 EDX=00000000 
+	ESP=000000E4 EBP=00000000 ESI=0000FFFF EDI=00007FBE 
+	SS=0028[00000300,FFFF] DS=0050[80C00000,FFFF] ES=0048[00FF0000,FFFF] 
+	CS=0030[000F0000,FFFF] FS=0000[00000000,FFFF] GS=0304[00003040,FFFF]
+	LD=0000[00000000,0000] GD=[0001C000,005F] ID=[000FF821,0007] TR=0000 A20=ON 
+	CR0=0000FFF1 CR2=00000000 CR3=00000000 PS=00000083 V0 D0 I0 T0 S1 Z0 A0 P0 C1 
+	0030:863C 1F            POP      DS
+	
+	
+	
+	
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diff --git a/modules/pcjs/lib/chipset.js b/modules/pcjs/lib/chipset.js
index 90b66c7a5..84be23307 100644
--- a/modules/pcjs/lib/chipset.js
+++ b/modules/pcjs/lib/chipset.js
@@ -765,7 +765,7 @@ ChipSet.KBC = {
     STATUS: {                   // this.b8042Status (on read from port 0x64)
         PORT:           0x64,
         OUTBUFF_FULL:   0x01,
-        INBUFF_FULL:    0x02,   // set if the controller has received but not yet read data written to the input buffer (not normally set)
+        INBUFF_FULL:    0x02,   // set if the controller has received but not yet read data from the input buffer (not normally set)
         SYS_FLAG:       0x04,
         CMD_FLAG:       0x08,   // set on write to KBC.CMD (port 0x64), clear on write to KBC.DATA (port 0x60)
         NO_INHIBIT:     0x10,   // (in Compaq parlance: security lock not engaged)
diff --git a/modules/pcjs/lib/debugger.js b/modules/pcjs/lib/debugger.js
index d9731fd60..1ee00ab19 100644
--- a/modules/pcjs/lib/debugger.js
+++ b/modules/pcjs/lib/debugger.js
@@ -699,10 +699,10 @@ if (DEBUGGER) {
     /* 0x61 */ [Debugger.INS.POPA,  Debugger.TYPE_NONE   | Debugger.TYPE_80286],
     /* 0x62 */ [Debugger.INS.BOUND, Debugger.TYPE_REG    | Debugger.TYPE_WORDV | Debugger.TYPE_IN   | Debugger.TYPE_80286, Debugger.TYPE_MEM   | Debugger.TYPE_WORD2 | Debugger.TYPE_IN],
     /* 0x63 */ [Debugger.INS.ARPL,  Debugger.TYPE_MODRM  | Debugger.TYPE_WORD  | Debugger.TYPE_OUT,                        Debugger.TYPE_REG   | Debugger.TYPE_WORD  | Debugger.TYPE_IN],
-    /* 0x64 */ [Debugger.INS.FS,    Debugger.TYPE_NONE   | Debugger.TYPE_80386],
-    /* 0x65 */ [Debugger.INS.GS,    Debugger.TYPE_NONE   | Debugger.TYPE_80386],
-    /* 0x66 */ [Debugger.INS.OS,    Debugger.TYPE_NONE   | Debugger.TYPE_80386],
-    /* 0x67 */ [Debugger.INS.AS,    Debugger.TYPE_NONE   | Debugger.TYPE_80386],
+    /* 0x64 */ [Debugger.INS.FS,    Debugger.TYPE_PREFIX | Debugger.TYPE_80386],
+    /* 0x65 */ [Debugger.INS.GS,    Debugger.TYPE_PREFIX | Debugger.TYPE_80386],
+    /* 0x66 */ [Debugger.INS.OS,    Debugger.TYPE_PREFIX | Debugger.TYPE_80386],
+    /* 0x67 */ [Debugger.INS.AS,    Debugger.TYPE_PREFIX | Debugger.TYPE_80386],
 
     /* 0x68 */ [Debugger.INS.PUSH,  Debugger.TYPE_IMM    | Debugger.TYPE_WORDV | Debugger.TYPE_IN   | Debugger.TYPE_80286],
     /* 0x69 */ [Debugger.INS.IMUL,  Debugger.TYPE_REG    | Debugger.TYPE_WORD  | Debugger.TYPE_BOTH | Debugger.TYPE_80286,   Debugger.TYPE_MODRM | Debugger.TYPE_WORDIW | Debugger.TYPE_IN],
@@ -2913,7 +2913,6 @@ if (DEBUGGER) {
              * If you want to create a real-mode breakpoint that will break regardless of mode,
              * use the physical address of the real-mode memory location instead.
              */
-
             if (addr == this.mapBreakpoint(this.getAddr(aAddrBreak))) {
                 if (aAddrBreak[3]) {
                     this.findBreakpoint(aBreak, aAddrBreak, true);
@@ -2943,11 +2942,14 @@ if (DEBUGGER) {
         var bOpcode = this.getByte(aAddr, 1);
 
         /*
-         * Prior to calling getInstruction(), doUnassemble() checks for these prefixes as well,
-         * updating aAddr[4] and/or aAddr[5] as appropriate; if that's been done, then let's suppress
-         * the display of those prefixes and simply incorporate them into the byte stream.
+         * Incorporate the following prefixes into the current instruction's byte stream
          */
-        if (aAddr[4] != null && bOpcode == X86.OPCODE.OS || aAddr[5] != null && bOpcode == X86.OPCODE.AS) {
+        if (bOpcode == X86.OPCODE.OS || bOpcode == X86.OPCODE.AS) {
+            if (bOpcode == X86.OPCODE.OS) {
+                aAddr[4] = !aAddr[4];
+            } else {
+                aAddr[5] = !aAddr[5];
+            }
             bOpcode = this.getByte(aAddr, 1);
         }
 
@@ -2976,7 +2978,10 @@ if (DEBUGGER) {
         }
 
         var typeCPU = null;
+        var fNonPrefix = true;
+
         for (var iOperand = 1; iOperand <= cOperands; iOperand++) {
+
             var sOperand = "";
             var type = aOpDesc[iOperand];
             if (type === undefined) continue;
@@ -2984,8 +2989,13 @@ if (DEBUGGER) {
             if (typeCPU == null) typeCPU = type >> Debugger.TYPE_CPU_SHIFT;
 
             var typeSize = type & Debugger.TYPE_SIZE;
-            if (typeSize == Debugger.TYPE_NONE || typeSize == Debugger.TYPE_PREFIX) continue;
-
+            if (typeSize == Debugger.TYPE_NONE) {
+                continue;
+            }
+            if (typeSize == Debugger.TYPE_PREFIX) {
+                fNonPrefix = false;
+                continue;
+            }
             var typeMode = type & Debugger.TYPE_MODE;
             if (typeMode >= Debugger.TYPE_MODRM) {
                 if (bModRM < 0) {
@@ -3053,7 +3063,7 @@ if (DEBUGGER) {
             sComment = Debugger.CPUS[typeCPU] + " CPU only";
         }
 
-        if (sComment) {
+        if (sComment && fNonPrefix) {
             sLine = str.pad(sLine, 52) + ';' + sComment;
             if (!this.cpu.aFlags.fChecksum) {
                 sLine += (nSequence != null? '=' + nSequence.toString() : "");
@@ -3062,6 +3072,8 @@ if (DEBUGGER) {
                 sLine += "cycles=" + nCycles.toString() + " cs=" + str.toHex(this.cpu.aCounts.nChecksum);
             }
         }
+
+        this.initAddrSize(aAddr, fNonPrefix);
         return sLine;
     };
 
@@ -3851,8 +3863,8 @@ if (DEBUGGER) {
     Debugger.prototype.doAssemble = function(asArgs)
     {
         var aAddr = this.parseAddr(asArgs[1], Debugger.ADDR_CODE);
-        if (aAddr[0] == null)
-            return;
+        if (aAddr[0] == null) return;
+
         this.aAddrAssemble = aAddr;
         if (asArgs[2] === undefined) {
             this.println("begin assemble @" + this.hexAddr(aAddr));
@@ -3860,6 +3872,7 @@ if (DEBUGGER) {
             this.cpu.updateCPU();
             return;
         }
+
         var aOpBytes = this.parseInstruction(asArgs[2], asArgs[3], aAddr);
         if (aOpBytes.length) {
             for (var i = 0; i < aOpBytes.length; i++) {
@@ -4040,7 +4053,7 @@ if (DEBUGGER) {
             }
         }
         var aAddr = this.parseAddr(sAddr, Debugger.ADDR_DATA);
-        if (aAddr[0] == null) return;
+        if (aAddr[0] == null || aAddr[0] == -1 && aAddr[2] == null) return;
 
         var sDump = "";
         if (BACKTRACK && sCmd == "di") {
@@ -4201,10 +4214,10 @@ if (DEBUGGER) {
                 var aAddr = aHistory[iHistory];
                 if (aAddr[1] == null) break;
                 /*
-                 * We must create a new aAddr from the address we obtained from aHistory, because
-                 * aAddr was a reference, not a copy, and we don't want getInstruction() modifying the original.
+                 * We must create a new aAddr from the address we obtained from aHistory, because aAddr
+                 * was a reference, not a copy, and we don't want getInstruction() modifying the original.
                  *
-                 * TODO: By using a new address for each line, history dumps fail to disassemble 32-bit overrides properly.
+                 * TODO: By using a new address each time, history dumps will not disassemble 32-bit overrides properly.
                  */
                 aAddr = this.newAddr(aAddr[0], aAddr[1], aAddr[2]);
                 this.println(this.getInstruction(aAddr, "history", n));
@@ -4887,6 +4900,10 @@ if (DEBUGGER) {
                 case X86.OPCODE.CS:
                 case X86.OPCODE.SS:
                 case X86.OPCODE.DS:
+                case X86.OPCODE.FS:     // I386 only
+                case X86.OPCODE.GS:     // I386 only
+                case X86.OPCODE.OS:     // I386 only
+                case X86.OPCODE.AS:     // I386 only
                 case X86.OPCODE.LOCK:
                     this.incAddr(aAddr, 1);
                     fPrefix = true;
@@ -4915,10 +4932,10 @@ if (DEBUGGER) {
                         this.incAddr(aAddr, 5);
                     }
                     break;
-                case X86.OPCODE.CALLW & 0xff:
+                case X86.OPCODE.GRP4W:
                     if (fCallStep) {
-                        var sIns = this.getInstruction(aAddr);
-                        this.fProcStep = (sIns.indexOf("CALL") >= 0? fProcStep : 0);
+                        var w = this.getWord(aAddr) & X86.OPCODE.CALLMASK;
+                        this.fProcStep = ((w == X86.OPCODE.CALLW || w == X86.OPCODE.CALLFDW)? fProcStep : 0);
                     }
                     break;
                 case X86.OPCODE.REPZ:
@@ -4999,20 +5016,29 @@ if (DEBUGGER) {
     };
 
     /**
-     * isPrefixIns(bOpcode)
+     * initAddrSize(aAddr, fNonPrefix)
      *
      * @this {Debugger}
-     * @param {number} bOpcode
-     * @return {boolean} true if prefix, false if not
+     * @param {Array} aAddr
+     * @param {boolean} fNonPrefix
      */
-    Debugger.prototype.isPrefixIns = function(bOpcode)
+    Debugger.prototype.initAddrSize = function(aAddr, fNonPrefix)
     {
-        return (bOpcode == X86.OPCODE.ES || bOpcode == X86.OPCODE.CS || bOpcode == X86.OPCODE.SS || bOpcode == X86.OPCODE.DS ||
-                bOpcode == X86.OPCODE.FS || bOpcode == X86.OPCODE.GS || bOpcode == X86.OPCODE.OS || bOpcode == X86.OPCODE.AS ||
-                bOpcode == X86.OPCODE.LOCK ||
-                bOpcode == X86.OPCODE.REPNZ ||
-                bOpcode == X86.OPCODE.REPZ
-        );
+        /*
+         * For proper disassembly of instructions preceded by an OPERAND (0x66) size prefix, we set aAddr[4]
+         * to true whenever the operand size is 32-bit; similarly, for an ADDRESS (0x67) size prefix, we set
+         * aAddr[5] to true whenever the address size is 32-bit.  Initially, both fields must be set to match
+         * the size of the current code segment.
+         */
+        if (fNonPrefix) {
+            aAddr[4] = (this.cpu.segCS.dataSize == 4);
+            aAddr[5] = (this.cpu.segCS.addrSize == 4);
+        }
+        /*
+         * We also use aAddr[6] to record whether the caller (ie, getInstruction()) is reporting that it
+         * processed a complete instruction (ie, a non-prefix) or not.
+         */
+        aAddr[6] = fNonPrefix;
     };
 
     /**
@@ -5065,43 +5091,12 @@ if (DEBUGGER) {
         var fBlank = (aAddr[0] != this.aAddrNextCode[0]);
 
         var cLines = 0;
-        var fInitSize = true;
+        this.initAddrSize(aAddr, true);
+
         while (cb > 0 && n--) {
             var bOpcode = this.getByte(aAddr);
             var addr = aAddr[2];
             var nSequence = (this.isBusy(false) || this.fProcStep)? this.nCycles : null;
-            /*
-             * We don't want to leave the disassembly ending on a prefix, especially now that stepCPU(0) continues
-             * executing until it reaches a non-prefix instruction.  So if a prefix is the last instruction, bump the
-             * count and force one more instruction to be disassembled.
-             */
-            if (fInitSize) {
-                /*
-                 * For proper disassembly of instructions preceded by an OPERAND (0x66) size prefix, we set aAddr[4]
-                 * to true whenever the operand size is 32-bit; similarly, for an ADDRESS (0x67) size prefix, we set
-                 * aAddr[5] to true whenever the address size is 32-bit.  Initially, both fields must be set to match
-                 * the size of the current code segment.
-                 */
-                aAddr[4] = (this.cpu.segCS.dataSize == 4);
-                aAddr[5] = (this.cpu.segCS.addrSize == 4);
-                fInitSize = false;
-            }
-            if (this.isPrefixIns(bOpcode)) {
-                if (bOpcode == X86.OPCODE.OS) {
-                    aAddr[4] = !aAddr[4];
-                } else if (bOpcode == X86.OPCODE.AS) {
-                    aAddr[5] = !aAddr[5];
-                } else {
-                    /*
-                     * For all prefixes (except for the OPERAND and ADDRESS overrides, which getInstruction()
-                     * now incorporates into the instruction), we will want to dump an additional instruction.
-                     */
-                    if (!n) n++;
-                    nSequence = null;
-                }
-            } else {
-                fInitSize = true;
-            }
             var sComment = (nSequence != null? "cycles" : null);
             var aSymbol = this.findSymbolAtAddr(aAddr);
             if (aSymbol[0]) {
@@ -5116,6 +5111,14 @@ if (DEBUGGER) {
                 nSequence = null;
             }
             var sIns = this.getInstruction(aAddr, sComment, nSequence);
+
+            /*
+             * If getInstruction() reported that it did not yet process a complete instruction (via aAddr[6]),
+             * then bump the instruction count by one, so that we display one more line (and hopefully the complete
+             * instruction).
+             */
+            if (!aAddr[6] && !n) n++;
+
             this.println(sIns);
             this.aAddrNextCode = aAddr;
             cb -= aAddr[2] - addr;
diff --git a/modules/pcjs/lib/memory.js b/modules/pcjs/lib/memory.js
index 729e03293..3495da162 100644
--- a/modules/pcjs/lib/memory.js
+++ b/modules/pcjs/lib/memory.js
@@ -249,6 +249,7 @@ Memory.prototype = {
          * presumably produced merely to become a clone.
          */
         this.id = mem.id | 0x1;
+        this.used = mem.used;
         this.size = mem.size;
         if (type) {
             this.type = type;
diff --git a/modules/pcjs/lib/ram.js b/modules/pcjs/lib/ram.js
index 61fb0bc5a..6cd40d45b 100644
--- a/modules/pcjs/lib/ram.js
+++ b/modules/pcjs/lib/ram.js
@@ -293,16 +293,44 @@ CompaqController.MAPPINGS = {
 
 /*
  * Bit definitions for the 8-bit read-only settings/diagnostics register (bSettings)
+ *
+ * SW1-7 and SW1-8 are mapped to bits 5 and 4 of bSettings, respectively, as follows:
+ *
+ *      SW1-7   SW1-8   Bit5    Bit4    Amount (of base memory provided by the Compaq 32-bit memory board)
+ *      -----   -----   ----    ----    ------
+ *        ON      ON      0       0     640Kb
+ *        ON      OFF     0       1     Invalid
+ *        OFF     ON      1       0     512Kb
+ *        OFF     OFF     1       1     256Kb
+ *
+ * Other SW1 switches include:
+ *
+ *      SW1-1:  ON enables fail-safe timer
+ *      SW1-2:  ON indicates 80387 coprocessor installed
+ *      SW1-3:  ON sets the memory from 0xC00000 to 0xFFFFFF (between 12 megabytes and 16 megabytes) non-cacheable
+ *      SW1-4:  ON select AUTO system speed (OFF selects HIGH system speed)
+ *      SW1-5:  RESERVED (however, the system can read its state; see below)
+ *      SW1-6:  Compaq Dual-Mode Monitor or Color Monitor (OFF selects Monochrome monitor other than Compaq)
+ *
+ * While SW1-7 and SW1-8 are connected to this memory-mapped register, other SW1 DIP switches are accessible through
+ * the 8042 Keyboard Controller KBC.INPORT register, as follows:
+ *
+ *      SW1-1:  TODO: Determine
+ *      SW1-2:  ChipSet.KBC.INPORT.COMPAQ_NO80387 clear if ON, set (0x04) if OFF
+ *      SW1-3:  TODO: Determine
+ *      SW1-4:  ChipSet.KBC.INPORT.COMPAQ_HISPEED clear if ON, set (0x10) if OFF
+ *      SW1-5:  ChipSet.KBC.INPORT.COMPAQ_DIP5OFF clear if ON, set (0x20) if OFF
+ *      SW1-6:  ChipSet.KBC.INPORT.COMPAQ_NONDUAL clear if ON, set (0x40) if OFF
  */
 CompaqController.SETTINGS = {
     B0_PARITY:  0x01,
     B1_PARITY:  0x02,
     B2_PARITY:  0x04,
     B3_PARITY:  0x08,
-    BASE_640KB: 0x00,
-    BASE_ERROR: 0x10,
-    BASE_512KB: 0x20,
-    BASE_256KB: 0x30,
+    BASE_640KB: 0x00,           // SW1-7,8: ON  ON   Bits 5,4: 00
+    BASE_ERROR: 0x10,           // SW1-7,8: ON  OFF  Bits 5,4: 01
+    BASE_512KB: 0x20,           // SW1-7,8: OFF ON   Bits 5,4: 10
+    BASE_256KB: 0x30,           // SW1-7,8: OFF OFF  Bits 5,4: 11
     ADDED_1MB:  0x40,
     PIGGYBACK:  0x80
 };
diff --git a/modules/pcjs/lib/x86.js b/modules/pcjs/lib/x86.js
index df10b61f5..24889d1fc 100644
--- a/modules/pcjs/lib/x86.js
+++ b/modules/pcjs/lib/x86.js
@@ -392,8 +392,10 @@ var X86 = {
         LOCK:       0xF0,       // opLOCK()
         REPNZ:      0xF2,       // opREPNZ()
         REPZ:       0xF3,       // opREPZ()
-        CALLW:      0x10FF,     // fnCALLw()
-        CALLDW:     0x18FF,     // fnCALLFdw()
+        GRP4W:      0xFF,
+        CALLW:      0x10FF,     // GRP4W: fnCALLw()
+        CALLFDW:    0x18FF,     // GRP4W: fnCALLFdw()
+        CALLMASK:   0x38FF,     // mask 2-byte GRP4W opcodes with this before comparing to CALLW or CALLFDW
         UD2:        0x0B0F      // UD2 (invalid opcode "guaranteed" to generate UD_FAULT on all post-8086 processors)
     }
 };