Minimal infrastructure for instantiating a PDP-10 test machine
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@ -75,18 +75,6 @@ var PDP10 = {
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/*
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* CPU model numbers (supported)
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*
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* The 11/20 includes the 11/10, which is not identified separately because there was
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* nothing functionally different about it.
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*
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* The 11/40 added the MODE bits to the PSW (but only KERNEL=00 and USER=11) and 18-bit
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* addressing via an MMU; there was still only one register set.
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*
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* The 11/45 added REGSET bit to the PSW (to support a second register set), SUPER=01
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* mode to the existing KERNEL=00 and USER=11 modes, separate I/D spaces, and other MMU
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* extensions (eg, MMR1 and MMR3).
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*
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* The 11/70 added 22-bit addressing and corresponding extensions to the MMU.
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*/
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MODEL_KA10: 1001,
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