Added resume support for saving/restoring all active timers and IRQs, along with the run/stop state of the CPU
This commit is contained in:
Jeff Parsons
Jeff Parsons
parent
fac5c3c57d
commit
bb24ccaca6
12 changed files with 844 additions and 671 deletions
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@ -36,6 +36,7 @@ if (NODE) {
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var Str = require("../../shared/es6/strlib");
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var Web = require("../../shared/es6/weblib");
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var Component = require("../../shared/es6/component");
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var State = require("../../shared/es6/state");
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var PDP11 = require("./defines");
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var BusPDP11 = require("./bus");
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var MemoryPDP11 = require("./memory");
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@ -62,7 +63,7 @@ class DevicePDP11 extends Component {
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super("Device", parmsDevice, DevicePDP11, MessagesPDP11.DEVICE);
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this.kw11 = { // KW11 registers
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csr: 0,
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lks: PDP11.KW11.LKS.MON,
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timer: -1 // initBus() will initialize this timer ID
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};
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}
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@ -111,18 +112,18 @@ class DevicePDP11 extends Component {
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{
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if (DEBUGGER) {
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var cpu = this.cpu;
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this.dumpRegs("KIPDR", cpu.mmuPDR[0], 0, asArgs[0]);
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this.dumpRegs("KDPDR", cpu.mmuPDR[0], 8, asArgs[0]);
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this.dumpRegs("KIPAR", cpu.mmuPAR[0], 0, asArgs[0]);
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this.dumpRegs("KDPAR", cpu.mmuPAR[0], 8, asArgs[0], true);
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this.dumpRegs("SIPDR", cpu.mmuPDR[1], 0, asArgs[0]);
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this.dumpRegs("SDPDR", cpu.mmuPDR[1], 8, asArgs[0]);
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this.dumpRegs("SIPAR", cpu.mmuPAR[1], 0, asArgs[0]);
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this.dumpRegs("SDPAR", cpu.mmuPAR[1], 8, asArgs[0], true);
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this.dumpRegs("UIPDR", cpu.mmuPDR[3], 0, asArgs[0]);
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this.dumpRegs("UDPDR", cpu.mmuPDR[3], 8, asArgs[0]);
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this.dumpRegs("UIPAR", cpu.mmuPAR[3], 0, asArgs[0]);
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this.dumpRegs("UDPAR", cpu.mmuPAR[3], 8, asArgs[0], true);
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this.dumpRegs("KIPDR", cpu.regsPDR[0], 0, asArgs[0]);
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this.dumpRegs("KDPDR", cpu.regsPDR[0], 8, asArgs[0]);
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this.dumpRegs("KIPAR", cpu.regsPAR[0], 0, asArgs[0]);
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this.dumpRegs("KDPAR", cpu.regsPAR[0], 8, asArgs[0], true);
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this.dumpRegs("SIPDR", cpu.regsPDR[1], 0, asArgs[0]);
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this.dumpRegs("SDPDR", cpu.regsPDR[1], 8, asArgs[0]);
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this.dumpRegs("SIPAR", cpu.regsPAR[1], 0, asArgs[0]);
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this.dumpRegs("SDPAR", cpu.regsPAR[1], 8, asArgs[0], true);
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this.dumpRegs("UIPDR", cpu.regsPDR[3], 0, asArgs[0]);
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this.dumpRegs("UDPDR", cpu.regsPDR[3], 8, asArgs[0]);
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this.dumpRegs("UIPAR", cpu.regsPAR[3], 0, asArgs[0]);
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this.dumpRegs("UDPAR", cpu.regsPAR[3], 8, asArgs[0], true);
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if (cpu.regMMR3 & PDP11.MMR3.UNIBUS_MAP) {
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this.dumpRegs("UNIMAP", cpu.regsUniMap, -1, asArgs[0]);
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}
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@ -167,6 +168,39 @@ class DevicePDP11 extends Component {
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}
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}
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/**
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* powerUp(data, fRepower)
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*
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* @this {DevicePDP11}
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* @param {Object|null} data
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* @param {boolean} [fRepower]
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* @return {boolean} true if successful, false if failure
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*/
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powerUp(data, fRepower)
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{
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if (!fRepower) {
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if (!data) {
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this.reset();
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} else {
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if (!this.restore(data)) return false;
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}
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}
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return true;
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}
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/**
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* powerDown(fSave, fShutdown)
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*
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* @this {DevicePDP11}
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* @param {boolean} [fSave]
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* @param {boolean} [fShutdown]
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* @return {Object|boolean} component state if fSave; otherwise, true if successful, false if failure
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*/
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powerDown(fSave, fShutdown)
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{
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return fSave? this.save() : true;
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}
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/**
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* reset()
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*
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@ -178,6 +212,45 @@ class DevicePDP11 extends Component {
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this.cpu.setTimer(this.kw11.timer, 1000/60, true);
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}
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/**
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* save()
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*
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* This implements save support for the DevicePDP11 component.
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*
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* @this {DevicePDP11}
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* @return {Object}
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*/
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save()
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{
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var state = new State(this);
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state.set(0, [
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this.kw11.lks
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]);
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return state.data();
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}
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/**
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* restore(data)
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*
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* This implements restore support for the DevicePDP11 component.
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*
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* @this {DevicePDP11}
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* @param {Object} data
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* @return {boolean} true if successful, false if failure
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*/
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restore(data)
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{
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/*
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* ES6 ALERT: Gotta love these destructuring assignments, which make it easy to perform the
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* inverse of what save() does when it collects a bunch of object properties into an array.
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*/
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[
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this.kw11.lks
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] = data[0];
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return true;
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}
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/**
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* interruptKW11()
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*
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@ -350,7 +423,7 @@ class DevicePDP11 extends Component {
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readSIPDR(addr)
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{
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var reg = (addr >> 1) & 7;
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return this.cpu.mmuPDR[1][reg];
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return this.cpu.regsPDR[1][reg];
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}
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/**
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@ -363,7 +436,7 @@ class DevicePDP11 extends Component {
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writeSIPDR(data, addr)
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{
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var reg = (addr >> 1) & 7;
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this.cpu.mmuPDR[1][reg] = data & 0xff0f;
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this.cpu.regsPDR[1][reg] = data & 0xff0f;
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}
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/**
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@ -376,7 +449,7 @@ class DevicePDP11 extends Component {
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readSDPDR(addr)
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{
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var reg = ((addr >> 1) & 7) + 8;
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return this.cpu.mmuPDR[1][reg];
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return this.cpu.regsPDR[1][reg];
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}
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/**
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@ -389,7 +462,7 @@ class DevicePDP11 extends Component {
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writeSDPDR(data, addr)
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{
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var reg = ((addr >> 1) & 7) + 8;
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this.cpu.mmuPDR[1][reg] = data & 0xff0f;
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this.cpu.regsPDR[1][reg] = data & 0xff0f;
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}
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/**
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@ -402,7 +475,7 @@ class DevicePDP11 extends Component {
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readSIPAR(addr)
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{
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var reg = (addr >> 1) & 7;
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return this.cpu.mmuPAR[1][reg];
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return this.cpu.regsPAR[1][reg];
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}
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/**
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@ -415,8 +488,8 @@ class DevicePDP11 extends Component {
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writeSIPAR(data, addr)
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{
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var reg = (addr >> 1) & 7;
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this.cpu.mmuPAR[1][reg] = data;
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this.cpu.mmuPDR[1][reg] &= 0xff0f;
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this.cpu.regsPAR[1][reg] = data;
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this.cpu.regsPDR[1][reg] &= 0xff0f;
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}
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@ -430,7 +503,7 @@ class DevicePDP11 extends Component {
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readSDPAR(addr)
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{
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var reg = ((addr >> 1) & 7) + 8;
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return this.cpu.mmuPAR[1][reg];
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return this.cpu.regsPAR[1][reg];
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}
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/**
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@ -443,8 +516,8 @@ class DevicePDP11 extends Component {
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writeSDPAR(data, addr)
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{
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var reg = ((addr >> 1) & 7) + 8;
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this.cpu.mmuPAR[1][reg] = data;
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this.cpu.mmuPDR[1][reg] &= 0xff0f;
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this.cpu.regsPAR[1][reg] = data;
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this.cpu.regsPDR[1][reg] &= 0xff0f;
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}
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/**
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@ -457,7 +530,7 @@ class DevicePDP11 extends Component {
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readKIPDR(addr)
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{
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var reg = (addr >> 1) & 7;
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return this.cpu.mmuPDR[0][reg];
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return this.cpu.regsPDR[0][reg];
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}
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/**
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@ -470,7 +543,7 @@ class DevicePDP11 extends Component {
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writeKIPDR(data, addr)
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{
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var reg = (addr >> 1) & 7;
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this.cpu.mmuPDR[0][reg] = data & 0xff0f;
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this.cpu.regsPDR[0][reg] = data & 0xff0f;
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}
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/**
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@ -483,7 +556,7 @@ class DevicePDP11 extends Component {
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readKDPDR(addr)
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{
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var reg = ((addr >> 1) & 7) + 8;
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return this.cpu.mmuPDR[0][reg];
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return this.cpu.regsPDR[0][reg];
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}
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/**
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@ -496,7 +569,7 @@ class DevicePDP11 extends Component {
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writeKDPDR(data, addr)
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{
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var reg = ((addr >> 1) & 7) + 8;
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this.cpu.mmuPDR[0][reg] = data & 0xff0f;
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this.cpu.regsPDR[0][reg] = data & 0xff0f;
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}
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/**
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@ -509,7 +582,7 @@ class DevicePDP11 extends Component {
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readKIPAR(addr)
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{
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var reg = (addr >> 1) & 7;
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return this.cpu.mmuPAR[0][reg];
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return this.cpu.regsPAR[0][reg];
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}
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/**
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@ -522,8 +595,8 @@ class DevicePDP11 extends Component {
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writeKIPAR(data, addr)
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{
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var reg = (addr >> 1) & 7;
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this.cpu.mmuPAR[0][reg] = data;
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this.cpu.mmuPDR[0][reg] &= 0xff0f;
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this.cpu.regsPAR[0][reg] = data;
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this.cpu.regsPDR[0][reg] &= 0xff0f;
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}
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@ -537,7 +610,7 @@ class DevicePDP11 extends Component {
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readKDPAR(addr)
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{
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var reg = ((addr >> 1) & 7) + 8;
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return this.cpu.mmuPAR[0][reg];
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return this.cpu.regsPAR[0][reg];
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}
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/**
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@ -550,8 +623,8 @@ class DevicePDP11 extends Component {
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writeKDPAR(data, addr)
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{
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var reg = ((addr >> 1) & 7) + 8;
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this.cpu.mmuPAR[0][reg] = data;
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this.cpu.mmuPDR[0][reg] &= 0xff0f;
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this.cpu.regsPAR[0][reg] = data;
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this.cpu.regsPDR[0][reg] &= 0xff0f;
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}
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/**
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@ -564,7 +637,7 @@ class DevicePDP11 extends Component {
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readUIPDR(addr)
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{
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var reg = (addr >> 1) & 7;
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return this.cpu.mmuPDR[3][reg];
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return this.cpu.regsPDR[3][reg];
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}
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/**
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@ -577,7 +650,7 @@ class DevicePDP11 extends Component {
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writeUIPDR(data, addr)
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{
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var reg = (addr >> 1) & 7;
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this.cpu.mmuPDR[3][reg] = data & 0xff0f;
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this.cpu.regsPDR[3][reg] = data & 0xff0f;
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}
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/**
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@ -590,7 +663,7 @@ class DevicePDP11 extends Component {
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readUDPDR(addr)
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{
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var reg = ((addr >> 1) & 7) + 8;
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return this.cpu.mmuPDR[3][reg];
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return this.cpu.regsPDR[3][reg];
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}
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/**
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@ -603,7 +676,7 @@ class DevicePDP11 extends Component {
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writeUDPDR(data, addr)
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{
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var reg = ((addr >> 1) & 7) + 8;
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this.cpu.mmuPDR[3][reg] = data & 0xff0f;
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this.cpu.regsPDR[3][reg] = data & 0xff0f;
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}
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/**
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@ -616,7 +689,7 @@ class DevicePDP11 extends Component {
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readUIPAR(addr)
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{
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var reg = (addr >> 1) & 7;
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return this.cpu.mmuPAR[3][reg];
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return this.cpu.regsPAR[3][reg];
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}
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/**
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@ -629,8 +702,8 @@ class DevicePDP11 extends Component {
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writeUIPAR(data, addr)
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{
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var reg = (addr >> 1) & 7;
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this.cpu.mmuPAR[3][reg] = data;
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this.cpu.mmuPDR[3][reg] &= 0xff0f;
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this.cpu.regsPAR[3][reg] = data;
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this.cpu.regsPDR[3][reg] &= 0xff0f;
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}
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@ -644,7 +717,7 @@ class DevicePDP11 extends Component {
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readUDPAR(addr)
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{
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var reg = ((addr >> 1) & 7) + 8;
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return this.cpu.mmuPAR[3][reg];
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return this.cpu.regsPAR[3][reg];
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}
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/**
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@ -657,8 +730,8 @@ class DevicePDP11 extends Component {
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writeUDPAR(data, addr)
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{
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var reg = ((addr >> 1) & 7) + 8;
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this.cpu.mmuPAR[3][reg] = data;
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this.cpu.mmuPDR[3][reg] &= 0xff0f;
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this.cpu.regsPAR[3][reg] = data;
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this.cpu.regsPDR[3][reg] &= 0xff0f;
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}
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/**
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