Some improvements for FOOTBALL, including support for the 386 LOADALL instruction
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Jeff Parsons
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27 changed files with 4431 additions and 3981 deletions
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@ -9,6 +9,7 @@ Intel 80286 CPU Information
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### 80286 Errata
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* [Early 80286 Errata of Interest](early_errata/#early-80286-errata-of-interest)
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* [ARPL Behavior](arpl/)
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* [Coprocessor Operand Beyond Segment Limit](b2_b3_info/#coprocessor-operand-partially-beyond-limit-of-erc-segment)
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* [Instructions Longer than 10 Bytes](extra_prefixes/)
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@ -16,9 +17,8 @@ Intel 80286 CPU Information
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* [Non-Restartable Protection Violations](b2_b3_info/#non-restartable-protection-violations)
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* [POPF Behavior](b2_b3_info/#popf-behavior)
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* [REP MOVS and REP INS Restartability](rep_restart/)
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* [Early 80286 Errata of Interest](early_errata/#early-80286-errata-of-interest)
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### 80286 Undocumented Opcodes
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### 80286 Undocumented Instructions
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* [LOADALL](loadall/)
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@ -1,12 +1,14 @@
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---
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layout: page
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title: "Intel 80286 CPU Documentation: ARPL"
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title: "Intel 80286 CPU Errata: ARPL"
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permalink: /pubs/pc/reference/intel/80286/arpl/
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---
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Intel 80286 CPU Documentation
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Intel 80286 CPU Errata: ARPL
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---
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[The following information is from an Intel document titled "80286 ARPL and Overlength Instructions, 15 October 1984"]
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### ARPL (63H)
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When the second operand of the ARPL instruction (as described in the iAPX286 Programmer's Reference Manual) is a null
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@ -15,5 +17,3 @@ but will be described in future revisions of the "iAPX286 Programmer's Reference
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This functionality of the ARPL is not believed not to be a problem, and there are no plans to change this functionality
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of the ARPL instruction.
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[This information is from an Intel document titled "80286 ARPL and Overlength Instructions, 15 October 1984"]
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@ -1,12 +1,14 @@
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---
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layout: page
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title: "Intel 80286 CPU Documentation: B-2/B-3 Steppings"
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title: "Intel 80286 CPU Errata: B-2/B-3 Steppings"
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permalink: /pubs/pc/reference/intel/80286/b2_b3_info/
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---
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Intel 80286 CPU Documentation
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Intel 80286 CPU Errata: B-2/B-3 Steppings
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---
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[The following information is from a 7-page Intel document titled "80286(B-2/B-3) Information Sheet, 21 November 1984"]
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### 80286 B-2/B-3 Steppings
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This applies to S-spec #40093 and to S-spec #54012 of the 80286, since they contain a (B-2/B-3) stepping of the 80286.
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@ -197,5 +199,3 @@ handled if the 80286 interrupts are always disabled before programming the inter
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is performed no unmasked interrupt is active. The interrupt handler for IR7 can read ISR7 of the 8259A to tell if this was a real
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interrupt on IR7. The ISR7 bit will be 0 if at the time the interrupt was acknowledged, no unmasked IR inputs of the 8259A were
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active ("phantom" interrupt).
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[This information is from a 7-page Intel document titled "80286(B-2/B-3) Information Sheet, 21 November 1984"]
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@ -1,12 +1,16 @@
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---
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layout: page
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title: "Intel 80286 CPU Documentation: Early Errata"
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title: "Intel 80286 CPU Errata: Early Problems"
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permalink: /pubs/pc/reference/intel/80286/early_errata/
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---
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Intel 80286 CPU Documentation
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Intel 80286 CPU Errata: Early Problems
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---
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[The following information is from an undated 15-page Intel document titled "Undocumented iAPX 286 Test Instruction".
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NOTE: The initial reference to LOADALL as "opcode 0F04H" and the subsequent references to the "0F05H opcode" are exactly
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as they appear in the original document. Whether or not they were mistakes is unknown.]
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### Exceptions from Undefined Opcodes and String Instructions
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The exception 13 handler will probably use a lookup table for the opcode byte of the instruction causing exception
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@ -101,5 +105,3 @@ steppings of the 80286 and are fixed in later steppings of the 80286.
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0-wait memory for the data values or be sure bit 0 of memory location 804H is zero. HOLD requests and processor
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extension data transfers should be inhibited while [LOADALL](../loadall/) is running. Later steppings of the 80286 will correctly
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load the MSW during [LOADALL](../loadall/) with HOLD and processor extension transfers.
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[This information is from an undated 15-page Intel document titled "Undocumented iAPX 286 Test Instruction"]
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@ -1,12 +1,14 @@
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---
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layout: page
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title: "Intel 80286 CPU Documentation: Extra Prefixes"
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title: "Intel 80286 CPU Errata: Extra Prefixes"
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permalink: /pubs/pc/reference/intel/80286/extra_prefixes/
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---
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Intel 80286 CPU Documentation
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Intel 80286 CPU Errata: Extra Prefixes
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---
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[The following information is from an Intel document titled "80286 ARPL and Overlength Instructions, 15 October 1984"]
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### Instructions Longer than 10 Bytes
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When the CPU detects an instruction that is illegal due to being greater than 10 bytes in length, it generates an
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@ -16,5 +18,3 @@ greater than ten bytes can occur is by using the assembler to intentionally plac
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There are no plans to change this functionality of the 80286 and future editions of the "iAPX286 Programmer's Reference
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Manual" and 80286 datasheet will accurately describe how 80286 reacts to instructions greater than 10 bytes in length.
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[This information is from an Intel document titled "80286 ARPL and Overlength Instructions, 15 October 1984"]
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@ -1,12 +1,14 @@
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---
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layout: page
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title: "Intel 80286 CPU Documentation: LOADALL"
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title: "Intel 80286 LOADALL Instruction"
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permalink: /pubs/pc/reference/intel/80286/loadall/
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---
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Intel 80286 CPU Documentation
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Intel 80286 LOADALL Instruction
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---
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[The following information is from an undated 15-page Intel document titled "Undocumented iAPX 286 Test Instruction"]
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### LOADALL (0F05H)
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The iAPX 286 microprocessor (part number 80286) has an undocumented instruction used by Intel test programs to
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@ -154,5 +156,3 @@ For proper protected mode operation, the following is required:
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4. The DPL fields of the ES and DS descriptors should be 3 to prevent their being zeroed by RET or IRET
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instructions.
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[This information is from an undated 15-page Intel document titled "Undocumented iAPX 286 Test Instruction"]
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@ -4,9 +4,11 @@ title: "Intel 80286 CPU Documentation: Real Mode"
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permalink: /pubs/pc/reference/intel/80286/real_mode/
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---
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Intel 80286 CPU Documentation
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Intel 80286 CPU Documentation: Real Mode
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---
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[The following information is from an undated 15-page Intel document titled "Undocumented iAPX 286 Test Instruction"]
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### Executing Real Mode Programs in Protected Mode
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An iAPX 86/88 program using real mode addressing can be executed in protected mode with full protection between
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@ -300,5 +302,3 @@ Interrupts must be handled specially. Interrupt handlers for both real mode and
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times. If an interrupt handler needs to access a data area, that data area must be addressable from both real and
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protected mode. The real mode interrupt table would be would be kept at location 000000H. The protected mode IDT could
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be anywhere. [LOADALL](../loadall/) will switch to the protected interrupt table.
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[This information is from an undated 15-page Intel document titled "Undocumented iAPX 286 Test Instruction"]
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@ -1,12 +1,14 @@
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---
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layout: page
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title: "Intel 80286 CPU Documentation: REP Restart"
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title: "Intel 80286 CPU Errata: REP Restart"
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permalink: /pubs/pc/reference/intel/80286/rep_restart/
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---
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Intel 80286 CPU Documentation
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Intel 80286 CPU Errata: REP Restart
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---
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[The following information is from an Intel document titled "80286 REP MOVS and REP INS Restartability, 15 October 1984"]
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### 80286 REP MOVS and REP INS Restartability
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The repeated string instructions on 80286 were made restartable after protection violations on the (B-2/B-3) and
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@ -46,5 +48,3 @@ The above three problems are being corrected in all future steppings of the 8028
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register will hold 0ffffH when the CPU detects a violation due to the conditions above. Note that even when REP MOVS and
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REP INS restartability is corrected, CX will correctly continue to be 0000H when these instructions complete without generating
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a protection violation.
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[This information is from an Intel document titled "80286 REP MOVS and REP INS Restartability, 15 October 1984"]
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