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The 8080 CPU goes through the Bus interfaces for all memory accesses now. The PCjs CPU maintained its own copy of Bus memory structures and interfaces, partly for improved performance but also because some CPUs can turn on address translation (ie, paging), making separate interfaces a necessity. However, PC8080 has much lower performance requirements and no address translation requirements, so we should revert to the original Bus interfaces.

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This commit is contained in:
Jeff Parsons 2016-05-02 12:54:55 -07:00
commit a56f1cfde1
6 changed files with 376 additions and 434 deletions
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81
modules/pc8080/lib/cpusim.js
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@ -92,14 +92,6 @@ function CPUSim(parmsCPU)
*/
this.cLiveRegs = 0;
/*
* We're just declaring aBusBlocks and associated Bus parameters here; they'll be initialized by initMemory()
* when the Bus is initialized.
*/
this.aBusBlocks = [];
this.nBusMask = 0;
this.nBlockShift = this.nBlockSize = this.nBlockLimit = this.nBlockTotal = this.nBlockMask = 0;
/*
* Array of halt handlers, if any (see addHaltCheck)
*/
@ -115,27 +107,6 @@ function CPUSim(parmsCPU)
Component.subclass(CPUSim, CPU);
/**
* initMemory(aBusBlocks, nBlockShift, nBusMask)
*
* Notification from Bus.initMemory(), giving us direct access to the entire memory space.
*
* @this {CPUSim}
* @param {Array} aBusBlocks
* @param {number} nBlockShift
* @param {number} nBusMask
*/
CPUSim.prototype.initMemory = function(aBusBlocks, nBlockShift, nBusMask)
{
this.aBusBlocks = aBusBlocks;
this.nBlockShift = nBlockShift;
this.nBlockSize = 1 << this.nBlockShift;
this.nBlockLimit = this.nBlockSize - 1;
this.nBlockTotal = aBusBlocks.length;
this.nBlockMask = this.nBlockTotal - 1;
this.nBusMask = nBusMask;
};
/**
* addHaltCheck(fn)
*
@ -149,36 +120,6 @@ CPUSim.prototype.addHaltCheck = function(fn)
this.afnHalt.push(fn);
};
/**
* addMemBreak(addr, fWrite)
*
* @this {CPUSim}
* @param {number} addr
* @param {boolean} fWrite is true for a memory write breakpoint, false for a memory read breakpoint
*/
CPUSim.prototype.addMemBreak = function(addr, fWrite)
{
if (DEBUGGER) {
var iBlock = addr >>> this.nBlockShift;
this.aBusBlocks[iBlock].addBreakpoint(addr & this.nBlockLimit, fWrite);
}
};
/**
* removeMemBreak(addr, fWrite)
*
* @this {CPUSim}
* @param {number} addr
* @param {boolean} fWrite is true for a memory write breakpoint, false for a memory read breakpoint
*/
CPUSim.prototype.removeMemBreak = function(addr, fWrite)
{
if (DEBUGGER) {
var iBlock = addr >>> this.nBlockShift;
this.aBusBlocks[iBlock].removeBreakpoint(addr & this.nBlockLimit, fWrite);
}
};
/**
* initProcessor()
*
@ -889,7 +830,7 @@ CPUSim.prototype.xorByte = function(src)
*/
CPUSim.prototype.getByte = function(addr)
{
return this.aBusBlocks[(addr & this.nBusMask) >>> this.nBlockShift].readByte(addr & this.nBlockLimit, addr);
return this.bus.getByte(addr);
};
/**
@ -901,14 +842,7 @@ CPUSim.prototype.getByte = function(addr)
*/
CPUSim.prototype.getWord = function(addr)
{
var off = addr & this.nBlockLimit;
var iBlock = (addr & this.nBusMask) >>> this.nBlockShift;
if (off < this.nBlockLimit) {
return this.aBusBlocks[iBlock].readShort(off, addr);
}
var w = this.aBusBlocks[iBlock].readByte(off, addr);
w |= this.aBusBlocks[(iBlock + 1) & this.nBlockMask].readByte(0, addr + 1) << 8;
return w;
return this.bus.getShort(addr);
};
/**
@ -920,7 +854,7 @@ CPUSim.prototype.getWord = function(addr)
*/
CPUSim.prototype.setByte = function(addr, b)
{
this.aBusBlocks[(addr & this.nBusMask) >>> this.nBlockShift].writeByte(addr & this.nBlockLimit, b & 0xff, addr);
this.bus.setByte(addr, b);
};
/**
@ -932,14 +866,7 @@ CPUSim.prototype.setByte = function(addr, b)
*/
CPUSim.prototype.setWord = function(addr, w)
{
var off = addr & this.nBlockLimit;
var iBlock = (addr & this.nBusMask) >>> this.nBlockShift;
if (off < this.nBlockLimit) {
this.aBusBlocks[iBlock].writeShort(off, w & 0xffff, addr);
return;
}
this.aBusBlocks[iBlock++].writeByte(off, w & 0xff, addr);
this.aBusBlocks[iBlock & this.nBlockMask].writeByte(0, (w >> 8) & 0xff, addr + 1);
this.bus.setShort(addr, w);
};
/**