Fixed MMR1/MMR2 updates, and synced boot monitor code with http://skn.noip.me/pdp11/boot.mac
This commit is contained in:
Jeff
Jeff Parsons
parent
7342ea254e
commit
9d67f243ef
9 changed files with 1401 additions and 809 deletions
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@ -254,8 +254,8 @@ CPUStatePDP11.prototype.resetMMU = function()
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this.mmuLastMode = 0;
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this.mmuMask = 0x3ffff;
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this.lastAI = 0; // last auto-incs and/or auto-decs; this gets propagated to MMR1
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this.lastPC = 0; // last PC at the time of getOpcode(); this get propagated to MMR2
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this.lastAI = 0; // last auto-incs and/or auto-decs; this is propagated to MMR1 as appropriate
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this.lastPC = 0; // last PC at the time of getOpcode(); this is propagated to MMR2 as appropriate
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this.resetTriggers();
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@ -327,6 +327,15 @@ CPUStatePDP11.prototype.setMMR0 = function(newMMR0)
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{
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newMMR0 &= 0xf381;
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if (this.regMMR0 != newMMR0) {
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/*
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* If updates to MMR1 and MMR2 are being shut off (ie, MMR0.ABORT bits are transitioning from clear to set),
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* then do one final sync with their real-time counterparts (lastAI and lastPC).
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*/
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if (!(this.regMMR0 & PDP11.MMR0.ABORT) && (newMMR0 & PDP11.MMR0.ABORT)) {
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this.assert(!(this.lastAI & ~0xffff));
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this.regMMR1 = this.lastAI & 0xffff;
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this.regMMR2 = this.lastPC;
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}
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this.regMMR0 = newMMR0;
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this.mmuLastMode = (newMMR0 >> 5) & 3;
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this.mmuLastPage = (newMMR0 >> 1) & 0xf;
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@ -352,7 +361,12 @@ CPUStatePDP11.prototype.setMMR0 = function(newMMR0)
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*/
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CPUStatePDP11.prototype.getMMR1 = function()
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{
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/*
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* If updates to MMR1 have not been shut off (ie, MMR0.ABORT bits are clear),
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* then we are always allowed to sync MMR1 with it real-time counterpart (lastAI).
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*/
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if (!(this.regMMR0 & PDP11.MMR0.ABORT)) {
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this.assert(!(this.lastAI & ~0xffff));
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this.regMMR1 = this.lastAI & 0xffff;
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}
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var result = this.regMMR1;
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@ -370,6 +384,10 @@ CPUStatePDP11.prototype.getMMR1 = function()
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*/
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CPUStatePDP11.prototype.getMMR2 = function()
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{
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/*
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* If updates to MMR2 have not been shut off (ie, MMR0.ABORT bits are clear),
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* then we are always allowed to sync MMR2 with it real-time counterpart (lastPC).
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*/
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if (!(this.regMMR0 & PDP11.MMR0.ABORT)) {
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this.regMMR2 = this.lastPC;
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}
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@ -559,7 +559,7 @@ if (DEBUGGER) {
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var fCompleted = false;
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if (!dbg.isBusy(true)) {
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dbg.setBusy(true);
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fCompleted = dbg.stepCPU(fRepeat? 1 : 0);
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fCompleted = dbg.stepCPU(fRepeat? 1 : 0, null);
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dbg.setBusy(false);
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}
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return fCompleted;
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@ -1317,7 +1317,7 @@ if (DEBUGGER) {
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*
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* @this {DebuggerPDP11}
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* @param {number} nCycles (0 for one instruction without checking breakpoints)
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* @param {boolean} [fRegs] is true to display registers after step (default is false)
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* @param {boolean|null} [fRegs] is true to display registers after step (default is false; use null for previous setting)
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* @param {boolean} [fUpdateDisplays] is false to disable Computer display updates (default is true)
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* @return {boolean}
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*/
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@ -1325,6 +1325,10 @@ if (DEBUGGER) {
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{
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if (!this.checkCPU()) return false;
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if (fRegs === null) {
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fRegs = (!this.sTraceCmdPrev || this.sTraceCmdPrev == "tr");
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}
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this.nCycles = 0;
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if (!nCycles) {
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@ -2773,12 +2777,12 @@ if (DEBUGGER) {
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{
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if (sAddr == '?') {
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this.println("breakpoint commands:");
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this.println("\tbp [a]\tset exec breakpoint at addr [a]");
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this.println("\tbr [a]\tset read breakpoint at addr [a]");
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this.println("\tbw [a]\tset write breakpoint at addr [a]");
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this.println("\tbc [a]\tclear breakpoint at addr [a]");
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this.println("\tbp [#]\tset exec breakpoint at addr #");
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this.println("\tbr [#]\tset read breakpoint at addr #");
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this.println("\tbw [#]\tset write breakpoint at addr #");
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this.println("\tbc [#]\tclear breakpoint at addr #");
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this.println("\tbl\tlist all breakpoints");
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this.println("\tbn [n]\tbreak after [n] instruction(s)");
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this.println("\tbn [#]\tbreak after # instruction(s)");
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return;
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}
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@ -3681,6 +3685,15 @@ if (DEBUGGER) {
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*/
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DebuggerPDP11.prototype.doTrace = function(sCmd, sCount)
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{
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if (sCount == '?') {
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this.println("trace commands:");
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this.println("\tt [#]\ttrace # instructions");
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this.println("\ttr [#]\ttrace # instructions with register updates");
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this.println("\ttc [#]\ttrace # cycles");
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this.println("note: bn [#] to break after # instructions is much faster");
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return;
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}
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var dbg = this;
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var fRegs = (sCmd != "t");
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var nCount = this.parseValue(sCount, null, true) || 1;
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@ -3689,6 +3702,7 @@ if (DEBUGGER) {
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nCycles = nCount;
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nCount = 1;
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}
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this.sTraceCmdPrev = sCmd;
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web.onCountRepeat(
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nCount,
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function onCountStep() {
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@ -364,11 +364,11 @@ var PDP11 = {
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* is enabled, the top 5 bits of an address select one of the 31 mapping registers, and the bottom 13 bits
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* are then added to the contents of the selected mapping register.
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*
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* ES6 ALERT: By using octal constants, this is the first place I'm dipping my toe into ECMAScript 6 waters.
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* If you're loading this raw source code into your browser, then by now (2016) you're almost certainly using
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* an ES6-aware browser. Everyone else should be using code compiled by Google's Closure Compiler, which
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* we configure to produce code that's backward-compatible with ES5 (for example, octal constants are
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* converted to decimal values).
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* ES6 ALERT: By using octal constants, I'm finally dipping my toe into ES6 (aka ECMAScript 2015) waters.
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* You'll even see a few binary constants below, too. If you're loading this raw source code into your browser,
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* then by now (2016) you're almost certainly using an ES6-aware browser. Production sites should be using code
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* compiled by Google's Closure Compiler, which we configure to produce code that's backward-compatible with ES5
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* (for example, all binary, octal, and hex constants are converted to decimal values).
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*
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* For more details: https://github.com/google/closure-compiler/wiki/ECMAScript6
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*/
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@ -498,22 +498,22 @@ var PDP11 = {
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UDPAR6: 0o177674, // User D Page Address Register 6
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UDPAR7: 0o177676, // User D Page Address Register 7
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R0SET0: 0o177700,
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R1SET0: 0o177701,
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R2SET0: 0o177702,
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R3SET0: 0o177703,
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R4SET0: 0o177704,
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R5SET0: 0o177705,
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R6KERNEL: 0o177706,
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R7KERNEL: 0o177707,
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R0SET1: 0o177710,
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R1SET1: 0o177711,
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R2SET1: 0o177712,
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R3SET1: 0o177713,
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R4SET1: 0o177714,
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R5SET1: 0o177715,
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R6SUPER: 0o177716,
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R6USER: 0o177717,
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R0SET0: 0o177700, //
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R1SET0: 0o177701, //
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R2SET0: 0o177702, //
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R3SET0: 0o177703, //
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R4SET0: 0o177704, //
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R5SET0: 0o177705, //
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R6KERNEL: 0o177706, //
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R7KERNEL: 0o177707, //
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R0SET1: 0o177710, //
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R1SET1: 0o177711, //
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R2SET1: 0o177712, //
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R3SET1: 0o177713, //
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R4SET1: 0o177714, //
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R5SET1: 0o177715, //
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R6SUPER: 0o177716, //
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R6USER: 0o177717, //
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/*
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* This next group of registers is largely ignored; all accesses are routed to regsControl[],
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@ -655,7 +655,7 @@ PanelPDP11.prototype.processContinue = function(value, index)
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var dbg = this.dbg;
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if (dbg && !dbg.isBusy(true)) {
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dbg.setBusy(true);
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dbg.stepCPU(0);
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dbg.stepCPU(0, null);
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dbg.setBusy(false);
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}
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else {
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