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MODEL_5170_REV3 boots without errors now

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However, performance will suffer until I can implement RTC interrupts;
also, there may be a problem exposed by the BIOS memory test following a soft reset
This commit is contained in:
Jeff Parsons 2014-10-14 16:07:46 -07:00 • committed by jeffpar
commit 997db9787b
15 changed files with 1557 additions and 1282 deletions
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6
my_modules/pcjs-client/lib/x86cpu.js
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@ -558,7 +558,9 @@ X86CPU.prototype.initProcessor = function()
if (this.model >= X86.MODEL_80186) {
/*
* TODO: I don't go out of my way to make 80186/80188 cycle times accurate, since no IBM PC models used
* those processors; beyond this point, my real priority is the 80286. But we may revisit the 80186 someday.
* those processors; beyond this point, my real priority is the 80286. But we may revisit the 80186 someday;
* instruction handlers that contain "hard-coded" 80286 cycle times include: opINSb, opINSw, opOUTSb,
* opOUTSw, opENTER, and opLEAVE.
*/
this.nShiftCountMask = 0x1f; // on newer processors, all shift counts are MOD 32
@ -582,7 +584,7 @@ X86CPU.prototype.initProcessor = function()
this.aOps[0xC0] = X86OpXX.opGRP2ab;
this.aOps[0xC1] = X86OpXX.opGRP2aw;
this.aOps[X86.OPCODE.ENTER] = X86OpXX.opENTER;
this.aOps[X86.OPCODE.ENTER] = X86OpXX.opLEAVE;
this.aOps[X86.OPCODE.LEAVE] = X86OpXX.opLEAVE;
this.aOps[0xF1] = X86OpXX.opINT1;
X86Grps.aOpGRP4b[0x07] = X86Grps.opGrpInvalid;
X86Grps.aOpGRP4w[0x07] = X86Grps.opGrpInvalid;