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MODEL_5170_REV3 boots without errors now

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However, performance will suffer until I can implement RTC interrupts;
also, there may be a problem exposed by the BIOS memory test following a soft reset
This commit is contained in:
Jeff Parsons 2014-10-14 16:07:46 -07:00 • committed by jeffpar
commit 997db9787b
15 changed files with 1557 additions and 1282 deletions
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2
devices/pc/bios/5170/1985-11-15.json
View file

@ -1023,4 +1023,4 @@
0,0,0,0,-822083584,4958953,216530944,-1259812051,1156107052,-773207253,53,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,14703594,791753200,942617905,-1979973579]
,"symbols":{"POST1_TEST01":{"o":80,"s":61440,"c":"TEST.01: 286 PROCESSOR TEST (REAL MODE)"},"POST1_TEST02":{"o":391,"s":61440,"c":"TEST.02: ROM CHECKSUM TEST"},"POST1_TEST03":{"o":419,"s":61440,"c":"TEST.03: VERIFY CMOS SHUTDOWN BYTE"},"POST1_TEST04":{"o":457,"s":61440,"c":"TEST.04: 8254 CHECK TIMER 1 (ALL BITS ON)"},"POST1_TEST05":{"o":503,"s":61440,"c":"TEST.05: 8254 CHECK TIMER 1 (ALL BITS OFF)"},"POST1_TEST06":{"o":541,"s":61440,"c":"TEST.06: 8237 DMA 0 INITIALIZATION"},"POST1_TEST07":{"o":607,"s":61440,"c":"TEST.07: 8237 DMA 1 INITIALIZATION"},"POST1_TEST08":{"o":724,"s":61440,"c":"TEST.08: DMA PAGE REGISTER TEST"},"POST1_TEST09":{"o":807,"s":61440,"c":"TEST.09: STORAGE REFRESH TEST"},"POST1_TEST10":{"o":829,"s":61440,"c":"TEST.10: 8042 INTERFACE TEST"},"POST1_TEST11":{"o":951,"s":61440,"c":"TEST.11: BASE 64K R/W STORAGE TEST"},"POST1_TEST11A":{"o":1494,"s":61440,"c":"TEST.11A: VERIFY GDT/IDT INSTRUCTIONS"},"POST1_TEST12":{"o":1726,"s":61440,"c":"TEST.12: VERIFY CMOS CHECKSUM"},"POST1_TEST13":{"o":1920,"s":61440,"c":"TEST.13: PROTECTED MODE TEST"},"POST1_TEST13A":{"o":2158,"s":61440,"c":"TEST.13A: MEMORY SIZE TEST (ABOVE 1024K)"},"POST1_TEST14":{"o":2713,"s":61440,"c":"TEST.14: INITIALIZE CRT CONTROLLER"},"POST1_TEST15":{"o":2829,"s":61440,"c":"TEST.15: VIDEO LINE TEST"},"POST1_TEST16":{"o":2845,"s":61440,"c":"TEST.16: CRT INTERFACE LINES TEST"},"MFG_BOOT":{"o":3109,"s":61440,"c":"MANUFACTURING BOOT TEST CODE ROUTINE"}}}
,"symbols":{"POST1_TEST01":{"o":80,"s":61440,"c":"TEST.01: 286 PROCESSOR TEST (REAL MODE)"},"POST1_TEST02":{"o":391,"s":61440,"c":"TEST.02: ROM CHECKSUM TEST"},"POST1_TEST03":{"o":419,"s":61440,"c":"TEST.03: VERIFY CMOS SHUTDOWN BYTE"},"POST1_TEST04":{"o":457,"s":61440,"c":"TEST.04: 8254 CHECK TIMER 1 (ALL BITS ON)"},"POST1_TEST05":{"o":503,"s":61440,"c":"TEST.05: 8254 CHECK TIMER 1 (ALL BITS OFF)"},"POST1_TEST06":{"o":541,"s":61440,"c":"TEST.06: 8237 DMA 0 INITIALIZATION"},"POST1_TEST07":{"o":607,"s":61440,"c":"TEST.07: 8237 DMA 1 INITIALIZATION"},"POST1_TEST08":{"o":724,"s":61440,"c":"TEST.08: DMA PAGE REGISTER TEST"},"POST1_TEST09":{"o":807,"s":61440,"c":"TEST.09: STORAGE REFRESH TEST"},"POST1_TEST10":{"o":829,"s":61440,"c":"TEST.10: 8042 INTERFACE TEST"},"POST1_TEST11":{"o":951,"s":61440,"c":"TEST.11: BASE 64K R/W STORAGE TEST"},"POST1_TEST11A":{"o":1494,"s":61440,"c":"TEST.11A: VERIFY GDT/IDT INSTRUCTIONS"},"POST1_TEST12":{"o":1726,"s":61440,"c":"TEST.12: VERIFY CMOS CHECKSUM"},"POST1_TEST13":{"o":1920,"s":61440,"c":"TEST.13: PROTECTED MODE TEST"},"POST1_TEST13A":{"o":2158,"s":61440,"c":"TEST.13A: MEMORY SIZE TEST (ABOVE 1024K)"},"POST1_TEST14":{"o":2713,"s":61440,"c":"TEST.14: INITIALIZE CRT CONTROLLER"},"POST1_TEST15":{"o":2829,"s":61440,"c":"TEST.15: VIDEO LINE TEST"},"POST1_TEST16":{"o":2845,"s":61440,"c":"TEST.16: CRT INTERFACE LINES TEST"},"MFG_BOOT":{"o":3109,"s":61440,"c":"MANUFACTURING BOOT TEST CODE ROUTINE"},"POST2":{"o":3220,"s":61440},"POST2_CHK_HFNUM":{"o":5372,"s":61440,"c":"CHECK FOR SECOND FIXED DISK PRESENT BUT NOT DEFINED"},"POST3":{"o":5749,"s":61440},"POST4":{"o":6469,"s":61440},"CMOS_READ":{"o":6469,"s":61440},"CMOS_WRITE":{"o":6495,"s":61440},"DDS":{"o":6521,"s":61440},"E_MSG":{"o":6529,"s":61440},"ERR_BEEP":{"o":6582,"s":61440},"BEEP":{"o":6644,"s":61440},"WAITF":{"o":6714,"s":61440,"c":"FIXED TIME WAIT (CX = COUNT OF 15.085737us INTERVALS TO WAIT)"},"CONFIG_BAD":{"o":6729,"s":61440},"XPC_BYTE":{"o":6749,"s":61440},"PRT_SEG":{"o":6772,"s":61440},"PROT_PRT":{"o":6793,"s":61440},"ROM_CHECKSUM":{"o":6837,"s":61440},"ROM_CHECK":{"o":6849,"s":61440},"KBD_RESET":{"o":6899,"s":61440},"BLINK_INT":{"o":6942,"s":61440},"SET_TOD":{"o":6956,"s":61440},"POST5":{"o":7230,"s":61440},"POST6":{"o":7867,"s":61440},"XMIT_8042":{"o":8167,"s":61440},"BOOT_STRAP_1":{"o":8232,"s":61440},"DISKETTE_IO_1":{"o":8521,"s":61440},"DISK_RESET":{"o":8656,"s":61440},"SEND_SPEC":{"o":9397,"s":61440},"SETUP_END":{"o":10462,"s":61440},"SETUP_DBL":{"o":10488,"s":61440,"c":"CHECK DOUBLE STEP"},"READ_ID":{"o":10588,"s":61440},"MOTOR_ON":{"o":10655,"s":61440},"NEC_OUTPUT":{"o":10877,"s":61440},"SEEK":{"o":10921,"s":61440},"RESULTS":{"o":11118,"s":61440},"WAIT_INT":{"o":11078,"s":61440},"DISK_INT_1":{"o":11230,"s":61440},"DSKETTE_SETUP":{"o":11253,"s":61440},"DISK_SETUP":{"o":11337,"s":61440},"DISK_IO":{"o":11762,"s":61440},"TST_RDY":{"o":12472,"s":61440,"c":"TEST HARD DISK READY (AH = 0x10)"},"NOT_BUSY":{"o":12892,"s":61440},"CHECK_ST":{"o":12971,"s":61440}}}

67
devices/pc/bios/5170/1985-11-15.map
View file

@ -17,3 +17,70 @@
F000:0B0D @ POST1_TEST15 ; TEST.15: VIDEO LINE TEST
F000:0B1D @ POST1_TEST16 ; TEST.16: CRT INTERFACE LINES TEST
F000:0C25 @ MFG_BOOT ; MANUFACTURING BOOT TEST CODE ROUTINE
;
; IBM's 11/15/85 ROM BIOS listing shows POST2 located at offset 0C96; it's actual location is 0C94.
;
0C94 +
F000:0000 @ POST2
F000:0868 @ POST2_CHK_HFNUM ; CHECK FOR SECOND FIXED DISK PRESENT BUT NOT DEFINED
;
; IBM's 11/15/85 ROM BIOS listing shows POST3 located at offset 1671; it's actual location is 1675.
;
1675 +
F000:0000 @ POST3
;
; IBM's 11/15/85 ROM BIOS listing shows POST4 located at offset 1941; it's actual location is 1945.
;
1945 +
F000:0000 @ POST4
F000:0000 @ CMOS_READ
F000:001A @ CMOS_WRITE
F000:0034 @ DDS
F000:003C @ E_MSG
F000:0071 @ ERR_BEEP
F000:00AF @ BEEP
F000:00F5 @ WAITF ; FIXED TIME WAIT (CX = COUNT OF 15.085737us INTERVALS TO WAIT)
F000:0104 @ CONFIG_BAD
F000:0118 @ XPC_BYTE
F000:012F @ PRT_SEG
F000:0144 @ PROT_PRT
F000:0170 @ ROM_CHECKSUM
F000:017C @ ROM_CHECK
F000:01AE @ KBD_RESET
F000:01D9 @ BLINK_INT
F000:01E7 @ SET_TOD
;
; IBM's 11/15/85 ROM BIOS listing shows POST5 located at offset 1C38; it's actual location is 1C3E.
;
1C3E +
F000:0000 @ POST5
;
; IBM's 11/15/85 ROM BIOS listing shows POST6 located at offset 1EB5; it's actual location is 1EBB.
;
1EBB +
F000:0000 @ POST6
F000:012C @ XMIT_8042
F000:016D @ BOOT_STRAP_1
;
; IBM's 11/15/85 ROM BIOS listing shows DISKETTE_IO_1 located at offset 2143; it's actual location is 2149.
;
20E9 +
F000:0060 @ DISKETTE_IO_1
F000:00E7 @ DISK_RESET
F000:03CC @ SEND_SPEC
F000:07F5 @ SETUP_END
F000:080F @ SETUP_DBL ; CHECK DOUBLE STEP
F000:0873 @ READ_ID
F000:08B6 @ MOTOR_ON
F000:0994 @ NEC_OUTPUT
F000:09C0 @ SEEK
F000:0A85 @ RESULTS
F000:0A5D @ WAIT_INT
F000:0AF5 @ DISK_INT_1
F000:0B0C @ DSKETTE_SETUP
F000:0B60 @ DISK_SETUP
F000:0D09 @ DISK_IO
2C69 +
F000:044F @ TST_RDY ; TEST HARD DISK READY (AH = 0x10)
F000:05F3 @ NOT_BUSY
F000:0642 @ CHECK_ST