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Updated PC8080 and PDPjs to support RAM images, eliminating the need for the old "writable ROM" kludge; RAM images can include their own load and exec addresses as part of the JSON file, but the RAM component can provide explicit overrides (if no load address is specified either way, the default load address is the starting RAM address)

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This commit is contained in:
Jeff Parsons 2016-10-17 11:01:32 -07:00 • committed by Jeff Parsons
commit 980c2ac5ab
64 changed files with 1479 additions and 1154 deletions
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18
modules/pdp11/lib/cpustate.js
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@ -50,7 +50,7 @@ if (NODE) {
* The CPUStatePDP11 class uses the following (parmsCPU) properties:
*
* model: a number (eg, 1170) that should match one of the PDP11.MODEL_* values
* resetAddr: reset address (default is 0)
* addrReset: reset address (default is 0)
*
* This extends the CPU class and passes any remaining parmsCPU properties to the CPU class
* constructor, along with a default speed (cycles per second) based on the specified (or default)
@ -63,7 +63,7 @@ if (NODE) {
function CPUStatePDP11(parmsCPU)
{
this.model = +parmsCPU['model'] || PDP11.MODEL_1170;
this.resetAddr = parmsCPU['resetAddr'] || 0;
this.addrReset = parmsCPU['addrReset'] || 0;
var nCyclesDefault = 0;
switch(this.model) {
@ -175,7 +175,7 @@ CPUStatePDP11.prototype.initRegs = function()
this.flagN = 0x8000; // PSW N bit
this.regPSW = 0x000f; // PSW other bits (TODO: What's the point of setting the flag bits here, too?)
this.regsGen = [ // General R0 - R7
0, 0, 0, 0, 0, 0, 0, this.resetAddr
0, 0, 0, 0, 0, 0, 0, this.addrReset
];
this.regsAlt = [ // Alternate R0 - R5
0, 0, 0, 0, 0, 0
@ -359,6 +359,18 @@ CPUStatePDP11.prototype.setMMR3 = function(newMMR3)
}
};
/**
* setReset(addr)
*
* @this {CPUStatePDP11}
* @param {number} addr
*/
CPUStatePDP11.prototype.setReset = function(addr)
{
this.addrReset = addr;
this.setPC(addr);
};
/**
* getChecksum()
*