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Across-the-board debugger fix

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This commit is contained in:
Jeff 2016-09-27 09:34:56 -07:00 • committed by Jeff Parsons
commit 9727a2d4df
3 changed files with 266 additions and 274 deletions
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139
modules/pc8080/lib/debugger.js
View file

@ -3669,81 +3669,74 @@ if (DEBUGGER) {
return; return;
} }
var fValid = false;
var w = this.parseExpression(sValue); var w = this.parseExpression(sValue);
if (w === undefined) return;
if (w !== undefined) { var sRegMatch = sReg.toUpperCase();
fValid = true; switch (sRegMatch) {
var sRegMatch = sReg.toUpperCase(); case "A":
switch (sRegMatch) { cpu.regA = w & 0xff;
case "A": break;
cpu.regA = w & 0xff; case "B":
break; cpu.regB = w & 0xff;
case "B": break;
cpu.regB = w & 0xff; case "BC":
break; cpu.regB = ((w >> 8) & 0xff);
case "BC": /* falls through */
cpu.regB = ((w >> 8) & 0xff); case "C":
/* falls through */ cpu.regC = w & 0xff;
case "C": break;
cpu.regC = w & 0xff; case "D":
break; cpu.regD = w & 0xff;
case "D": break;
cpu.regD = w & 0xff; case "DE":
break; cpu.regD = ((w >> 8) & 0xff);
case "DE": /* falls through */
cpu.regD = ((w >> 8) & 0xff); case "E":
/* falls through */ cpu.regE = w & 0xff;
case "E": break;
cpu.regE = w & 0xff; case "H":
break; cpu.regH = w & 0xff;
case "H": break;
cpu.regH = w & 0xff; case "HL":
break; cpu.regH = ((w >> 8) & 0xff);
case "HL": /* falls through */
cpu.regH = ((w >> 8) & 0xff); case "L":
/* falls through */ cpu.regL = w & 0xff;
case "L": break;
cpu.regL = w & 0xff; case "SP":
break; cpu.setSP(w);
case "SP": break;
cpu.setSP(w); case "PC":
break; cpu.setPC(w);
case "PC": this.dbgAddrNextCode = this.newAddr(cpu.getPC());
cpu.setPC(w); break;
this.dbgAddrNextCode = this.newAddr(cpu.getPC()); case "PS":
break; cpu.setPS(w);
case "PS": break;
cpu.setPS(w); case "PSW":
break; cpu.setPSW(w);
case "PSW": break;
cpu.setPSW(w); case "CF":
break; if (w) cpu.setCF(); else cpu.clearCF();
case "CF": break;
if (w) cpu.setCF(); else cpu.clearCF(); case "PF":
break; if (w) cpu.setPF(); else cpu.clearPF();
case "PF": break;
if (w) cpu.setPF(); else cpu.clearPF(); case "AF":
break; if (w) cpu.setAF(); else cpu.clearAF();
case "AF": break;
if (w) cpu.setAF(); else cpu.clearAF(); case "ZF":
break; if (w) cpu.setZF(); else cpu.clearZF();
case "ZF": break;
if (w) cpu.setZF(); else cpu.clearZF(); case "SF":
break; if (w) cpu.setSF(); else cpu.clearSF();
case "SF": break;
if (w) cpu.setSF(); else cpu.clearSF(); case "IF":
break; if (w) cpu.setIF(); else cpu.clearIF();
case "IF": break;
if (w) cpu.setIF(); else cpu.clearIF(); default:
break; this.println("unknown register: " + sReg);
default:
this.println("unknown register: " + sReg);
return;
}
}
if (!fValid) {
this.println("invalid value: " + sValue);
return; return;
} }
cpu.updateCPU(); cpu.updateCPU();

400
modules/pcx86/lib/debugger.js
View file

@ -6784,214 +6784,214 @@ if (DEBUGGER) {
this.println("missing value for " + asArgs[1]); this.println("missing value for " + asArgs[1]);
return; return;
} }
var fValid = false;
var w = this.parseExpression(sValue); var w = this.parseExpression(sValue);
if (w !== undefined) { if (w === undefined) return;
fValid = true;
var sRegMatch = sReg.toUpperCase(); var fValid = true;
if (sRegMatch.charAt(0) == 'E' && this.cchReg <= 4) { var sRegMatch = sReg.toUpperCase();
sRegMatch = null; if (sRegMatch.charAt(0) == 'E' && this.cchReg <= 4) {
} sRegMatch = null;
switch (sRegMatch) { }
case "AL": switch (sRegMatch) {
this.cpu.regEAX = (this.cpu.regEAX & ~0xff) | (w & 0xff); case "AL":
break; this.cpu.regEAX = (this.cpu.regEAX & ~0xff) | (w & 0xff);
case "AH": break;
this.cpu.regEAX = (this.cpu.regEAX & ~0xff00) | ((w << 8) & 0xff); case "AH":
break; this.cpu.regEAX = (this.cpu.regEAX & ~0xff00) | ((w << 8) & 0xff);
case "AX": break;
this.cpu.regEAX = (this.cpu.regEAX & ~0xffff) | (w & 0xffff); case "AX":
break; this.cpu.regEAX = (this.cpu.regEAX & ~0xffff) | (w & 0xffff);
case "BL": break;
this.cpu.regEBX = (this.cpu.regEBX & ~0xff) | (w & 0xff); case "BL":
break; this.cpu.regEBX = (this.cpu.regEBX & ~0xff) | (w & 0xff);
case "BH": break;
this.cpu.regEBX = (this.cpu.regEBX & ~0xff00) | ((w << 8) & 0xff); case "BH":
break; this.cpu.regEBX = (this.cpu.regEBX & ~0xff00) | ((w << 8) & 0xff);
case "BX": break;
this.cpu.regEBX = (this.cpu.regEBX & ~0xffff) | (w & 0xffff); case "BX":
break; this.cpu.regEBX = (this.cpu.regEBX & ~0xffff) | (w & 0xffff);
case "CL": break;
this.cpu.regECX = (this.cpu.regECX & ~0xff) | (w & 0xff); case "CL":
break; this.cpu.regECX = (this.cpu.regECX & ~0xff) | (w & 0xff);
case "CH": break;
this.cpu.regECX = (this.cpu.regECX & ~0xff00) | ((w << 8) & 0xff); case "CH":
break; this.cpu.regECX = (this.cpu.regECX & ~0xff00) | ((w << 8) & 0xff);
case "CX": break;
this.cpu.regECX = (this.cpu.regECX & ~0xffff) | (w & 0xffff); case "CX":
break; this.cpu.regECX = (this.cpu.regECX & ~0xffff) | (w & 0xffff);
case "DL": break;
this.cpu.regEDX = (this.cpu.regEDX & ~0xff) | (w & 0xff); case "DL":
break; this.cpu.regEDX = (this.cpu.regEDX & ~0xff) | (w & 0xff);
case "DH": break;
this.cpu.regEDX = (this.cpu.regEDX & ~0xff00) | ((w << 8) & 0xff); case "DH":
break; this.cpu.regEDX = (this.cpu.regEDX & ~0xff00) | ((w << 8) & 0xff);
case "DX": break;
this.cpu.regEDX = (this.cpu.regEDX & ~0xffff) | (w & 0xffff); case "DX":
break; this.cpu.regEDX = (this.cpu.regEDX & ~0xffff) | (w & 0xffff);
case "SP": break;
this.cpu.setSP((this.cpu.getSP() & ~0xffff) | (w & 0xffff)); case "SP":
break; this.cpu.setSP((this.cpu.getSP() & ~0xffff) | (w & 0xffff));
case "BP": break;
this.cpu.regEBP = (this.cpu.regEBP & ~0xffff) | (w & 0xffff); case "BP":
break; this.cpu.regEBP = (this.cpu.regEBP & ~0xffff) | (w & 0xffff);
case "SI": break;
this.cpu.regESI = (this.cpu.regESI & ~0xffff) | (w & 0xffff); case "SI":
break; this.cpu.regESI = (this.cpu.regESI & ~0xffff) | (w & 0xffff);
case "DI": break;
this.cpu.regEDI = (this.cpu.regEDI & ~0xffff) | (w & 0xffff); case "DI":
break; this.cpu.regEDI = (this.cpu.regEDI & ~0xffff) | (w & 0xffff);
/* break;
* DANGER: For any of the segment loads below, by going through the normal CPU /*
* segment load procedure, you run the risk of generating a fault in the machine * DANGER: For any of the segment loads below, by going through the normal CPU
* if you're not careful. So, um, be careful. * segment load procedure, you run the risk of generating a fault in the machine
*/ * if you're not careful. So, um, be careful.
case "DS": */
this.cpu.setDS(w); case "DS":
break; this.cpu.setDS(w);
case "ES": break;
this.cpu.setES(w); case "ES":
break; this.cpu.setES(w);
case "SS": break;
this.cpu.setSS(w); case "SS":
break; this.cpu.setSS(w);
case "CS": break;
// fInstruction = true; case "CS":
this.cpu.setCS(w); // fInstruction = true;
this.dbgAddrNextCode = this.newAddr(this.cpu.getIP(), this.cpu.getCS()); this.cpu.setCS(w);
break; this.dbgAddrNextCode = this.newAddr(this.cpu.getIP(), this.cpu.getCS());
case "IP": break;
case "EIP": case "IP":
// fInstruction = true; case "EIP":
this.cpu.setIP(w); // fInstruction = true;
this.dbgAddrNextCode = this.newAddr(this.cpu.getIP(), this.cpu.getCS()); this.cpu.setIP(w);
break; this.dbgAddrNextCode = this.newAddr(this.cpu.getIP(), this.cpu.getCS());
/* break;
* I used to alias "PC" (Program Counter) to "IP" (Instruction Pointer), because in PC-DOS 1.00 /*
* through 2.10, DEBUG.COM did the same thing. Then I discovered that, starting with PC-DOS 3.00, * I used to alias "PC" (Program Counter) to "IP" (Instruction Pointer), because in PC-DOS 1.00
* DEBUG.COM changed "PC" to refer to the 16-bit flags register (Program or Processor Control?) * through 2.10, DEBUG.COM did the same thing. Then I discovered that, starting with PC-DOS 3.00,
* I've elected to go for PC-DOS 3.00+ compatibility, since that will be more widely known. * DEBUG.COM changed "PC" to refer to the 16-bit flags register (Program or Processor Control?)
* * I've elected to go for PC-DOS 3.00+ compatibility, since that will be more widely known.
* PCx86 prefers "PS" (Processor Status) for accessing the FLAGS register in its 16-bit (or 32-bit) *
* entirety. Individual flag bits can also be accessed as 1-bit registers, using the names shown * PCx86 prefers "PS" (Processor Status) for accessing the FLAGS register in its 16-bit (or 32-bit)
* below ("C", "P", "A", "Z", etc.) * entirety. Individual flag bits can also be accessed as 1-bit registers, using the names shown
*/ * below ("C", "P", "A", "Z", etc.)
case "PC": */
case "PS": case "PC":
this.cpu.setPS(w); case "PS":
break; this.cpu.setPS(w);
case 'C': break;
if (w) this.cpu.setCF(); else this.cpu.clearCF(); case 'C':
break; if (w) this.cpu.setCF(); else this.cpu.clearCF();
case 'P': break;
if (w) this.cpu.setPF(); else this.cpu.clearPF(); case 'P':
break; if (w) this.cpu.setPF(); else this.cpu.clearPF();
case 'A': break;
if (w) this.cpu.setAF(); else this.cpu.clearAF(); case 'A':
break; if (w) this.cpu.setAF(); else this.cpu.clearAF();
case 'Z': break;
if (w) this.cpu.setZF(); else this.cpu.clearZF(); case 'Z':
break; if (w) this.cpu.setZF(); else this.cpu.clearZF();
case 'S': break;
if (w) this.cpu.setSF(); else this.cpu.clearSF(); case 'S':
break; if (w) this.cpu.setSF(); else this.cpu.clearSF();
case 'I': break;
if (w) this.cpu.setIF(); else this.cpu.clearIF(); case 'I':
break; if (w) this.cpu.setIF(); else this.cpu.clearIF();
case 'D': break;
if (w) this.cpu.setDF(); else this.cpu.clearDF(); case 'D':
break; if (w) this.cpu.setDF(); else this.cpu.clearDF();
case 'V': break;
if (w) this.cpu.setOF(); else this.cpu.clearOF(); case 'V':
break; if (w) this.cpu.setOF(); else this.cpu.clearOF();
default: break;
var fUnknown = true; default:
if (this.cpu.model >= X86.MODEL_80286) { var fUnknown = true;
fUnknown = false; if (this.cpu.model >= X86.MODEL_80286) {
switch(sRegMatch){ fUnknown = false;
case "MS": switch(sRegMatch){
this.cpu.setMSW(w); case "MS":
break; this.cpu.setMSW(w);
case "TR": break;
case "TR":
/*
* DANGER: Like any of the segment loads above, by going through the normal CPU
* segment load procedure, you run the risk of generating a fault in the machine
* if you're not careful. So, um, be careful.
*/
if (this.cpu.segTSS.load(w) === X86.ADDR_INVALID) {
fValid = false;
}
break;
/*
* TODO: Add support for GDTR (addr and limit), IDTR (addr and limit), and perhaps
* even the ability to edit descriptor information associated with each segment register.
*/
default:
fUnknown = true;
if (I386 && this.cpu.model >= X86.MODEL_80386) {
fUnknown = false;
switch(sRegMatch){
case "EAX":
this.cpu.regEAX = w;
break;
case "EBX":
this.cpu.regEBX = w;
break;
case "ECX":
this.cpu.regECX = w;
break;
case "EDX":
this.cpu.regEDX = w;
break;
case "ESP":
this.cpu.setSP(w);
break;
case "EBP":
this.cpu.regEBP = w;
break;
case "ESI":
this.cpu.regESI = w;
break;
case "EDI":
this.cpu.regEDI = w;
break;
/* /*
* DANGER: Like any of the segment loads above, by going through the normal CPU * DANGER: For any of the segment loads below, by going through the normal CPU
* segment load procedure, you run the risk of generating a fault in the machine * segment load procedure, you run the risk of generating a fault in the machine
* if you're not careful. So, um, be careful. * if you're not careful. So, um, be careful.
*/ */
if (this.cpu.segTSS.load(w) === X86.ADDR_INVALID) { case "FS":
fValid = false; this.cpu.setFS(w);
break;
case "GS":
this.cpu.setGS(w);
break;
case "CR0":
this.cpu.regCR0 = w;
X86.helpLoadCR0.call(this.cpu, w);
break;
case "CR2":
this.cpu.regCR2 = w;
break;
case "CR3":
this.cpu.regCR3 = w;
X86.helpLoadCR3.call(this.cpu, w);
break;
/*
* TODO: Add support for DR0-DR7 and TR6-TR7.
*/
default:
fUnknown = true;
break;
} }
break;
/*
* TODO: Add support for GDTR (addr and limit), IDTR (addr and limit), and perhaps
* even the ability to edit descriptor information associated with each segment register.
*/
default:
fUnknown = true;
if (I386 && this.cpu.model >= X86.MODEL_80386) {
fUnknown = false;
switch(sRegMatch){
case "EAX":
this.cpu.regEAX = w;
break;
case "EBX":
this.cpu.regEBX = w;
break;
case "ECX":
this.cpu.regECX = w;
break;
case "EDX":
this.cpu.regEDX = w;
break;
case "ESP":
this.cpu.setSP(w);
break;
case "EBP":
this.cpu.regEBP = w;
break;
case "ESI":
this.cpu.regESI = w;
break;
case "EDI":
this.cpu.regEDI = w;
break;
/*
* DANGER: For any of the segment loads below, by going through the normal CPU
* segment load procedure, you run the risk of generating a fault in the machine
* if you're not careful. So, um, be careful.
*/
case "FS":
this.cpu.setFS(w);
break;
case "GS":
this.cpu.setGS(w);
break;
case "CR0":
this.cpu.regCR0 = w;
X86.helpLoadCR0.call(this.cpu, w);
break;
case "CR2":
this.cpu.regCR2 = w;
break;
case "CR3":
this.cpu.regCR3 = w;
X86.helpLoadCR3.call(this.cpu, w);
break;
/*
* TODO: Add support for DR0-DR7 and TR6-TR7.
*/
default:
fUnknown = true;
break;
}
}
break;
} }
break;
} }
if (fUnknown) { }
this.println("unknown register: " + sReg); if (fUnknown) {
return; this.println("unknown register: " + sReg);
} return;
} }
} }
if (!fValid) { if (!fValid) {

1
modules/pdp11/lib/debugger.js
View file

@ -3177,7 +3177,6 @@ if (DEBUGGER) {
this.println("unknown register: " + sReg); this.println("unknown register: " + sReg);
return; return;
} }
cpu.updateCPU(); cpu.updateCPU();
this.println("updated registers:"); this.println("updated registers:");
} }