Across-the-board debugger fix
This commit is contained in:
Jeff
Jeff Parsons
parent
e322c5f912
commit
9727a2d4df
3 changed files with 266 additions and 274 deletions
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@ -6784,214 +6784,214 @@ if (DEBUGGER) {
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this.println("missing value for " + asArgs[1]);
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return;
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}
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var fValid = false;
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var w = this.parseExpression(sValue);
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if (w !== undefined) {
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fValid = true;
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var sRegMatch = sReg.toUpperCase();
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if (sRegMatch.charAt(0) == 'E' && this.cchReg <= 4) {
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sRegMatch = null;
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}
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switch (sRegMatch) {
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case "AL":
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this.cpu.regEAX = (this.cpu.regEAX & ~0xff) | (w & 0xff);
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break;
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case "AH":
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this.cpu.regEAX = (this.cpu.regEAX & ~0xff00) | ((w << 8) & 0xff);
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break;
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case "AX":
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this.cpu.regEAX = (this.cpu.regEAX & ~0xffff) | (w & 0xffff);
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break;
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case "BL":
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this.cpu.regEBX = (this.cpu.regEBX & ~0xff) | (w & 0xff);
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break;
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case "BH":
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this.cpu.regEBX = (this.cpu.regEBX & ~0xff00) | ((w << 8) & 0xff);
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break;
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case "BX":
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this.cpu.regEBX = (this.cpu.regEBX & ~0xffff) | (w & 0xffff);
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break;
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case "CL":
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this.cpu.regECX = (this.cpu.regECX & ~0xff) | (w & 0xff);
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break;
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case "CH":
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this.cpu.regECX = (this.cpu.regECX & ~0xff00) | ((w << 8) & 0xff);
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break;
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case "CX":
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this.cpu.regECX = (this.cpu.regECX & ~0xffff) | (w & 0xffff);
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break;
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case "DL":
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this.cpu.regEDX = (this.cpu.regEDX & ~0xff) | (w & 0xff);
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break;
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case "DH":
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this.cpu.regEDX = (this.cpu.regEDX & ~0xff00) | ((w << 8) & 0xff);
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break;
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case "DX":
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this.cpu.regEDX = (this.cpu.regEDX & ~0xffff) | (w & 0xffff);
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break;
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case "SP":
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this.cpu.setSP((this.cpu.getSP() & ~0xffff) | (w & 0xffff));
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break;
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case "BP":
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this.cpu.regEBP = (this.cpu.regEBP & ~0xffff) | (w & 0xffff);
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break;
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case "SI":
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this.cpu.regESI = (this.cpu.regESI & ~0xffff) | (w & 0xffff);
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break;
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case "DI":
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this.cpu.regEDI = (this.cpu.regEDI & ~0xffff) | (w & 0xffff);
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break;
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/*
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* DANGER: For any of the segment loads below, by going through the normal CPU
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* segment load procedure, you run the risk of generating a fault in the machine
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* if you're not careful. So, um, be careful.
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*/
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case "DS":
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this.cpu.setDS(w);
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break;
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case "ES":
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this.cpu.setES(w);
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break;
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case "SS":
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this.cpu.setSS(w);
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break;
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case "CS":
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// fInstruction = true;
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this.cpu.setCS(w);
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this.dbgAddrNextCode = this.newAddr(this.cpu.getIP(), this.cpu.getCS());
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break;
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case "IP":
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case "EIP":
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// fInstruction = true;
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this.cpu.setIP(w);
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this.dbgAddrNextCode = this.newAddr(this.cpu.getIP(), this.cpu.getCS());
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break;
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/*
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* I used to alias "PC" (Program Counter) to "IP" (Instruction Pointer), because in PC-DOS 1.00
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* through 2.10, DEBUG.COM did the same thing. Then I discovered that, starting with PC-DOS 3.00,
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* DEBUG.COM changed "PC" to refer to the 16-bit flags register (Program or Processor Control?)
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* I've elected to go for PC-DOS 3.00+ compatibility, since that will be more widely known.
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*
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* PCx86 prefers "PS" (Processor Status) for accessing the FLAGS register in its 16-bit (or 32-bit)
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* entirety. Individual flag bits can also be accessed as 1-bit registers, using the names shown
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* below ("C", "P", "A", "Z", etc.)
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*/
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case "PC":
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case "PS":
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this.cpu.setPS(w);
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break;
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case 'C':
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if (w) this.cpu.setCF(); else this.cpu.clearCF();
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break;
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case 'P':
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if (w) this.cpu.setPF(); else this.cpu.clearPF();
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break;
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case 'A':
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if (w) this.cpu.setAF(); else this.cpu.clearAF();
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break;
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case 'Z':
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if (w) this.cpu.setZF(); else this.cpu.clearZF();
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break;
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case 'S':
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if (w) this.cpu.setSF(); else this.cpu.clearSF();
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break;
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case 'I':
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if (w) this.cpu.setIF(); else this.cpu.clearIF();
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break;
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case 'D':
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if (w) this.cpu.setDF(); else this.cpu.clearDF();
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break;
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case 'V':
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if (w) this.cpu.setOF(); else this.cpu.clearOF();
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break;
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default:
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var fUnknown = true;
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if (this.cpu.model >= X86.MODEL_80286) {
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fUnknown = false;
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switch(sRegMatch){
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case "MS":
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this.cpu.setMSW(w);
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break;
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case "TR":
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if (w === undefined) return;
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var fValid = true;
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var sRegMatch = sReg.toUpperCase();
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if (sRegMatch.charAt(0) == 'E' && this.cchReg <= 4) {
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sRegMatch = null;
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}
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switch (sRegMatch) {
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case "AL":
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this.cpu.regEAX = (this.cpu.regEAX & ~0xff) | (w & 0xff);
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break;
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case "AH":
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this.cpu.regEAX = (this.cpu.regEAX & ~0xff00) | ((w << 8) & 0xff);
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break;
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case "AX":
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this.cpu.regEAX = (this.cpu.regEAX & ~0xffff) | (w & 0xffff);
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break;
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case "BL":
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this.cpu.regEBX = (this.cpu.regEBX & ~0xff) | (w & 0xff);
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break;
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case "BH":
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this.cpu.regEBX = (this.cpu.regEBX & ~0xff00) | ((w << 8) & 0xff);
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break;
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case "BX":
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this.cpu.regEBX = (this.cpu.regEBX & ~0xffff) | (w & 0xffff);
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break;
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case "CL":
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this.cpu.regECX = (this.cpu.regECX & ~0xff) | (w & 0xff);
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break;
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case "CH":
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this.cpu.regECX = (this.cpu.regECX & ~0xff00) | ((w << 8) & 0xff);
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break;
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case "CX":
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this.cpu.regECX = (this.cpu.regECX & ~0xffff) | (w & 0xffff);
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break;
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case "DL":
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this.cpu.regEDX = (this.cpu.regEDX & ~0xff) | (w & 0xff);
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break;
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case "DH":
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this.cpu.regEDX = (this.cpu.regEDX & ~0xff00) | ((w << 8) & 0xff);
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break;
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case "DX":
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this.cpu.regEDX = (this.cpu.regEDX & ~0xffff) | (w & 0xffff);
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break;
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case "SP":
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this.cpu.setSP((this.cpu.getSP() & ~0xffff) | (w & 0xffff));
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break;
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case "BP":
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this.cpu.regEBP = (this.cpu.regEBP & ~0xffff) | (w & 0xffff);
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break;
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case "SI":
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this.cpu.regESI = (this.cpu.regESI & ~0xffff) | (w & 0xffff);
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break;
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case "DI":
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this.cpu.regEDI = (this.cpu.regEDI & ~0xffff) | (w & 0xffff);
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break;
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/*
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* DANGER: For any of the segment loads below, by going through the normal CPU
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* segment load procedure, you run the risk of generating a fault in the machine
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* if you're not careful. So, um, be careful.
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*/
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case "DS":
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this.cpu.setDS(w);
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break;
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case "ES":
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this.cpu.setES(w);
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break;
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case "SS":
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this.cpu.setSS(w);
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break;
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case "CS":
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// fInstruction = true;
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this.cpu.setCS(w);
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this.dbgAddrNextCode = this.newAddr(this.cpu.getIP(), this.cpu.getCS());
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break;
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case "IP":
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case "EIP":
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// fInstruction = true;
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this.cpu.setIP(w);
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this.dbgAddrNextCode = this.newAddr(this.cpu.getIP(), this.cpu.getCS());
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break;
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/*
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* I used to alias "PC" (Program Counter) to "IP" (Instruction Pointer), because in PC-DOS 1.00
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* through 2.10, DEBUG.COM did the same thing. Then I discovered that, starting with PC-DOS 3.00,
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* DEBUG.COM changed "PC" to refer to the 16-bit flags register (Program or Processor Control?)
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* I've elected to go for PC-DOS 3.00+ compatibility, since that will be more widely known.
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*
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* PCx86 prefers "PS" (Processor Status) for accessing the FLAGS register in its 16-bit (or 32-bit)
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* entirety. Individual flag bits can also be accessed as 1-bit registers, using the names shown
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* below ("C", "P", "A", "Z", etc.)
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*/
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case "PC":
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case "PS":
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this.cpu.setPS(w);
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break;
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case 'C':
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if (w) this.cpu.setCF(); else this.cpu.clearCF();
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break;
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case 'P':
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if (w) this.cpu.setPF(); else this.cpu.clearPF();
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break;
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case 'A':
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if (w) this.cpu.setAF(); else this.cpu.clearAF();
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break;
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case 'Z':
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if (w) this.cpu.setZF(); else this.cpu.clearZF();
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break;
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case 'S':
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if (w) this.cpu.setSF(); else this.cpu.clearSF();
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break;
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case 'I':
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if (w) this.cpu.setIF(); else this.cpu.clearIF();
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break;
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case 'D':
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if (w) this.cpu.setDF(); else this.cpu.clearDF();
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break;
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case 'V':
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if (w) this.cpu.setOF(); else this.cpu.clearOF();
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break;
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default:
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var fUnknown = true;
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if (this.cpu.model >= X86.MODEL_80286) {
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fUnknown = false;
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switch(sRegMatch){
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case "MS":
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this.cpu.setMSW(w);
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break;
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case "TR":
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/*
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* DANGER: Like any of the segment loads above, by going through the normal CPU
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* segment load procedure, you run the risk of generating a fault in the machine
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* if you're not careful. So, um, be careful.
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*/
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if (this.cpu.segTSS.load(w) === X86.ADDR_INVALID) {
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fValid = false;
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}
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break;
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/*
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* TODO: Add support for GDTR (addr and limit), IDTR (addr and limit), and perhaps
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* even the ability to edit descriptor information associated with each segment register.
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*/
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default:
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fUnknown = true;
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if (I386 && this.cpu.model >= X86.MODEL_80386) {
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fUnknown = false;
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switch(sRegMatch){
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case "EAX":
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this.cpu.regEAX = w;
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break;
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case "EBX":
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this.cpu.regEBX = w;
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break;
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case "ECX":
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this.cpu.regECX = w;
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break;
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case "EDX":
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this.cpu.regEDX = w;
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break;
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case "ESP":
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this.cpu.setSP(w);
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break;
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case "EBP":
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this.cpu.regEBP = w;
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break;
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case "ESI":
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this.cpu.regESI = w;
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break;
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case "EDI":
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this.cpu.regEDI = w;
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break;
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/*
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* DANGER: Like any of the segment loads above, by going through the normal CPU
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* DANGER: For any of the segment loads below, by going through the normal CPU
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* segment load procedure, you run the risk of generating a fault in the machine
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* if you're not careful. So, um, be careful.
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*/
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if (this.cpu.segTSS.load(w) === X86.ADDR_INVALID) {
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fValid = false;
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case "FS":
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this.cpu.setFS(w);
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break;
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case "GS":
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this.cpu.setGS(w);
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break;
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case "CR0":
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this.cpu.regCR0 = w;
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X86.helpLoadCR0.call(this.cpu, w);
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break;
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case "CR2":
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this.cpu.regCR2 = w;
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break;
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case "CR3":
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this.cpu.regCR3 = w;
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X86.helpLoadCR3.call(this.cpu, w);
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break;
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/*
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* TODO: Add support for DR0-DR7 and TR6-TR7.
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*/
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default:
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fUnknown = true;
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break;
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}
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break;
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/*
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* TODO: Add support for GDTR (addr and limit), IDTR (addr and limit), and perhaps
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* even the ability to edit descriptor information associated with each segment register.
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*/
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default:
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fUnknown = true;
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if (I386 && this.cpu.model >= X86.MODEL_80386) {
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fUnknown = false;
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switch(sRegMatch){
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case "EAX":
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this.cpu.regEAX = w;
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break;
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case "EBX":
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this.cpu.regEBX = w;
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break;
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case "ECX":
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this.cpu.regECX = w;
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break;
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case "EDX":
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this.cpu.regEDX = w;
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break;
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case "ESP":
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this.cpu.setSP(w);
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break;
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case "EBP":
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this.cpu.regEBP = w;
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break;
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case "ESI":
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this.cpu.regESI = w;
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break;
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case "EDI":
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this.cpu.regEDI = w;
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break;
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/*
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* DANGER: For any of the segment loads below, by going through the normal CPU
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* segment load procedure, you run the risk of generating a fault in the machine
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* if you're not careful. So, um, be careful.
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*/
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case "FS":
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this.cpu.setFS(w);
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break;
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case "GS":
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this.cpu.setGS(w);
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break;
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case "CR0":
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this.cpu.regCR0 = w;
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X86.helpLoadCR0.call(this.cpu, w);
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break;
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case "CR2":
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this.cpu.regCR2 = w;
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break;
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case "CR3":
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this.cpu.regCR3 = w;
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X86.helpLoadCR3.call(this.cpu, w);
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break;
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/*
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* TODO: Add support for DR0-DR7 and TR6-TR7.
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*/
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default:
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fUnknown = true;
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break;
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}
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}
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break;
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}
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break;
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}
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if (fUnknown) {
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this.println("unknown register: " + sReg);
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return;
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}
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}
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if (fUnknown) {
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this.println("unknown register: " + sReg);
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return;
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}
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}
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if (!fValid) {
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