Updated Closure Compiler, fixed some constant inlining problems, and turned PREFETCH off for now
This commit is contained in:
Jeff Parsons
parent
526da018d0
commit
8e71267747
34 changed files with 9226 additions and 3625 deletions
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@ -195,244 +195,6 @@ function X86CPU(parmsCPU)
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Component.subclass(X86CPU, CPU);
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X86CPU.CYCLES_8088 = {
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nWordCyclePenalty: 4, // NOTE: accurate for the 8088/80188 only (on the 8086/80186, it applies to odd addresses only)
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nEACyclesBase: 5, // base or index only (BX, BP, SI or DI)
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nEACyclesDisp: 6, // displacement only
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nEACyclesBaseIndex: 7, // base + index (BP+DI and BX+SI)
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nEACyclesBaseIndexExtra: 8, // base + index (BP+SI and BX+DI require an extra cycle)
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nEACyclesBaseDisp: 9, // base or index + displacement
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nEACyclesBaseIndexDisp: 11, // base + index + displacement (BP+DI+n and BX+SI+n)
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nEACyclesBaseIndexDispExtra:12, // base + index + displacement (BP+SI+n and BX+DI+n require an extra cycle)
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nOpCyclesAAA: 4, // AAA, AAS, DAA, DAS, TEST acc,imm
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nOpCyclesAAD: 60,
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nOpCyclesAAM: 83,
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nOpCyclesArithRR: 3, // ADC, ADD, AND, OR, SBB, SUB, XOR and CMP reg,reg cycle time
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nOpCyclesArithRM: 9, // ADC, ADD, AND, OR, SBB, SUB, and XOR reg,mem (and CMP mem,reg) cycle time
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nOpCyclesArithMR: 16, // ADC, ADD, AND, OR, SBB, SUB, and XOR mem,reg cycle time
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nOpCyclesArithMID: 1, // ADC, ADD, AND, OR, SBB, SUB, XOR and CMP mem,imm cycle delta
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nOpCyclesCall: 19,
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nOpCyclesCallF: 28,
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nOpCyclesCallWR: 16,
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nOpCyclesCallWM: 21,
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nOpCyclesCallDM: 37,
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nOpCyclesCLI: 2,
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nOpCyclesCompareRM: 9, // CMP reg,mem cycle time (same as nOpCyclesArithRM on an 8086 but not on a 80286)
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nOpCyclesCWD: 5,
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nOpCyclesBound: 33, // N/A if 8086/8088, 33-35 if 80186/80188 (TODO: Determine what the range means for an 80186/80188)
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nOpCyclesInP: 10,
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nOpCyclesInDX: 8,
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nOpCyclesIncR: 3, // INC reg, DEC reg
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nOpCyclesIncM: 15, // INC mem, DEC mem
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nOpCyclesInt: 51,
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nOpCyclesInt3D: 1,
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nOpCyclesIntOD: 2,
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nOpCyclesIntOFall: 4,
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nOpCyclesIRet: 32,
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nOpCyclesJmp: 15,
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nOpCyclesJmpF: 15,
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nOpCyclesJmpC: 16,
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nOpCyclesJmpCFall: 4,
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nOpCyclesJmpWR: 11,
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nOpCyclesJmpWM: 18,
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nOpCyclesJmpDM: 24,
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nOpCyclesLAHF: 4, // LAHF, SAHF, MOV reg,imm
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nOpCyclesLEA: 2,
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nOpCyclesLS: 16, // LDS, LES
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nOpCyclesLoop: 17, // LOOP, LOOPNZ
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nOpCyclesLoopZ: 18, // LOOPZ, JCXZ
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nOpCyclesLoopNZ: 19, // LOOPNZ
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nOpCyclesLoopFall: 5, // LOOP
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nOpCyclesLoopZFall: 6, // LOOPZ, JCXZ
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nOpCyclesMovRR: 2,
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nOpCyclesMovRM: 8,
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nOpCyclesMovMR: 9,
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nOpCyclesMovRI: 10,
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nOpCyclesMovMI: 10,
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nOpCyclesMovAM: 10,
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nOpCyclesMovMA: 10,
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nOpCyclesDivBR: 80, // range of 80-90
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nOpCyclesDivWR: 144, // range of 144-162
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nOpCyclesDivBM: 86, // range of 86-96
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nOpCyclesDivWM: 154, // range of 154-172
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nOpCyclesIDivBR: 101, // range of 101-112
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nOpCyclesIDivWR: 165, // range of 165-184
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nOpCyclesIDivBM: 107, // range of 107-118
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nOpCyclesIDivWM: 171, // range of 171-190
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nOpCyclesMulBR: 70, // range of 70-77
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nOpCyclesMulWR: 113, // range of 113-118
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nOpCyclesMulBM: 76, // range of 76-83
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nOpCyclesMulWM: 124, // range of 124-139
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nOpCyclesIMulBR: 80, // range of 80-98
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nOpCyclesIMulWR: 128, // range of 128-154
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nOpCyclesIMulBM: 86, // range of 86-104
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nOpCyclesIMulWM: 134, // range of 134-160
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nOpCyclesNegR: 3, // NEG reg, NOT reg
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nOpCyclesNegM: 16, // NEG mem, NOT mem
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nOpCyclesOutP: 10,
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nOpCyclesOutDX: 8,
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nOpCyclesPopAll: 51, // N/A if 8086/8088, 51 if 80186, 83 if 80188 (TODO: Verify)
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nOpCyclesPopReg: 8,
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nOpCyclesPopMem: 17,
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nOpCyclesPushAll: 36, // N/A if 8086/8088, 36 if 80186, 68 if 80188 (TODO: Verify)
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nOpCyclesPushReg: 11, // NOTE: "The 8086 Book" claims this is 10, but it's an outlier....
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nOpCyclesPushMem: 16,
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nOpCyclesPushSeg: 10,
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nOpCyclesPrefix: 2,
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nOpCyclesCmpS: 18,
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nOpCyclesCmpSr0: 9-2, // reduced by nOpCyclesPrefix
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nOpCyclesCmpSrn: 17-2, // reduced by nOpCyclesPrefix
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nOpCyclesLodS: 12,
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nOpCyclesLodSr0: 9-2, // reduced by nOpCyclesPrefix
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nOpCyclesLodSrn: 13-2, // reduced by nOpCyclesPrefix
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nOpCyclesMovS: 18,
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nOpCyclesMovSr0: 9-2, // reduced by nOpCyclesPrefix
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nOpCyclesMovSrn: 17-2, // reduced by nOpCyclesPrefix
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nOpCyclesScaS: 15,
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nOpCyclesScaSr0: 9-2, // reduced by nOpCyclesPrefix
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nOpCyclesScaSrn: 15-2, // reduced by nOpCyclesPrefix
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nOpCyclesStoS: 11,
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nOpCyclesStoSr0: 9-2, // reduced by nOpCyclesPrefix
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nOpCyclesStoSrn: 10-2, // reduced by nOpCyclesPrefix
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nOpCyclesRet: 8,
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nOpCyclesRetn: 12,
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nOpCyclesRetF: 18,
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nOpCyclesRetFn: 17,
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nOpCyclesShift1M: 15, // ROL/ROR/RCL/RCR/SHL/SHR/SAR reg,1
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nOpCyclesShiftCR: 8, // ROL/ROR/RCL/RCR/SHL/SHR/SAR reg,CL
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nOpCyclesShiftCM: 20, // ROL/ROR/RCL/RCR/SHL/SHR/SAR mem,CL
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nOpCyclesShiftCS: 2, // this is the left-shift value used to convert the count to the cycle cost
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nOpCyclesTestRR: 3,
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nOpCyclesTestRM: 9,
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nOpCyclesTestRI: 5,
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nOpCyclesTestMI: 11,
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nOpCyclesXchgRR: 4,
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nOpCyclesXchgRM: 17,
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nOpCyclesXLAT: 11
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};
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X86CPU.CYCLES_80286 = {
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nWordCyclePenalty: 0,
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nEACyclesBase: 0,
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nEACyclesDisp: 0,
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nEACyclesBaseIndex: 0,
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nEACyclesBaseIndexExtra: 0,
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nEACyclesBaseDisp: 0,
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nEACyclesBaseIndexDisp: 1,
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nEACyclesBaseIndexDispExtra:1,
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nOpCyclesAAA: 3,
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nOpCyclesAAD: 14,
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nOpCyclesAAM: 16,
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nOpCyclesArithRR: 2,
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nOpCyclesArithRM: 7,
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nOpCyclesArithMR: 7,
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nOpCyclesArithMID: 0,
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nOpCyclesCall: 7, // on the 80286, this ALSO includes the number of bytes in the target instruction
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nOpCyclesCallF: 13, // on the 80286, this ALSO includes the number of bytes in the target instruction
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nOpCyclesCallWR: 7, // on the 80286, this ALSO includes the number of bytes in the target instruction
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nOpCyclesCallWM: 11, // on the 80286, this ALSO includes the number of bytes in the target instruction
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nOpCyclesCallDM: 16, // on the 80286, this ALSO includes the number of bytes in the target instruction
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nOpCyclesCLI: 3,
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nOpCyclesCompareRM: 6,
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nOpCyclesCWD: 2,
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nOpCyclesBound: 13,
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nOpCyclesInP: 5,
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nOpCyclesInDX: 5,
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nOpCyclesIncR: 2,
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nOpCyclesIncM: 7,
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nOpCyclesInt: 23, // on the 80286, this ALSO includes the number of bytes in the target instruction
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nOpCyclesInt3D: 0,
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nOpCyclesIntOD: 1,
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nOpCyclesIntOFall: 3,
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nOpCyclesIRet: 17, // on the 80286, this ALSO includes the number of bytes in the target instruction
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nOpCyclesJmp: 7, // on the 80286, this ALSO includes the number of bytes in the target instruction
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nOpCyclesJmpF: 11, // on the 80286, this ALSO includes the number of bytes in the target instruction
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nOpCyclesJmpC: 7, // on the 80286, this ALSO includes the number of bytes in the target instruction
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nOpCyclesJmpCFall: 3,
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nOpCyclesJmpWR: 7, // on the 80286, this ALSO includes the number of bytes in the target instruction
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nOpCyclesJmpWM: 11, // on the 80286, this ALSO includes the number of bytes in the target instruction
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nOpCyclesJmpDM: 15, // on the 80286, this ALSO includes the number of bytes in the target instruction
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nOpCyclesLAHF: 2,
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nOpCyclesLEA: 3,
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nOpCyclesLS: 7,
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nOpCyclesLoop: 8, // on the 80286, this ALSO includes the number of bytes in the target instruction
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nOpCyclesLoopZ: 8, // on the 80286, this ALSO includes the number of bytes in the target instruction
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nOpCyclesLoopNZ: 8, // on the 80286, this ALSO includes the number of bytes in the target instruction
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nOpCyclesLoopFall: 4,
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nOpCyclesLoopZFall: 4,
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nOpCyclesMovRR: 2, // this is actually the same as the 8086...
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nOpCyclesMovRM: 3,
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nOpCyclesMovMR: 5,
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nOpCyclesMovRI: 2,
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nOpCyclesMovMI: 3,
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nOpCyclesMovAM: 5, // this is actually slower than the MOD/RM form of MOV AX,mem (see nOpCyclesMovRM)
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nOpCyclesMovMA: 3,
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nOpCyclesDivBR: 14,
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nOpCyclesDivWR: 22,
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nOpCyclesDivBM: 17,
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nOpCyclesDivWM: 25,
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nOpCyclesIDivBR: 17,
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nOpCyclesIDivWR: 25,
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nOpCyclesIDivBM: 20,
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nOpCyclesIDivWM: 28,
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nOpCyclesMulBR: 13,
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nOpCyclesMulWR: 21,
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nOpCyclesMulBM: 16,
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nOpCyclesMulWM: 24,
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nOpCyclesIMulBR: 13,
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nOpCyclesIMulWR: 21,
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nOpCyclesIMulBM: 16,
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nOpCyclesIMulWM: 24,
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nOpCyclesNegR: 2,
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nOpCyclesNegM: 7,
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nOpCyclesOutP: 5,
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nOpCyclesOutDX: 5,
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nOpCyclesPopAll: 19,
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nOpCyclesPopReg: 5,
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nOpCyclesPopMem: 5,
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nOpCyclesPushAll: 17,
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nOpCyclesPushReg: 3,
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nOpCyclesPushMem: 5,
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nOpCyclesPushSeg: 3,
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nOpCyclesPrefix: 0,
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nOpCyclesCmpS: 8,
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nOpCyclesCmpSr0: 5,
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nOpCyclesCmpSrn: 9,
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nOpCyclesLodS: 5,
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nOpCyclesLodSr0: 5,
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nOpCyclesLodSrn: 4,
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nOpCyclesMovS: 5,
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nOpCyclesMovSr0: 5,
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nOpCyclesMovSrn: 4,
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nOpCyclesScaS: 7,
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nOpCyclesScaSr0: 5,
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nOpCyclesScaSrn: 8,
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nOpCyclesStoS: 3,
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nOpCyclesStoSr0: 4,
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nOpCyclesStoSrn: 3,
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nOpCyclesRet: 11, // on the 80286, this ALSO includes the number of bytes in the target instruction
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nOpCyclesRetn: 11, // on the 80286, this ALSO includes the number of bytes in the target instruction
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nOpCyclesRetF: 15, // on the 80286, this ALSO includes the number of bytes in the target instruction
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nOpCyclesRetFn: 15, // on the 80286, this ALSO includes the number of bytes in the target instruction
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nOpCyclesShift1M: 7,
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nOpCyclesShiftCR: 5,
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nOpCyclesShiftCM: 8,
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nOpCyclesShiftCS: 0,
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nOpCyclesTestRR: 2,
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nOpCyclesTestRM: 6,
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nOpCyclesTestRI: 3,
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nOpCyclesTestMI: 6,
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nOpCyclesXchgRR: 3,
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nOpCyclesXchgRM: 5,
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nOpCyclesXLAT: 5
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};
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/*
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* TODO: All 80386 cycle counts are based on 80286 counts until I have time to hand-generate an 80386-specific table;
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* Cycle counts for 80386-only instructions are hard-coded in their respective handlers, since those counts don't vary.
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*/
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X86CPU.CYCLES_80386 = X86CPU.CYCLES_80286;
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if (PREFETCH) {
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/*
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* NOTE: X86CPU.PREFETCH.LENGTH must be set to a power of two, so that LENGTH - 1 will form a mask
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@ -975,7 +737,7 @@ X86CPU.prototype.initProcessor = function()
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this.OPFLAG_NOINTR_8086 = X86.OPFLAG.NOINTR;
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this.nShiftCountMask = 0xff; // on an 8086/8088, all shift counts are used as-is
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this.cycleCounts = (this.model == X86.MODEL_80386? X86CPU.CYCLES_80386 : (this.model == X86.MODEL_80286? X86CPU.CYCLES_80286 : X86CPU.CYCLES_8088));
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this.cycleCounts = (this.model >= X86.MODEL_80286? X86.CYCLES_80286 : X86.CYCLES_8088);
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this.aOps = X86.aOps;
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this.aOpGrp4b = X86.aOpGrp4b;
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