Added rudimentary PDP-10 assembler capability to the built-in debugger
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14 changed files with 501 additions and 262 deletions
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@ -13,7 +13,7 @@ PCjs has archived selected software for the following machines:
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* [IBM PC](pcx86/)
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* [Challenger 1P](c1p/)
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* [PDP-11](pdp11/)
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* DEC [PDP-10](pdp10/) and [PDP-11](pdp11/)
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PCjs also includes a small collection of disk images in the [Disk Libraries](/disks/):
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12
apps/pdp10/README.md
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12
apps/pdp10/README.md
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---
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layout: page
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title: PDP-10 Software
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permalink: /apps/pdp10/
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---
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PDP-10 Software
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---------------
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PCjs provides the following PDP-10 tests:
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- [PDP-10 Opcode Tests](tests/)
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122
apps/pdp10/tests/README.md
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122
apps/pdp10/tests/README.md
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---
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layout: page
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title: DEC PDP-10 Opcode Tests
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permalink: /apps/pdp10/tests/
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machines:
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- id: testka10
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type: pdp10
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debugger: true
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config: /devices/pdp10/machine/ka10/test/debugger/machine.xml
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---
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DEC PDP-10 Opcode Tests
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-----------------------
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The PDP-10 machine below loads the following test:
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- [PDP-10 Half-Word Opcode Test](optest-v01.json)
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Details on how to run and modify the test, and perform similar tests in [SIMH](https://github.com/simh/simh),
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are provided below.
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{% include machine.html id="testka10" %}
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The [PDP-10 Half-Word Opcode Test](optest-v01.json) file specifies that the following words:
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0o505040111111, // HRLI 1,111111
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0o541040444444, // HRRI 1,444444
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0o544100000001, // HLR 2,1
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0o504100000001, // HRL 2,1
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should be loaded at address 0o100, and that the program counter (PC register) should be set to 0o100. The embedded
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comments display the instructions that correspond to each word.
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If you want to alter or add new instructions, the PDP-10 Debugger now includes a rudimentary assembler. Using the `a` command,
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along with an optional start address, you can enter "assembler mode". For example, here's how the first four instructions from
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the [PDP-10 Half-Word Opcode Test](optest-v01.json) could be entered by hand:
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>> a 100
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begin assemble at 000100
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>> hrli 1,111111
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000100: 505040 111111 HRLI 1,111111
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>> hrri 1,444444
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000101: 541040 444444 HRRI 1,444444
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>> hlr 2,1
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000102: 544100 000001 HLR 2,1
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>> hrl 2,1
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000103: 504100 000001 HRL 2,1
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ended assemble at 000104
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Entering a blank line exits "assembler mode". To disassemble the four instructions, use `u 100 l4`:
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>> u 100 l4
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000100: 505040 111111 HRLI 1,111111
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000101: 541040 444444 HRRI 1,444444
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000102: 544100 000001 HLR 2,1
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000103: 504100 000001 HRL 2,1
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You can also copy-and-paste a series of instructions into the PDPjs Debugger, as long as each command ends
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with a semicolon:
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a 100;
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hrli 1,111111;
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hrri 1,444444;
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hlr 2,1;
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hrl 2,1;
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end
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Individual instructions can also be assembled *without* entering "assembler mode", as long as you precede
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each instruction with the `a` command and a specific address:
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a 100 hrli 1,111111;
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a 101 hrri 1,444444;
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a 102 hlr 2,1;
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a 103 hrl 2,1
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Individual instructions can be executed with the `t` command and memory can be dumped with the `d` command.
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After executing the first four instructions and using the `d 0 l4` command to dump first four words of memory
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(also known as AC registers 0-3), you should see the following output:
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>> r
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000100: 505040 111111 HRLI 1,111111
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>> t
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000101: 541040 444444 HRRI 1,444444
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>> t
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000102: 544100 000001 HLR 2,1
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>> t
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000103: 504100 000001 HRL 2,1
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>> t
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000104: 000000 000000 UUO 0,0
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>> d 0 l4
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000000: 000000 000000 111111 444444 444444 111111 000000 000000
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To assemble and test the same instructions in [SIMH](https://github.com/simh/simh), using the `pdp10` binary:
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sim> dep 100 505040111111
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sim> dep 101 541040444444
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sim> dep 102 544100000001
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sim> dep 103 504100000001
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sim> ex -m 100-103
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100: HRLI 1,111111
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101: HRRI 1,444444
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102: HLR 2,1
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103: HRL 2,1
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sim> dep pc 100
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sim> step
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Step expired, PC: 000101 (HRRI 1,444444)
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sim> step
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Step expired, PC: 000102 (HLR 2,1)
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sim> step
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Step expired, PC: 000103 (HRL 2,1)
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sim> step
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Step expired, PC: 000104 (000000000000)
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sim> ex 0-3
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0: 000000000000
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1: 111111444444
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2: 444444111111
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3: 000000000000
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10
apps/pdp10/tests/optest-v01.json
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10
apps/pdp10/tests/optest-v01.json
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{
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"load": 0o100,
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"exec": 0o100,
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"data": [
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0o505040111111, // HRLI 1,111111
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0o541040444444, // HRRI 1,444444
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0o544100000001, // HLR 2,1
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0o504100000001, // HRL 2,1
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]
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}
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@ -1,43 +0,0 @@
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{
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"load": 0o100,
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"exec": 0o100,
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"data": [
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0o505040111111, // HRLI 1,111111
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0o541040222222, // HRRI 1,222222
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0o544100000001, // HLR 2,1
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0o504100000001, // HRL 2,1
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//
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// >> dw 0 l4
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// 000000: 000000 000000 111111 222222 222222 111111 000000 000000
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//
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// Compare to SIMH:
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//
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// sim> dep 100 505040111111
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// sim> dep 101 541040222222
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// sim> dep 102 544100000001
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// sim> dep 103 504100000001
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// sim> ex -m 100-103
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// 100: HRLI 1,111111
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// 101: HRRI 1,222222
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// 102: HLR 2,1
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// 103: HRL 2,1
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// sim> dep pc 100
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// sim> step
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//
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// Step expired, PC: 000101 (HRRI 1,222222)
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// sim> step
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//
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// Step expired, PC: 000102 (HLR 2,1)
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// sim> step
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//
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// Step expired, PC: 000103 (HRL 2,1)
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// sim> step
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//
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// Step expired, PC: 000104 (000000000000)
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// sim> ex 0-3
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// 0: 000000000000
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// 1: 111111222222
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// 2: 222222111111
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// 3: 000000000000
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]
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}
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