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All PDP-10 MOVN (Move Negative) opcodes implemented

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This commit is contained in:
Jeff 2017-03-02 10:19:37 -08:00 • committed by Jeff Parsons
commit 84f8cece67
4 changed files with 692 additions and 364 deletions
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4
apps/pdp10/tests/optest-v01.json
View file

@ -15,14 +15,14 @@
0o541000000010, // 000112: HRRI 0,10 0o541000000010, // 000112: HRRI 0,10
0o251000000017, // 000113: BLT 0,17 0o251000000017, // 000113: BLT 0,17
// //
// 00=000000000010 01=111111444444 02=444444111111 03=777777444444 // 00=000010000020 01=111111444444 02=444444111111 03=777777444444
// 04=444444777777 05=777777777777 06=777777777777 07=000000000000 // 04=444444777777 05=777777777777 06=777777777777 07=000000000000
// 10=000000000010 11=111111444444 12=444444111111 13=777777444444 // 10=000000000010 11=111111444444 12=444444111111 13=777777444444
// 14=444444777777 15=777777777777 16=777777777777 17=000000000000 // 14=444444777777 15=777777777777 16=777777777777 17=000000000000
// //
0o577040000002, // 000114: HLRES 1,2 0o577040000002, // 000114: HLRES 1,2
// //
// 00=000000000010 01=000000111111 02=777777444444 03=777777444444 // 00=000010000020 01=777777444444 02=777777444444 03=777777444444
// 04=444444777777 05=777777777777 06=777777777777 07=000000000000 // 04=444444777777 05=777777777777 06=777777777777 07=000000000000
// 10=000000000010 11=111111444444 12=444444111111 13=777777444444 // 10=000000000010 11=111111444444 12=444444111111 13=777777444444
// 14=444444777777 15=777777777777 16=777777777777 17=000000000000 // 14=444444777777 15=777777777777 16=777777777777 17=000000000000

1016
modules/pdp10/lib/cpuops.js
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File diff suppressed because it is too large Load diff

4
modules/pdp10/lib/cpustate.js
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@ -443,12 +443,12 @@ class CPUStatePDP10 extends CPUPDP10 {
* *
* @this {CPUStatePDP10} * @this {CPUStatePDP10}
* @param {number} src (36-bit) * @param {number} src (36-bit)
* @return {number} (negated 36-bit src) * @return {number} (negated, but as an unsigned 36-bit result)
*/ */
negate(src) negate(src)
{ {
if (!src) { if (!src) {
this.fCarry = this.fCarry1 = true; this.fCarry0 = this.fCarry1 = true;
} }
else { else {
/* /*

32
modules/pdp10/lib/debugger.js
View file

@ -873,6 +873,18 @@ class DebuggerPDP10 extends Debugger {
case DebuggerPDP10.REGS.EA: case DebuggerPDP10.REGS.EA:
value = this.cpu.regEA; value = this.cpu.regEA;
break; break;
case DebuggerPDP10.REGS.C0:
value = this.cpu.fCarry0? 1 : 0;
break;
case DebuggerPDP10.REGS.C1:
value = this.cpu.fCarry1? 1 : 0;
break;
case DebuggerPDP10.REGS.OV:
value = this.cpu.fOverflow? 1 : 0;
break;
case DebuggerPDP10.REGS.ND:
value = this.cpu.fNoDivide? 1 : 0;
break;
} }
return value; return value;
} }
@ -2055,7 +2067,7 @@ class DebuggerPDP10 extends Debugger {
{ {
var sReg = this.getRegName(iReg); var sReg = this.getRegName(iReg);
if (sReg) { if (sReg) {
var nBits = (iReg == DebuggerPDP10.REGS.RA? 23 : 18); var nBits = (iReg >= DebuggerPDP10.REGS.C0? 1 : (iReg == DebuggerPDP10.REGS.RA? 23 : 18));
sReg += '=' + this.toStrBase(this.getRegValue(iReg), nBits) + ' '; sReg += '=' + this.toStrBase(this.getRegValue(iReg), nBits) + ' ';
} }
return sReg; return sReg;
@ -2070,18 +2082,22 @@ class DebuggerPDP10 extends Debugger {
getMiscDump() getMiscDump()
{ {
var sDump = ""; var sDump = "";
sDump += this.getRegOutput(DebuggerPDP10.REGS.PC) + this.getRegOutput(DebuggerPDP10.REGS.RA) + this.getRegOutput(DebuggerPDP10.REGS.EA); for (var i = 0; i < DebuggerPDP10.REGNAMES.length; i++) {
sDump += this.getRegOutput(i);
}
return sDump; return sDump;
} }
/** /**
* getRegDump(fMisc) * getRegDump(fMisc)
* *
* For now, fMisc defaults to true, providing a full register dump by default.
*
* @this {DebuggerPDP10} * @this {DebuggerPDP10}
* @param {boolean} [fMisc] (true to include misc registers) * @param {boolean} [fMisc] (true to include misc registers)
* @return {string} * @return {string}
*/ */
getRegDump(fMisc) getRegDump(fMisc = true)
{ {
var sDump = ""; var sDump = "";
for (var i = 0; i < 16; i++) { for (var i = 0; i < 16; i++) {
@ -3022,8 +3038,8 @@ class DebuggerPDP10 extends Debugger {
return; return;
} }
var fMisc = false;
var cpu = this.cpu; var cpu = this.cpu;
var fMisc = undefined;
if (fInstruction == null) fInstruction = true; if (fInstruction == null) fInstruction = true;
if (asArgs != null && asArgs.length > 1) { if (asArgs != null && asArgs.length > 1) {
@ -3798,11 +3814,15 @@ if (DEBUGGER) {
DebuggerPDP10.REGS = { DebuggerPDP10.REGS = {
PC: 0, PC: 0,
RA: 1, RA: 1,
EA: 2 EA: 2,
C0: 3, // single-bit "register" representing the Carry 0 flag
C1: 4, // single-bit "register" representing the Carry 1 flag
OV: 5, // single-bit "register" representing the Overflow flag
ND: 6, // single-bit "register" representing the No Divide flag
}; };
DebuggerPDP10.REGNAMES = [ DebuggerPDP10.REGNAMES = [
"PC", "RA", "EA" "PC", "RA", "EA", "C0", "C1", "OV", "ND"
]; ];
/* /*