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This commit is contained in:
Jeff Parsons 2016-09-17 18:19:46 -07:00
commit 6984a97512
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modules/pdp11/lib/debugger.js
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@ -295,7 +295,7 @@ if (DEBUGGER) {
* Note that, by convention, opcodes that require two operands list the SRC operand first and DST operand * Note that, by convention, opcodes that require two operands list the SRC operand first and DST operand
* second (ie, the OPPOSITE of the Intel convention). * second (ie, the OPPOSITE of the Intel convention).
* *
* Also note that, for some of the newer PDP-11 opcodes (eg, MUL, DIV, ASH, ASCH), the location of the * Also note that, for some of the newer PDP-11 opcodes (eg, MUL, DIV, ASH, ASHC), the location of the
* opcode's SRC and DST bits are reversed. This is why, for example, you'll see the MUL instruction defined * opcode's SRC and DST bits are reversed. This is why, for example, you'll see the MUL instruction defined
* below as having TYPE_DST for the first operand and TYPE_SRCREG for the second operand. This does NOT mean * below as having TYPE_DST for the first operand and TYPE_SRCREG for the second operand. This does NOT mean
* that the opcode's destination operand is being listed first, but rather that the bits describing the source * that the opcode's destination operand is being listed first, but rather that the bits describing the source