Retro/pcjs
Watch
1
0
Fork
You've already forked pcjs
 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Implemented (but have not yet tested) 286 LOADALL

Browse source
This commit is contained in:
Jeff Parsons 2014-10-31 13:40:19 -07:00 • committed by jeffpar
commit 5e6604b760
9 changed files with 335 additions and 173 deletions
Download patch file Download diff file Expand all files Collapse all files

4
pubs/pc/reference/intel/80286/loadall/README.md
View file

@ -19,7 +19,7 @@ iAPX 86 real mode programs.
All CPU registers (including LDTR, TR, GDTR, IDTR, and MSW) are loaded from memory by this instruction.
The normally hidden descriptor cache registers for the ES, DS, SS, CS, TR, and LDT registers are also loaded.
LOADALL may be executed in either real address mode or protected mode (CPL must be 0). Any attempt to execute
LOADALL at any privilege level other than 0 in protected rode causes exception 13 with an error code of 0.
LOADALL at any privilege level other than 0 in protected mode causes exception 13 with an error code of 0.
LOADALL allows direct control over the base, limit, and access rights associated with each segment register.
These values are kept in the descriptor cache registers which are normally hidden from programs. In protected mode,
@ -147,4 +147,4 @@ For proper protected mode operation, the following is required:
4. The DPL fields of the ES and DS descriptors should be 3 to prevent their being zeroed by RET or IRET
instructions.
[This information is from an undated 15-page Intel document titled "Undocumented iAPX 286 Test Instruction"]
[This information is from an undated 15-page Intel document titled "Undocumented iAPX 286 Test Instruction"]