Reordered flag output in the debugger to match bit order

This commit is contained in:
Jeff 2017-03-28 16:31:02 -07:00 committed by Jeff Parsons
commit 5a8a76249a
2 changed files with 14 additions and 14 deletions

View file

@ -922,15 +922,15 @@ class DebuggerPDP10 extends Debugger {
case DebuggerPDP10.REGS.PS:
value = (cpu.getPS() / PDP10.HALF_SHIFT)|0;
break;
case DebuggerPDP10.REGS.OV:
value = (cpu.regPS & PDP10.PSFLAG.AROV)? 1 : 0;
break;
case DebuggerPDP10.REGS.C0:
value = (cpu.regPS & PDP10.PSFLAG.CRY0)? 1 : 0;
break;
case DebuggerPDP10.REGS.C1:
value = (cpu.regPS & PDP10.PSFLAG.CRY1)? 1 : 0;
break;
case DebuggerPDP10.REGS.OV:
value = (cpu.regPS & PDP10.PSFLAG.AROV)? 1 : 0;
break;
case DebuggerPDP10.REGS.ND:
value = (cpu.regPS & PDP10.PSFLAG.DCK)? 1 : 0;
break;
@ -961,15 +961,15 @@ class DebuggerPDP10 extends Debugger {
case DebuggerPDP10.REGS.PS:
cpu.setPS(value * PDP10.HALF_SHIFT);
break;
case DebuggerPDP10.REGS.OV:
flag = PDP10.PSFLAG.AROV;
break;
case DebuggerPDP10.REGS.C0:
flag = PDP10.PSFLAG.CRY0;
break;
case DebuggerPDP10.REGS.C1:
flag = PDP10.PSFLAG.CRY1;
break;
case DebuggerPDP10.REGS.OV:
flag = PDP10.PSFLAG.AROV;
break;
case DebuggerPDP10.REGS.ND:
flag = PDP10.PSFLAG.DCK;
break;
@ -2256,7 +2256,7 @@ class DebuggerPDP10 extends Debugger {
{
var sReg = this.getRegName(iReg);
if (sReg) {
var nBits = (iReg >= DebuggerPDP10.REGS.C0? 1 : (iReg == DebuggerPDP10.REGS.RA? 23 : 18));
var nBits = (iReg >= DebuggerPDP10.REGS.OV? 1 : (iReg == DebuggerPDP10.REGS.RA? 23 : 18));
sReg += '=' + this.toStrBase(this.getRegValue(iReg), nBits) + ' ';
}
return sReg;
@ -4076,15 +4076,15 @@ if (DEBUGGER) {
RA: 1,
EA: 2,
PS: 3,
C0: 4, // single-bit "register" representing the Carry 0 flag
C1: 5, // single-bit "register" representing the Carry 1 flag
OV: 6, // single-bit "register" representing the Overflow flag
OV: 4, // single-bit "register" representing the Overflow flag
C0: 5, // single-bit "register" representing the Carry 0 flag
C1: 6, // single-bit "register" representing the Carry 1 flag
ND: 7, // single-bit "register" representing the No Divide flag
PD: 8, // single-bit "register" representing the Pushdown Overflow flag
};
DebuggerPDP10.REGNAMES = [
"PC", "RA", "EA", "PS", "C0", "C1", "OV", "ND", "PD"
"PC", "RA", "EA", "PS", "OV", "C0", "C1", "ND", "PD"
];
/*

View file

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@ -212,7 +212,7 @@ function sg(a,b){var c=ff(a,b[1],a.ia);if(c){var d=b[2];if(void 0==d)a.u("begin
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