Added more register documentation
This commit is contained in:
Jeff
Jeff Parsons
parent
ff6d15a622
commit
56c305ca64
5 changed files with 503 additions and 349 deletions
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@ -123,14 +123,13 @@ CPUStatePDP11.prototype.reset = function()
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CPUStatePDP11.prototype.initRegs = function()
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{
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/*
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* TODO: Verify the initial state of all PDP-11 flags (are they documented?)
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* TODO: Verify the initial state of all PDP-11 flags and registers (are they well-documented?)
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*/
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this.flagC = 0x10000; // PSW C bit
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this.flagV = 0x8000; // PSW V bit
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this.flagZ = 0xffff; // ~ PSW Z bit (TODO: Why is Z clear instead of set like all other flags?)
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this.flagN = 0x8000; // PSW N bit
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this.regPSW = 0xf; // PSW other bits (TODO: What's the point of setting the flag bits here, too?)
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this.regOp = -1; // current opcode
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this.flagC = 0x10000; // PSW C bit
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this.flagV = 0x8000; // PSW V bit
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this.flagZ = 0xffff; // ~ PSW Z bit (TODO: Why do we clear instead of set Z, like other flags?)
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this.flagN = 0x8000; // PSW N bit
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this.regPSW = 0x000f; // PSW other bits (TODO: What's the point of setting the flag bits here, too?)
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this.regsGen = [ // General R0 - R7
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0, 0, 0, 0, 0, 0, 0, this.resetAddr
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];
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@ -140,22 +139,14 @@ CPUStatePDP11.prototype.initRegs = function()
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this.regsAltStack = [ // Alternate R6 stack pointers (kernel, super, illegal, user)
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0, 0, 0, 0
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];
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this.memory = []; // Main memory (words)
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this.interruptQueue = []; // List of interrupts pending
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this.pir = 0;
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this.runState = 0; // 0=run, 1=step, 2=wait, 3=run
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this.loopRate = 9999; // instructions we can execute in 12ms
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this.priorityReview = 2; // flag to mark if we need to check priority change
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this.stackLimit = 0xff;
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this.opFlags = 0;
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this.trapPSW = -1;
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this.CPU_Error = 0;
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this.cpuType = 70;
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this.MMR0 = 0;
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this.MMR1 = 0;
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this.MMR2 = 0;
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this.MMR3 = 0;
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this.mmuMode = 0; // current memory management mode (0=kernel,1=super,2=undefined,3=user)
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this.regSL = 0xff; // 177774
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this.regPIR = 0; // 177772
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this.regCPUErr = 0; // 177766
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this.MMR0 = 0; // 177572
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this.MMR1 = 0; // 177574
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this.MMR2 = 0; // 177576
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this.MMR3 = 0; // 172516
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this.mmuMode = 0; // current memory management mode (see PDP11.MODE.KERNEL | SUPER | UNUSED | USER)
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this.mmuEnable = 0; // MMU enabled for PDP11.ACCESS.READ or PDP11.ACCESS.WRITE
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this.mmuLastMode = 0;
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this.mmuLastPage = 0;
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@ -176,6 +167,16 @@ CPUStatePDP11.prototype.initRegs = function()
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this.controlReg = [ // various control registers we don't really care about
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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];
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this.regOp = -1; // current opcode
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this.opFlags = 0;
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this.cpuType = 70;
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this.trapPSW = -1;
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this.interruptQueue = []; // List of interrupts pending
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this.runState = 0; // 0=run, 1=step, 2=wait, 3=run
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this.loopRate = 9999; // instructions we can execute in 12ms
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this.priorityReview = 2; // flag to mark if we need to check priority change
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};
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/**
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@ -185,10 +186,10 @@ CPUStatePDP11.prototype.initRegs = function()
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*/
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CPUStatePDP11.prototype.resetRegs = function()
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{
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this.stackLimit = 0xff;
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this.CPU_Error = 0;
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this.regSL = 0xff;
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this.regCPUErr = 0;
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this.interruptQueue = [];
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this.pir = 0;
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this.regPIR = 0;
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this.MMR0 = this.MMR1 = this.MMR2 = this.MMR3 = this.mmuFrozen = this.mmuEnable = 0;
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this.mmuMask[0] = this.mmuMask[1] = this.mmuMask[3] = 0x7;
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this.mmuLastMode = 0;
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@ -739,7 +740,7 @@ CPUStatePDP11.prototype.trap = function(vector, reason)
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if ((newPSW = this.readWordByVirtual(((vector + 2) & 0xffff) | 0x10000)) >= 0) {
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this.setPSW((newPSW & 0xcfff) | ((this.trapPSW >> 2) & 0x3000)); // set new this.PSW with previous mode
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if (doubleTrap) {
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this.CPU_Error |= 4;
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this.regCPUErr |= PDP11.CPUERR.RED;
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this.regsGen[6] = 4;
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}
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if (this.pushWord(this.trapPSW) >= 0 && this.pushWord(this.regsGen[7]) >= 0) {
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@ -763,7 +764,7 @@ CPUStatePDP11.prototype.mapUnibus = function(unibusAddress)
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{
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var idx = (unibusAddress >> 13) & 0x1f;
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if (idx < 31) {
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if (this.MMR3 & 0x20) {
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if (this.MMR3 & PDP11.MMR3.UNIBUS_MAP) {
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unibusAddress = (this.unibusMap[idx] + (unibusAddress & 0x1ffe)) & 0x3ffffe;
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if (unibusAddress >= BusPDP11.IOPAGE_UNIBUS && unibusAddress < BusPDP11.IOPAGE_22BIT) this.panic(898);
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}
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@ -832,7 +833,7 @@ CPUStatePDP11.prototype.mapVirtualToPhysical = function(virtualAddress, accessFl
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physicalAddress |= BusPDP11.IOPAGE_22BIT;
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} else { // no max_memory check in 16 bit mode
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if ((physicalAddress & 1) && !(accessFlags & PDP11.ACCESS.BYTE)) {
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this.CPU_Error |= 0x40;
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this.regCPUErr |= PDP11.CPUERR.ODDADDR;
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this.trap(PDP11.TRAP.BUS_ERROR, 22);
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}
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}
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@ -852,11 +853,11 @@ CPUStatePDP11.prototype.mapVirtualToPhysical = function(virtualAddress, accessFl
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}
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if (physicalAddress < BusPDP11.IOPAGE_UNIBUS) {
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if (physicalAddress >= BusPDP11.MAX_MEMORY) {
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this.CPU_Error |= 0x20;
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this.regCPUErr |= PDP11.CPUERR.NOMEMORY;
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this.trap(PDP11.TRAP.BUS_ERROR, 24); // KB11-EM does this after ABORT handling - KB11-CM before
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}
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if ((physicalAddress & 1) && !(accessFlags & PDP11.ACCESS.BYTE)) {
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this.CPU_Error |= 0x40;
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this.regCPUErr |= PDP11.CPUERR.ODDADDR;
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this.trap(PDP11.TRAP.BUS_ERROR, 26);
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}
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}
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@ -1066,13 +1067,13 @@ CPUStatePDP11.prototype.pushWord = function(data)
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if (!(this.MMR0 & 0xe000)) {
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this.MMR1 = (this.MMR1 << 8) | 0xf6;
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}
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if ((!this.mmuMode) && virtualAddress <= this.stackLimit && virtualAddress > 4) {
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if (virtualAddress <= this.stackLimit - 32) {
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this.CPU_Error |= 4; // Red stack
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if ((!this.mmuMode) && virtualAddress <= this.regSL && virtualAddress > 4) {
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if (virtualAddress <= this.regSL - 32) {
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this.regCPUErr |= PDP11.CPUERR.RED;
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this.regsGen[6] = 4;
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this.trap(PDP11.TRAP.BUS_ERROR, 32);
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} else {
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this.CPU_Error |= 8; // Yellow
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this.regCPUErr |= PDP11.CPUERR.YELLOW;
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this.opFlags |= 4;
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}
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}
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@ -1123,13 +1124,13 @@ CPUStatePDP11.prototype.getVirtualByMode = function(addressMode, accessFlags)
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case 1: // Mode 1: (R)
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if (reg === 6 && (!this.mmuMode) && (accessFlags & PDP11.ACCESS.WRITE) &&
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(this.regsGen[6] <= this.stackLimit || this.regsGen[6] >= 0xfffe)) {
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if (this.regsGen[6] <= this.stackLimit - 32 || this.regsGen[6] >= 0xfffe) {
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this.CPU_Error |= 4; // Red stack
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(this.regsGen[6] <= this.regSL || this.regsGen[6] >= 0xfffe)) {
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if (this.regsGen[6] <= this.regSL - 32 || this.regsGen[6] >= 0xfffe) {
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this.regCPUErr |= PDP11.CPUERR.RED;
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this.regsGen[6] = 4;
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this.trap(PDP11.TRAP.BUS_ERROR, 36);
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} else {
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this.CPU_Error |= 8; // Yellow
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this.regCPUErr |= PDP11.CPUERR.YELLOW;
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this.opFlags |= PDP11.OPFLAG.TRAP_SP;
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}
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}
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@ -1207,13 +1208,13 @@ CPUStatePDP11.prototype.getVirtualByMode = function(addressMode, accessFlags)
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this.MMR1 = (this.MMR1 << 8) | ((stepSize << 3) & 0xf8) | reg;
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}
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if (reg === 6 && (!this.mmuMode) && (accessFlags & PDP11.ACCESS.WRITE) && stepSize <= 0 &&
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(this.regsGen[6] <= this.stackLimit || this.regsGen[6] >= 0xfffe)) {
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if (this.regsGen[6] <= this.stackLimit - 32) {
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this.CPU_Error |= 4; // Red stack
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(this.regsGen[6] <= this.regSL || this.regsGen[6] >= 0xfffe)) {
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if (this.regsGen[6] <= this.regSL - 32) {
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this.regCPUErr |= PDP11.CPUERR.RED;
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this.regsGen[6] = 4;
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this.trap(PDP11.TRAP.BUS_ERROR, 38);
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} else {
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this.CPU_Error |= 8; // Yellow
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this.regCPUErr |= PDP11.CPUERR.YELLOW;
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this.opFlags |= PDP11.OPFLAG.TRAP_SP;
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}
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}
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@ -1493,7 +1494,7 @@ CPUStatePDP11.prototype.stepCPU = function(nMinCycles)
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} else {
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this.priorityReview = 0;
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j = -1;
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savePSW = this.pir & 0xe0;
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savePSW = this.regPIR & 0xe0;
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if ((i = this.interruptQueue.length) > 0) {
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while (i-- > 0) {
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if (this.interruptQueue[i].delay > 0) {
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@ -2483,7 +2484,7 @@ CPUStatePDP11.prototype.stepCPU = function(nMinCycles)
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case 0x0: /*0000000*/ // HALT 000000
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//LOG_INSTRUCTION(opCode, 0, "HALT");
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if (0xc000 & this.PSW) {
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this.CPU_Error |= 0x80; /*0200*/
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this.regCPUErr |= PDP11.CPUERR.BADHALT;
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this.trap(PDP11.TRAP.BUS_ERROR, 46);
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} else {
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this.runState = 3; // halt
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@ -236,19 +236,168 @@ var PDP11 = {
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ZERO: 0x1, // zero byte or word
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SIGNEXT: 0x2 // sign-extend a byte to a word
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},
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CPUERR: {
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RED: 0x0004, // red zone stack limit
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YELLOW: 0x0008, // yellow zone stack limit
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TIMEOUT: 0x0010, // UNIBUS timeout error
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NOMEMORY: 0x0020, // non-existent memory error
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ODDADDR: 0x0040, // odd word address error (as in non-even, not strange)
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BADHALT: 0x0080 // HALT attempted in USER or SUPER modes
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},
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MMR0: {
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ENABLED: 0x0001, // address relocation enabled
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PAGE_NUM: 0x000E, // page number of last fault
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PAGE_D: 0x0010, // last fault occurred in D space
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PAGE_MODE: 0x0060, // processor mode as of last fault
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COMPLETED: 0x0080, // last instruction completed
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DSTMODE: 0x0100, // only destination mode references will be relocated (for diagnostic use)
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MMU_TRAPS: 0x0200, // enable MMU traps
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UNUSED: 0x0C00,
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TRAP_MMU: 0x1000, // trap: MMU
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ABORT_RO: 0x2000, // abort: read-only
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ABORT_PL: 0x4000, // abort: page length
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ABORT_NR: 0x8000 // abort: non-resident
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},
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MMR1: { // general purpose auto-inc/auto-dec register
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REG1_NUM: 0x0007,
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REG1_DELTA: 0x00F8,
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REG2_NUM: 0x0700,
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REG2_DELTA: 0xF800
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},
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MMR2: { // virtual program counter register
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},
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MMR3: { // mapping register
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USER_D: 0x0001,
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SUPER_D: 0x0002,
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KERNEL_D: 0x0004,
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MMU_22BIT: 0x0010,
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UNIBUS_MAP: 0x0020 // UNIBUS map relocation enabled
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},
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/*
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* Assorted special (UNIBUS) addresses
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*
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* Within the PDP-11's 18-bit address space, of the 0x40000 possible addresses, the top 8Kb (0x2000)
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* is called the IOPAGE and is reserved for CPU and I/O registers. The IOPAGE spans 0x3E000-0x3FFFF.
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*
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* To map UNIBUS addresses to 22-bit physical addresses, a UNIBUS relocation map is used. It consists
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* of 31 double-word registers that each hold a 22-bit base address. When UNIBUS relocation is enabled,
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* the top 5 bits of an address select one of the 31 mapping registers, and the bottom 13 bits are then
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* added to the contents of the selected mapping register.
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*
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* ES6 ALERT: By using octal constants, this is the first place I'm dipping my toe into ECMAScript 6 waters.
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* If you're loading this raw source code into your browser, then by now (2016) you're almost certainly using
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* an ES6-aware browser. Everyone else should be using code compiled by Google's Closure Compiler, which
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* automatically produces code that's backward-compatible with ES5.1 (for example, octal constants are converted
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* to decimal values).
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* automatically produces code that's backward-compatible with ES5.1 (for example, octal constants are
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* converted to decimal values).
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*
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* For more details: https://github.com/google/closure-compiler/wiki/ECMAScript6
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*/
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UNIBUS: { // 22-bit 18-bit 16-bit 22-bit Description
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PSW: 0o17777776, // 777776 177776 0x3FFFFE PSW
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UNIBUS: { //16-bit 18-bit 22-bit Hex Description
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PSW: 0o177776, // 777776 17777776 0x3FFFFE PSW
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SL: 0o177774, // Stack Limit
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PIR: 0o177772, // Program Interrupt Request
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MB: 0o177770, // Microprogram break
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CPUERR: 0o177766, // CPU error
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MMR0: 0o177572, // 777572 17777572
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MMR1: 0o177574, // 777574 17777574
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MMR2: 0o177576, // 777576 17777576
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MMR3: 0o172516, // 772516 17772516
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UISDR0: 0o177600, // User I Space Descriptor Register 0
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UISDR1: 0o177602, // User I Space Descriptor Register 1
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UISDR2: 0o177604, // User I Space Descriptor Register 2
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UISDR3: 0o177606, // User I Space Descriptor Register 3
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UISDR4: 0o177610, // User I Space Descriptor Register 4
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UISDR5: 0o177612, // User I Space Descriptor Register 5
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UISDR6: 0o177614, // User I Space Descriptor Register 6
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UISDR7: 0o177616, // User I Space Descriptor Register 7
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UDSDR0: 0o177620, // User D Space Descriptor Register 0
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UDSDR1: 0o177622, // User D Space Descriptor Register 1
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UDSDR2: 0o177624, // User D Space Descriptor Register 2
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UDSDR3: 0o177626, // User D Space Descriptor Register 3
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UDSDR4: 0o177630, // User D Space Descriptor Register 4
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UDSDR5: 0o177632, // User D Space Descriptor Register 5
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UDSDR6: 0o177634, // User D Space Descriptor Register 6
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UDSDR7: 0o177636, // User D Space Descriptor Register 7
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UISAR0: 0o177640, // User I Space Address Register 0
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UISAR1: 0o177642, // User I Space Address Register 1
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UISAR2: 0o177644, // User I Space Address Register 2
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UISAR3: 0o177646, // User I Space Address Register 3
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UISAR4: 0o177650, // User I Space Address Register 4
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UISAR5: 0o177652, // User I Space Address Register 5
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UISAR6: 0o177654, // User I Space Address Register 6
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UISAR7: 0o177656, // User I Space Address Register 7
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UDSAR0: 0o177660, // User D Space Address Register 0
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UDSAR1: 0o177662, // User D Space Address Register 1
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UDSAR2: 0o177664, // User D Space Address Register 2
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UDSAR3: 0o177666, // User D Space Address Register 3
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UDSAR4: 0o177670, // User D Space Address Register 4
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UDSAR5: 0o177672, // User D Space Address Register 5
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UDSAR6: 0o177674, // User D Space Address Register 6
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UDSAR7: 0o177676, // User D Space Address Register 7
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SISDR0: 0o172200, // Supervisor I Space Descriptor Register 0
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SISDR1: 0o172202, // Supervisor I Space Descriptor Register 1
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SISDR2: 0o172204, // Supervisor I Space Descriptor Register 2
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SISDR3: 0o172206, // Supervisor I Space Descriptor Register 3
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SISDR4: 0o172210, // Supervisor I Space Descriptor Register 4
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SISDR5: 0o172212, // Supervisor I Space Descriptor Register 5
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SISDR6: 0o172214, // Supervisor I Space Descriptor Register 6
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SISDR7: 0o172216, // Supervisor I Space Descriptor Register 7
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SDSDR0: 0o172220, // Supervisor D Space Descriptor Register 0
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SDSDR1: 0o172222, // Supervisor D Space Descriptor Register 1
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SDSDR2: 0o172224, // Supervisor D Space Descriptor Register 2
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SDSDR3: 0o172226, // Supervisor D Space Descriptor Register 3
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SDSDR4: 0o172230, // Supervisor D Space Descriptor Register 4
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SDSDR5: 0o172232, // Supervisor D Space Descriptor Register 5
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SDSDR6: 0o172234, // Supervisor D Space Descriptor Register 6
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SDSDR7: 0o172236, // Supervisor D Space Descriptor Register 7
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SISAR0: 0o172240, // Supervisor I Space Address Register 0
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SISAR1: 0o172242, // Supervisor I Space Address Register 1
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SISAR2: 0o172244, // Supervisor I Space Address Register 2
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SISAR3: 0o172246, // Supervisor I Space Address Register 3
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SISAR4: 0o172250, // Supervisor I Space Address Register 4
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SISAR5: 0o172252, // Supervisor I Space Address Register 5
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SISAR6: 0o172254, // Supervisor I Space Address Register 6
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SISAR7: 0o172256, // Supervisor I Space Address Register 7
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SDSAR0: 0o172260, // Supervisor D Space Address Register 0
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SDSAR1: 0o172262, // Supervisor D Space Address Register 1
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SDSAR2: 0o172264, // Supervisor D Space Address Register 2
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SDSAR3: 0o172266, // Supervisor D Space Address Register 3
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SDSAR4: 0o172270, // Supervisor D Space Address Register 4
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SDSAR5: 0o172272, // Supervisor D Space Address Register 5
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SDSAR6: 0o172274, // Supervisor D Space Address Register 6
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SDSAR7: 0o172276, // Supervisor D Space Address Register 7
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KISDR0: 0o172300, // Kernel I Space Descriptor Register 0
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KISDR1: 0o172302, // Kernel I Space Descriptor Register 1
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KISDR2: 0o172304, // Kernel I Space Descriptor Register 2
|
||||
KISDR3: 0o172306, // Kernel I Space Descriptor Register 3
|
||||
KISDR4: 0o172310, // Kernel I Space Descriptor Register 4
|
||||
KISDR5: 0o172312, // Kernel I Space Descriptor Register 5
|
||||
KISDR6: 0o172314, // Kernel I Space Descriptor Register 6
|
||||
KISDR7: 0o172316, // Kernel I Space Descriptor Register 7
|
||||
KDSDR0: 0o172320, // Kernel D Space Descriptor Register 0
|
||||
KDSDR1: 0o172322, // Kernel D Space Descriptor Register 1
|
||||
KDSDR2: 0o172324, // Kernel D Space Descriptor Register 2
|
||||
KDSDR3: 0o172326, // Kernel D Space Descriptor Register 3
|
||||
KDSDR4: 0o172330, // Kernel D Space Descriptor Register 4
|
||||
KDSDR5: 0o172332, // Kernel D Space Descriptor Register 5
|
||||
KDSDR6: 0o172334, // Kernel D Space Descriptor Register 6
|
||||
KDSDR7: 0o172336, // Kernel D Space Descriptor Register 7
|
||||
KISAR0: 0o172340, // Kernel I Space Address Register 0
|
||||
KISAR1: 0o172342, // Kernel I Space Address Register 1
|
||||
KISAR2: 0o172344, // Kernel I Space Address Register 2
|
||||
KISAR3: 0o172346, // Kernel I Space Address Register 3
|
||||
KISAR4: 0o172350, // Kernel I Space Address Register 4
|
||||
KISAR5: 0o172352, // Kernel I Space Address Register 5
|
||||
KISAR6: 0o172354, // Kernel I Space Address Register 6
|
||||
KISAR7: 0o172356, // Kernel I Space Address Register 7
|
||||
KDSAR0: 0o172360, // Kernel D Space Address Register 0
|
||||
KDSAR1: 0o172362, // Kernel D Space Address Register 1
|
||||
KDSAR2: 0o172364, // Kernel D Space Address Register 2
|
||||
KDSAR3: 0o172366, // Kernel D Space Address Register 3
|
||||
KDSAR4: 0o172370, // Kernel D Space Address Register 4
|
||||
KDSAR5: 0o172372, // Kernel D Space Address Register 5
|
||||
KDSAR6: 0o172374, // Kernel D Space Address Register 6
|
||||
KDSAR7: 0o172376, // Kernel D Space Address Register 7
|
||||
}
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -204,7 +204,7 @@ DevicePDP11.prototype.initBus = function(cmp, bus, cpu, dbg)
|
|||
* readPSW(addr)
|
||||
*
|
||||
* @this {DevicePDP11}
|
||||
* @param {number} addr (ie, PDP11.UNIBUS.PSW)
|
||||
* @param {number} addr (eg, PDP11.UNIBUS.PSW)
|
||||
* @return {number}
|
||||
*/
|
||||
DevicePDP11.prototype.readPSW = function(addr)
|
||||
|
|
@ -697,7 +697,7 @@ DevicePDP11.prototype.insertData = function(original, physicalAddress, data, byt
|
|||
if (physicalAddress & 1) {
|
||||
if (!byteFlag) {
|
||||
//log.push("TRAP 4 201 " + physicalAddress.toString(8) + " " + data.toString(8));
|
||||
return this.cpu.trap(4, 122);
|
||||
return this.cpu.trap(PDP11.TRAP.BUS_ERROR, 122);
|
||||
}
|
||||
if (data >= 0) {
|
||||
data = ((data << 8) & 0xff00) | (original & 0xff);
|
||||
|
|
@ -821,7 +821,7 @@ DevicePDP11.prototype.access = function(physicalAddress, data, byteFlag)
|
|||
case 0x3FFFC0: /*017777700*/ // 017777700 - 017777777
|
||||
switch (physicalAddress & ~1) {
|
||||
/*
|
||||
* Superseded by UNIBUS_TABLE (much more of this code will be commented out
|
||||
* Superseded by UNIBUS_TABLE (more of this code will be commented out
|
||||
* as it is replaced by read/write handlers in the UNIBUS_TABLE; stay tuned).
|
||||
*
|
||||
case 0x3FFFFE: // 017777776 // PSW
|
||||
|
|
@ -840,19 +840,19 @@ DevicePDP11.prototype.access = function(physicalAddress, data, byteFlag)
|
|||
*/
|
||||
case 0x3FFFFC: /*017777774*/ // stack limit
|
||||
if (data < 0) {
|
||||
result = cpu.stackLimit & 0xff00;
|
||||
result = cpu.regSL & 0xff00;
|
||||
} else {
|
||||
if (physicalAddress & 1) {
|
||||
data = data << 8;
|
||||
}
|
||||
cpu.stackLimit = data | 0xff;
|
||||
cpu.regSL = data | 0xff;
|
||||
result = 0;
|
||||
}
|
||||
//log.push("stacklimit access "+cpu.stackLimit.toString(8));
|
||||
//log.push("stack limit access "+cpu.regSL.toString(8));
|
||||
break;
|
||||
case 0x3FFFFA: /*017777772*/ // PIR
|
||||
if (data < 0) {
|
||||
result = cpu.pir;
|
||||
result = cpu.regPIR;
|
||||
} else {
|
||||
if (physicalAddress & 1) {
|
||||
data = data << 8;
|
||||
|
|
@ -864,28 +864,28 @@ DevicePDP11.prototype.access = function(physicalAddress, data, byteFlag)
|
|||
result += 0x22;
|
||||
} while (idx >>= 1);
|
||||
}
|
||||
cpu.pir = result;
|
||||
cpu.regPIR = result;
|
||||
cpu.priorityReview = 2;
|
||||
}
|
||||
break;
|
||||
case 0x3FFFF6: /*017777766*/ // CPU error
|
||||
if (cpu.cpuType !== 70) return cpu.trap(4, 222);
|
||||
if (cpu.cpuType !== 70) return cpu.trap(PDP11.TRAP.BUS_ERROR, 222);
|
||||
if (data < 0) {
|
||||
result = cpu.CPU_Error;
|
||||
result = cpu.regCPUErr;
|
||||
} else {
|
||||
result = cpu.CPU_Error = 0; // Always writes as zero?
|
||||
result = cpu.regCPUErr = 0; // TODO: Always writes as zero?
|
||||
}
|
||||
break;
|
||||
case 0x3FFFF4: /*017777764*/ // System I/D
|
||||
if (cpu.cpuType !== 70) return cpu.trap(4, 224);
|
||||
if (cpu.cpuType !== 70) return cpu.trap(PDP11.TRAP.BUS_ERROR, 224);
|
||||
result = 1;
|
||||
break;
|
||||
case 0x3FFFF2: /*017777762*/ // Upper size
|
||||
if (cpu.cpuType !== 70) return cpu.trap(4, 226);
|
||||
if (cpu.cpuType !== 70) return cpu.trap(PDP11.TRAP.BUS_ERROR, 226);
|
||||
result = 0;
|
||||
break;
|
||||
case 0x3FFFF0: /*017777760*/ // Lower size
|
||||
if (cpu.cpuType !== 70) return cpu.trap(4, 228);
|
||||
if (cpu.cpuType !== 70) return cpu.trap(PDP11.TRAP.BUS_ERROR, 228);
|
||||
result = (BusPDP11.MAX_MEMORY >> 6) - 1;
|
||||
break;
|
||||
case 0x3FFFF8: /*017777770*/ // Microprogram break
|
||||
|
|
@ -899,7 +899,7 @@ DevicePDP11.prototype.access = function(physicalAddress, data, byteFlag)
|
|||
case 0x3FFFE4: /*017777744*/ // Memory system error
|
||||
case 0x3FFFE2: /*017777742*/ // High error address
|
||||
case 0x3FFFE0: /*017777740*/ // Low error address
|
||||
if (cpu.cpuType !== 70) return cpu.trap(4, 232);
|
||||
if (cpu.cpuType !== 70) return cpu.trap(PDP11.TRAP.BUS_ERROR, 232);
|
||||
idx = (physicalAddress - 0x3FFFE0) /*017777740*/ >> 1;
|
||||
if (data < 0) {
|
||||
result = cpu.controlReg[idx];
|
||||
|
|
@ -968,8 +968,8 @@ DevicePDP11.prototype.access = function(physicalAddress, data, byteFlag)
|
|||
}
|
||||
return result;
|
||||
default:
|
||||
cpu.CPU_Error |= 0x10;
|
||||
return cpu.trap(4, 124);
|
||||
cpu.regCPUErr |= PDP11.CPUERR.TIMEOUT;
|
||||
return cpu.trap(PDP11.TRAP.BUS_ERROR, 124);
|
||||
}
|
||||
break;
|
||||
case 0x3FFF80: /*017777600*/ // 017777600 - 017777677 MMU user mode Map
|
||||
|
|
@ -1121,8 +1121,8 @@ DevicePDP11.prototype.access = function(physicalAddress, data, byteFlag)
|
|||
}
|
||||
break;
|
||||
default:
|
||||
cpu.CPU_Error |= 0x10;
|
||||
return cpu.trap(4, 126);
|
||||
cpu.regCPUErr |= PDP11.CPUERR.TIMEOUT;
|
||||
return cpu.trap(PDP11.TRAP.BUS_ERROR, 126);
|
||||
}
|
||||
break;
|
||||
case 0x3FFF00: /*017777400*/ // 017777400 - 017777477
|
||||
|
|
@ -1164,8 +1164,8 @@ DevicePDP11.prototype.access = function(physicalAddress, data, byteFlag)
|
|||
if (result >= 0) rk11.rkdb = result;
|
||||
break;
|
||||
default:
|
||||
cpu.CPU_Error |= 0x10;
|
||||
return cpu.trap(4, 128);
|
||||
cpu.regCPUErr |= PDP11.CPUERR.TIMEOUT;
|
||||
return cpu.trap(PDP11.TRAP.BUS_ERROR, 128);
|
||||
}
|
||||
break;
|
||||
case 0x3FFDC0: /*017776700*/ // 017777600 - 017777677 rp11 controller
|
||||
|
|
@ -1269,8 +1269,8 @@ DevicePDP11.prototype.access = function(physicalAddress, data, byteFlag)
|
|||
if (result >= 0) rp11.rpcs3 = result;
|
||||
break;
|
||||
default:
|
||||
cpu.CPU_Error |= 0x10;
|
||||
return cpu.trap(4, 132);
|
||||
cpu.regCPUErr |= PDP11.CPUERR.TIMEOUT;
|
||||
return cpu.trap(PDP11.TRAP.BUS_ERROR, 132);
|
||||
}
|
||||
break;
|
||||
case 0x3FF900: /*017774400*/ // 017774400 - 017774477
|
||||
|
|
@ -1308,8 +1308,8 @@ DevicePDP11.prototype.access = function(physicalAddress, data, byteFlag)
|
|||
}
|
||||
break;
|
||||
default:
|
||||
cpu.CPU_Error |= 0x10;
|
||||
return cpu.trap(4, 134);
|
||||
cpu.regCPUErr |= PDP11.CPUERR.TIMEOUT;
|
||||
return cpu.trap(PDP11.TRAP.BUS_ERROR, 134);
|
||||
}
|
||||
break;
|
||||
case 0x3FF540: /*017772500*/ // 017772500 - 017772577
|
||||
|
|
@ -1334,8 +1334,8 @@ DevicePDP11.prototype.access = function(physicalAddress, data, byteFlag)
|
|||
}
|
||||
break;
|
||||
default:
|
||||
cpu.CPU_Error |= 0x10;
|
||||
return cpu.trap(4, 136);
|
||||
cpu.regCPUErr |= PDP11.CPUERR.TIMEOUT;
|
||||
return cpu.trap(PDP11.TRAP.BUS_ERROR, 136);
|
||||
}
|
||||
break;
|
||||
case 0x3FF4C0: /*017772300*/ // 017772300 - 017772377 MMU kernel mode Map
|
||||
|
|
@ -1356,7 +1356,7 @@ DevicePDP11.prototype.access = function(physicalAddress, data, byteFlag)
|
|||
break;
|
||||
case 0x3FF0C0: /*017770300*/ // 017770300 - 017770377 Unibus Map
|
||||
case 0x3FF080: /*017770200*/ // 017770200 - 017770277 Unibus Map
|
||||
if (cpu.cpuType !== 70) return cpu.trap(4, 234);
|
||||
if (cpu.cpuType !== 70) return cpu.trap(PDP11.TRAP.BUS_ERROR, 234);
|
||||
idx = (physicalAddress >> 2) & 0x1f;
|
||||
result = cpu.unibusMap[idx];
|
||||
if (physicalAddress & 0x2) /*02*/ result = result >> 16;
|
||||
|
|
@ -1384,13 +1384,13 @@ DevicePDP11.prototype.access = function(physicalAddress, data, byteFlag)
|
|||
idx = (physicalAddress >> 1) & 0xff;
|
||||
result = DevicePDP11.M9312[idx];
|
||||
} else {
|
||||
cpu.CPU_Error |= 0x10;
|
||||
return cpu.trap(4, 138);
|
||||
cpu.regCPUErr |= PDP11.CPUERR.TIMEOUT;
|
||||
return cpu.trap(PDP11.TRAP.BUS_ERROR, 138);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
cpu.CPU_Error |= 0x10;
|
||||
return cpu.trap(4, 142);
|
||||
cpu.regCPUErr |= PDP11.CPUERR.TIMEOUT;
|
||||
return cpu.trap(PDP11.TRAP.BUS_ERROR, 142);
|
||||
}
|
||||
if (byteFlag && result >= 0) { // make any required byte adjustment
|
||||
if ((physicalAddress & 1)) {
|
||||
|
|
@ -1405,8 +1405,12 @@ DevicePDP11.prototype.access = function(physicalAddress, data, byteFlag)
|
|||
return result;
|
||||
};
|
||||
|
||||
DevicePDP11.UNIBUS_TABLE = {};
|
||||
DevicePDP11.UNIBUS_TABLE[PDP11.UNIBUS.PSW] = [null, null, DevicePDP11.prototype.readPSW, DevicePDP11.prototype.writePSW];
|
||||
/*
|
||||
* ES6 ALERT: As you can see below, I've finally started using computed property names.
|
||||
*/
|
||||
DevicePDP11.UNIBUS_TABLE = {
|
||||
[PDP11.UNIBUS.PSW]: [null, null, DevicePDP11.prototype.readPSW, DevicePDP11.prototype.writePSW]
|
||||
};
|
||||
|
||||
/**
|
||||
* DevicePDP11.init()
|
||||
|
|
|
|||
Loading…
Reference in a new issue