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All but one attempted diagnostic test (EKBBF0 TEST 63) passes now

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This commit is contained in:
Jeff Parsons 2016-11-26 13:25:15 -08:00 • committed by Jeff Parsons
commit 559a7eb8fa
5 changed files with 101 additions and 111 deletions
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1
modules/pdp11/lib/cpuops.js
View file

@ -1739,6 +1739,7 @@ PDP11.opSPL = function(opCode)
if (!(this.regPSW & PDP11.PSW.CMODE)) {
this.regPSW = (this.regPSW & ~(PDP11.PSW.UNUSED | PDP11.PSW.PRI)) | ((opCode & 0x7) << PDP11.PSW.SHIFT.PRI);
this.opFlags |= PDP11.OPFLAG.IRQ_DELAY;
this.opFlags &= ~PDP11.OPFLAG.IRQ;
}
this.nStepCycles -= (4 + 1);
};

35
modules/pdp11/lib/cpustate.js
View file

@ -934,8 +934,8 @@ CPUStatePDP11.prototype.checkInterrupts = function()
}
else if (this.opFlags & PDP11.OPFLAG.IRQ_DELAY) {
/*
* We know that IRQ (bit 1) is clear, so since IRQ_DELAY (bit 0) is set, incrementing opFlags
* will transform IRQ_DELAY into IRQ, without affecting any other (higher) bits.
* We know that IRQ (bit 2) is clear, so since IRQ_DELAY (bit 0) is set, incrementing opFlags
* will eventually transform IRQ_DELAY into IRQ, without affecting any other (higher) bits.
*/
this.opFlags++;
}
@ -1098,20 +1098,12 @@ CPUStatePDP11.prototype.setPSW = function(newPSW)
this.regPSW = newPSW;
/*
* Trigger a call to checkInterrupts(), just in case.
*
* TODO: I think this is overdone; if you set a breakpoint on checkInterrupts(), you'll see that a significant
* percentage of calls do nothing. For example, you'll usually see a spurious checkInterrupts() immediately after
* an interrupt has been dispatched, because it's dispatched via trap(), and trap() calls setPSW().
*
* I mean, sure, it's POSSIBLE that the new PSW loaded by trap() actually set a lower priority, allowing a lower
* priority interrupt to immediately be acknowledged. But perhaps we should be a bit more rigorous here.
*
* For example, we could avoid setting IRQ unless 1) there's actually an active IRQ (ie, irqNext
* is not null) or 2) an optional fCheckInterrupts flag is passed to us, because the caller has some knowledge
* that priority could be changing. Just throwing out some ideas....
* Trigger a call to checkInterrupts(), just in case. If there's an active IRQ, then setting
* OPFLAG.IRQ is a no-brainer, but even if not, we set IRQ_DELAY in case the priority was lowered
* enough to permit a programmed interrupt (via regPIR).
*/
this.opFlags |= PDP11.OPFLAG.IRQ;
this.opFlags &= ~PDP11.OPFLAG.IRQ;
this.opFlags |= (this.irqNext? PDP11.OPFLAG.IRQ : PDP11.OPFLAG.IRQ_DELAY);
};
/**
@ -1161,10 +1153,7 @@ CPUStatePDP11.prototype.setPIR = function(newPIR)
do {
newPIR += PDP11.PIR.PIA_INC;
} while (bits >>= 1);
/*
* TODO: Which should we set: IRQ or IRQ_DELAY?
*/
this.opFlags |= PDP11.OPFLAG.IRQ;
this.opFlags |= PDP11.OPFLAG.IRQ_DELAY;
}
this.regPIR = newPIR;
};
@ -1431,13 +1420,13 @@ CPUStatePDP11.prototype.trap = function(vector, flag, reason)
* trick that the SPL instruction uses: setting IRQ_DELAY instead of IRQ, which effectively delays
* IRQ detection for one instruction, which is just long enough to allow the diagnostic to pass.
*/
this.opFlags &= ~(flag | PDP11.OPFLAG.TRAP_TF | PDP11.OPFLAG.IRQ);
this.opFlags |= PDP11.OPFLAG.IRQ_DELAY | PDP11.OPFLAG.TRAP;
this.opFlags &= ~(flag | PDP11.OPFLAG.TRAP_TF | PDP11.OPFLAG.IRQ_MASK);
this.opFlags |= PDP11.OPFLAG.IRQ_DELAY | PDP11.OPFLAG.TRAP_LAST;
this.trapPSW = -1; // reset flag that we have a trap within a trap
/*
* These next properties (in conjunction with setting PDP11.OPFLAG.TRAP) are purely an aid for the Debugger;
* These next properties (in conjunction with setting PDP11.OPFLAG.TRAP_LAST) are purely an aid for the Debugger;
* see getTrapStatus().
*/
this.trapVector = vector;
@ -1481,7 +1470,7 @@ CPUStatePDP11.prototype.trapReturn = function()
*/
CPUStatePDP11.prototype.getTrapStatus = function()
{
return (this.opFlags & PDP11.OPFLAG.TRAP)? (this.trapVector | this.trapReason << 8) : 0;
return (this.opFlags & PDP11.OPFLAG.TRAP_LAST)? (this.trapVector | this.trapReason << 8) : 0;
};
/**

22
modules/pdp11/lib/defines.js
View file

@ -261,17 +261,17 @@ var PDP11 = {
* Internal operation state flags
*/
OPFLAG: {
IRQ_DELAY: 0x01, // set IRQ on next check (set by SPL and traps)
IRQ: 0x02, // call checkInterrupts()
IRQ_MASK: 0x03,
WAIT: 0x04, // WAIT operation in progress
TRAP: 0x08, // set if last operation was a trap (see trapLast for the vector, and trapReason for the reason)
TRAP_TF: 0x10, // aka PDP11.PSW.TF (WARNING: do not change this bit, or you will likely break opRTI())
TRAP_SP: 0x20, // set for a deferred BUS trap (due to a "yellow" stack overflow condition)
TRAP_MMU: 0x40,
TRAP_MASK: 0x70,
NO_FLAGS: 0x80, // set whenever the PSW is written directly, requiring all updateXXXFlags() functions to leave flags unchanged
PRESERVE: 0x07 // OPFLAG bits to preserve prior to the next instruction
IRQ_DELAY: 0x0001, // incremented until it becomes IRQ (set by SPL and traps)
IRQ: 0x0002, // time to call checkInterrupts()
IRQ_MASK: 0x0003,
WAIT: 0x0008, // WAIT operation in progress
PRESERVE: 0x000F, // OPFLAG bits to preserve prior to the next instruction
TRAP_TF: 0x0010, // aka PDP11.PSW.TF (WARNING: do not change this bit, or you will likely break opRTI())
TRAP_SP: 0x0020, // set for a deferred BUS trap (due to a "yellow" stack overflow condition)
TRAP_MMU: 0x0040,
TRAP_MASK: 0x0070,
TRAP_LAST: 0x0080, // set if last operation was a trap (see trapLast for the vector, and trapReason for the reason)
NO_FLAGS: 0x0100 // set whenever the PSW is written directly, requiring all updateXXXFlags() functions to leave flags unchanged
},
/*
* Opcode reg (opcode bits 2-0)