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Fixed Debugger 16-bit register updates

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This commit is contained in:
Jeff Parsons 2016-04-22 07:48:13 -07:00
commit 5558a581d7
1 changed files with 24 additions and 22 deletions
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46
modules/pc8080/lib/debugger.js
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@ -4041,6 +4041,7 @@ if (DEBUGGER) {
return; return;
} }
var cpu = this.cpu;
if (fInstruction == null) fInstruction = true; if (fInstruction == null) fInstruction = true;
if (asArgs != null && asArgs.length > 1) { if (asArgs != null && asArgs.length > 1) {
@ -4058,6 +4059,7 @@ if (DEBUGGER) {
this.println("missing value for " + asArgs[1]); this.println("missing value for " + asArgs[1]);
return; return;
} }
var fValid = false; var fValid = false;
var w = this.parseExpression(sValue); var w = this.parseExpression(sValue);
@ -4069,62 +4071,62 @@ if (DEBUGGER) {
} }
switch (sRegMatch) { switch (sRegMatch) {
case "A": case "A":
this.cpu.regA = w & 0xff; cpu.regA = w & 0xff;
break; break;
case "B": case "B":
this.cpu.regB = w & 0xff; cpu.regB = w & 0xff;
break; break;
case "BC": case "BC":
this.cpu.regB = ((w << 8) & 0xff); cpu.regB = ((w >> 8) & 0xff);
/* falls through */ /* falls through */
case "C": case "C":
this.cpu.regC = w & 0xff; cpu.regC = w & 0xff;
break; break;
case "D": case "D":
this.cpu.regD = w & 0xff; cpu.regD = w & 0xff;
break; break;
case "DE": case "DE":
this.cpu.regD = ((w << 8) & 0xff); cpu.regD = ((w >> 8) & 0xff);
/* falls through */ /* falls through */
case "E": case "E":
this.cpu.regE = w & 0xff; cpu.regE = w & 0xff;
break; break;
case "H": case "H":
this.cpu.regH = w & 0xff; cpu.regH = w & 0xff;
break; break;
case "HL": case "HL":
this.cpu.regH = ((w << 8) & 0xff); cpu.regH = ((w >> 8) & 0xff);
/* falls through */ /* falls through */
case "L": case "L":
this.cpu.regL = w & 0xff; cpu.regL = w & 0xff;
break; break;
case "SP": case "SP":
this.cpu.setSP(w); cpu.setSP(w);
break; break;
case "PC": case "PC":
this.cpu.setPC(w); cpu.setPC(w);
this.dbgAddrNextCode = this.newAddr(this.cpu.getPC()); this.dbgAddrNextCode = this.newAddr(cpu.getPC());
break; break;
case "PS": case "PS":
this.cpu.setPS(w); cpu.setPS(w);
break; break;
case 'C': case 'C':
if (w) this.cpu.setCF(); else this.cpu.clearCF(); if (w) cpu.setCF(); else cpu.clearCF();
break; break;
case 'P': case 'P':
if (w) this.cpu.setPF(); else this.cpu.clearPF(); if (w) cpu.setPF(); else cpu.clearPF();
break; break;
case 'A': case 'A':
if (w) this.cpu.setAF(); else this.cpu.clearAF(); if (w) cpu.setAF(); else cpu.clearAF();
break; break;
case 'Z': case 'Z':
if (w) this.cpu.setZF(); else this.cpu.clearZF(); if (w) cpu.setZF(); else cpu.clearZF();
break; break;
case 'S': case 'S':
if (w) this.cpu.setSF(); else this.cpu.clearSF(); if (w) cpu.setSF(); else cpu.clearSF();
break; break;
case 'I': case 'I':
if (w) this.cpu.setIF(); else this.cpu.clearIF(); if (w) cpu.setIF(); else cpu.clearIF();
break; break;
default: default:
this.println("unknown register: " + sReg); this.println("unknown register: " + sReg);
@ -4135,14 +4137,14 @@ if (DEBUGGER) {
this.println("invalid value: " + sValue); this.println("invalid value: " + sValue);
return; return;
} }
this.cpu.updateCPU(); cpu.updateCPU();
this.println("updated registers:"); this.println("updated registers:");
} }
this.println(this.getRegDump()); this.println(this.getRegDump());
if (fInstruction) { if (fInstruction) {
this.dbgAddrNextCode = this.newAddr(this.cpu.getPC()); this.dbgAddrNextCode = this.newAddr(cpu.getPC());
this.doUnassemble(this.toHexAddr(this.dbgAddrNextCode)); this.doUnassemble(this.toHexAddr(this.dbgAddrNextCode));
} }
}; };