Fixed Debugger 16-bit register updates
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parent
8800ed5ef8
commit
5558a581d7
1 changed files with 24 additions and 22 deletions
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@ -4041,6 +4041,7 @@ if (DEBUGGER) {
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return;
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}
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var cpu = this.cpu;
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if (fInstruction == null) fInstruction = true;
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if (asArgs != null && asArgs.length > 1) {
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@ -4058,6 +4059,7 @@ if (DEBUGGER) {
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this.println("missing value for " + asArgs[1]);
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return;
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}
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var fValid = false;
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var w = this.parseExpression(sValue);
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@ -4069,62 +4071,62 @@ if (DEBUGGER) {
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}
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switch (sRegMatch) {
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case "A":
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this.cpu.regA = w & 0xff;
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cpu.regA = w & 0xff;
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break;
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case "B":
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this.cpu.regB = w & 0xff;
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cpu.regB = w & 0xff;
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break;
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case "BC":
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this.cpu.regB = ((w << 8) & 0xff);
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cpu.regB = ((w >> 8) & 0xff);
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/* falls through */
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case "C":
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this.cpu.regC = w & 0xff;
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cpu.regC = w & 0xff;
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break;
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case "D":
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this.cpu.regD = w & 0xff;
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cpu.regD = w & 0xff;
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break;
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case "DE":
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this.cpu.regD = ((w << 8) & 0xff);
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cpu.regD = ((w >> 8) & 0xff);
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/* falls through */
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case "E":
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this.cpu.regE = w & 0xff;
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cpu.regE = w & 0xff;
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break;
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case "H":
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this.cpu.regH = w & 0xff;
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cpu.regH = w & 0xff;
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break;
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case "HL":
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this.cpu.regH = ((w << 8) & 0xff);
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cpu.regH = ((w >> 8) & 0xff);
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/* falls through */
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case "L":
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this.cpu.regL = w & 0xff;
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cpu.regL = w & 0xff;
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break;
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case "SP":
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this.cpu.setSP(w);
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cpu.setSP(w);
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break;
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case "PC":
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this.cpu.setPC(w);
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this.dbgAddrNextCode = this.newAddr(this.cpu.getPC());
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cpu.setPC(w);
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this.dbgAddrNextCode = this.newAddr(cpu.getPC());
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break;
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case "PS":
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this.cpu.setPS(w);
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cpu.setPS(w);
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break;
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case 'C':
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if (w) this.cpu.setCF(); else this.cpu.clearCF();
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if (w) cpu.setCF(); else cpu.clearCF();
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break;
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case 'P':
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if (w) this.cpu.setPF(); else this.cpu.clearPF();
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if (w) cpu.setPF(); else cpu.clearPF();
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break;
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case 'A':
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if (w) this.cpu.setAF(); else this.cpu.clearAF();
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if (w) cpu.setAF(); else cpu.clearAF();
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break;
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case 'Z':
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if (w) this.cpu.setZF(); else this.cpu.clearZF();
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if (w) cpu.setZF(); else cpu.clearZF();
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break;
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case 'S':
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if (w) this.cpu.setSF(); else this.cpu.clearSF();
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if (w) cpu.setSF(); else cpu.clearSF();
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break;
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case 'I':
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if (w) this.cpu.setIF(); else this.cpu.clearIF();
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if (w) cpu.setIF(); else cpu.clearIF();
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break;
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default:
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this.println("unknown register: " + sReg);
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@ -4135,14 +4137,14 @@ if (DEBUGGER) {
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this.println("invalid value: " + sValue);
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return;
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}
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this.cpu.updateCPU();
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cpu.updateCPU();
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this.println("updated registers:");
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}
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this.println(this.getRegDump());
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if (fInstruction) {
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this.dbgAddrNextCode = this.newAddr(this.cpu.getPC());
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this.dbgAddrNextCode = this.newAddr(cpu.getPC());
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this.doUnassemble(this.toHexAddr(this.dbgAddrNextCode));
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}
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};
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