Begin differentiating 286 and 386 descriptors
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parent
210423d577
commit
545c290785
4 changed files with 124 additions and 100 deletions
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@ -554,7 +554,7 @@ X86Seg.prototype.loadDesc8 = function(addrDesc, sel, fSuppress)
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}
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fGate = false;
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}
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else if (type == X86.DESC.ACC.TYPE.TSS) {
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else if (type == X86.DESC.ACC.TYPE.TSS286) {
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if (!this.switchTSS(sel, fCall)) {
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base = addrDesc = X86.ADDR_INVALID;
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break;
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@ -567,13 +567,13 @@ X86Seg.prototype.loadDesc8 = function(addrDesc, sel, fSuppress)
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nFaultError = sel;
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if (rpl < this.cpl) rpl = this.cpl; // set RPL to max(RPL,CPL) for call gates
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}
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else if (type == X86.DESC.ACC.TYPE.GATE_INT) {
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else if (type == X86.DESC.ACC.TYPE.GATE286_INT) {
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fGate = true;
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regPSMask = ~(X86.PS.NT | X86.PS.TF | X86.PS.IF);
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nFaultError = sel | X86.ERRCODE.EXT;
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cpu.assert(!(acc & 0x1f));
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}
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else if (type == X86.DESC.ACC.TYPE.GATE_TRAP) {
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else if (type == X86.DESC.ACC.TYPE.GATE286_TRAP) {
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fGate = true;
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regPSMask = ~(X86.PS.NT | X86.PS.TF);
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nFaultError = sel | X86.ERRCODE.EXT;
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@ -618,7 +618,7 @@ X86Seg.prototype.loadDesc8 = function(addrDesc, sel, fSuppress)
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regSP += 2;
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}
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addrTSS = cpu.segTSS.base;
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offSP = (this.cpl << 2) + X86.TSS.CPL0_SP;
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offSP = (this.cpl << 2) + X86.TSS286.CPL0_SP;
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offSS = offSP + 2;
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regSSPrev = cpu.getSS();
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regSPPrev = cpu.getSP();
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@ -692,7 +692,7 @@ X86Seg.prototype.loadDesc8 = function(addrDesc, sel, fSuppress)
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}
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}
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else if (this.id == X86Seg.ID.TSS) {
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if (!selMasked || type != X86.DESC.ACC.TYPE.TSS && type != X86.DESC.ACC.TYPE.TSS_BUSY) {
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if (!selMasked || type != X86.DESC.ACC.TYPE.TSS286 && type != X86.DESC.ACC.TYPE.TSS286_BUSY) {
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if (!fSuppress) X86.fnFault.call(cpu, X86.EXCEPTION.TS_FAULT, sel, true);
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base = addrDesc = X86.ADDR_INVALID;
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break;
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@ -702,7 +702,7 @@ X86Seg.prototype.loadDesc8 = function(addrDesc, sel, fSuppress)
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/*
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* For LSL, we must support any descriptor marked X86.DESC.ACC.TYPE.SEG, as well as TSS and LDT descriptors.
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*/
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if (!(type & X86.DESC.ACC.TYPE.SEG) && type > X86.DESC.ACC.TYPE.TSS_BUSY) {
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if (!(type & X86.DESC.ACC.TYPE.SEG) && type > X86.DESC.ACC.TYPE.TSS286_BUSY) {
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base = addrDesc = X86.ADDR_INVALID;
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break;
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}
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@ -761,11 +761,11 @@ X86Seg.prototype.switchTSS = function switchTSS(selNew, fNest)
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/*
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* TODO: Verify that it is (always) correct to require that the BUSY bit be currently set.
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*/
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if (cpu.segTSS.type != X86.DESC.ACC.TYPE.TSS_BUSY) {
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if (cpu.segTSS.type != X86.DESC.ACC.TYPE.TSS286_BUSY) {
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X86.fnFault.call(cpu, X86.EXCEPTION.TS_FAULT, selNew, true);
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return false;
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}
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cpu.setShort(cpu.segTSS.addrDesc + X86.DESC.ACC.OFFSET, (cpu.segTSS.acc & ~X86.DESC.ACC.TYPE.TSS_BUSY) | X86.DESC.ACC.TYPE.TSS);
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cpu.setShort(cpu.segTSS.addrDesc + X86.DESC.ACC.OFFSET, (cpu.segTSS.acc & ~X86.DESC.ACC.TYPE.TSS286_BUSY) | X86.DESC.ACC.TYPE.TSS286);
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}
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if (cpu.segTSS.load(selNew) === X86.ADDR_INVALID) {
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@ -777,66 +777,66 @@ X86Seg.prototype.switchTSS = function switchTSS(selNew, fNest)
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this.dbg.message((fNest? "Task switch" : "Task return") + ": TR " + str.toHexWord(selOld) + " (%" + str.toHex(addrOld, 6) + "), new TR " + str.toHexWord(selNew) + " (%" + str.toHex(addrNew, 6) + ")");
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}
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if (fNest === false) {
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if (cpu.segTSS.type != X86.DESC.ACC.TYPE.TSS_BUSY) {
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if (cpu.segTSS.type != X86.DESC.ACC.TYPE.TSS286_BUSY) {
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X86.fnFault.call(cpu, X86.EXCEPTION.GP_FAULT, selNew, true);
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return false;
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}
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} else {
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if (cpu.segTSS.type == X86.DESC.ACC.TYPE.TSS_BUSY) {
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if (cpu.segTSS.type == X86.DESC.ACC.TYPE.TSS286_BUSY) {
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X86.fnFault.call(cpu, X86.EXCEPTION.GP_FAULT, selNew, true);
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return false;
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}
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cpu.setShort(cpu.segTSS.addrDesc + X86.DESC.ACC.OFFSET, cpu.segTSS.acc |= X86.DESC.ACC.TYPE.TSS_BUSY);
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cpu.segTSS.type = X86.DESC.ACC.TYPE.TSS_BUSY;
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cpu.setShort(cpu.segTSS.addrDesc + X86.DESC.ACC.OFFSET, cpu.segTSS.acc |= X86.DESC.ACC.TYPE.TSS286_BUSY);
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cpu.segTSS.type = X86.DESC.ACC.TYPE.TSS286_BUSY;
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}
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/*
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* Update the old TSS
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*/
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cpu.setShort(addrOld + X86.TSS.TASK_IP, cpu.getIP());
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cpu.setShort(addrOld + X86.TSS.TASK_PS, cpu.getPS());
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cpu.setShort(addrOld + X86.TSS.TASK_AX, cpu.regEAX);
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cpu.setShort(addrOld + X86.TSS.TASK_CX, cpu.regECX);
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cpu.setShort(addrOld + X86.TSS.TASK_DX, cpu.regEDX);
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cpu.setShort(addrOld + X86.TSS.TASK_BX, cpu.regEBX);
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cpu.setShort(addrOld + X86.TSS.TASK_SP, cpu.getSP());
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cpu.setShort(addrOld + X86.TSS.TASK_BP, cpu.regEBP);
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cpu.setShort(addrOld + X86.TSS.TASK_SI, cpu.regESI);
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cpu.setShort(addrOld + X86.TSS.TASK_DI, cpu.regEDI);
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cpu.setShort(addrOld + X86.TSS.TASK_ES, cpu.segES.sel);
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cpu.setShort(addrOld + X86.TSS.TASK_CS, cpu.segCS.sel);
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cpu.setShort(addrOld + X86.TSS.TASK_SS, cpu.segSS.sel);
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cpu.setShort(addrOld + X86.TSS.TASK_DS, cpu.segDS.sel);
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cpu.setShort(addrOld + X86.TSS286.TASK_IP, cpu.getIP());
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cpu.setShort(addrOld + X86.TSS286.TASK_PS, cpu.getPS());
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cpu.setShort(addrOld + X86.TSS286.TASK_AX, cpu.regEAX);
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cpu.setShort(addrOld + X86.TSS286.TASK_CX, cpu.regECX);
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cpu.setShort(addrOld + X86.TSS286.TASK_DX, cpu.regEDX);
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cpu.setShort(addrOld + X86.TSS286.TASK_BX, cpu.regEBX);
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cpu.setShort(addrOld + X86.TSS286.TASK_SP, cpu.getSP());
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cpu.setShort(addrOld + X86.TSS286.TASK_BP, cpu.regEBP);
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cpu.setShort(addrOld + X86.TSS286.TASK_SI, cpu.regESI);
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cpu.setShort(addrOld + X86.TSS286.TASK_DI, cpu.regEDI);
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cpu.setShort(addrOld + X86.TSS286.TASK_ES, cpu.segES.sel);
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cpu.setShort(addrOld + X86.TSS286.TASK_CS, cpu.segCS.sel);
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cpu.setShort(addrOld + X86.TSS286.TASK_SS, cpu.segSS.sel);
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cpu.setShort(addrOld + X86.TSS286.TASK_DS, cpu.segDS.sel);
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/*
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* Reload all registers from the new TSS; it's important to reload the LDTR sooner
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* rather than later, so that as segment registers are reloaded, any LDT selectors will
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* will be located in the correct table.
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*/
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cpu.segLDT.load(cpu.getShort(addrNew + X86.TSS.TASK_LDT));
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cpu.setPS(cpu.getShort(addrNew + X86.TSS.TASK_PS) | (fNest? X86.PS.NT : 0));
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cpu.segLDT.load(cpu.getShort(addrNew + X86.TSS286.TASK_LDT));
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cpu.setPS(cpu.getShort(addrNew + X86.TSS286.TASK_PS) | (fNest? X86.PS.NT : 0));
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cpu.assert(!fNest || !!(cpu.regPS & X86.PS.NT));
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cpu.regEAX = cpu.getShort(addrNew + X86.TSS.TASK_AX);
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cpu.regECX = cpu.getShort(addrNew + X86.TSS.TASK_CX);
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cpu.regEDX = cpu.getShort(addrNew + X86.TSS.TASK_DX);
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cpu.regEBX = cpu.getShort(addrNew + X86.TSS.TASK_BX);
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cpu.regEBP = cpu.getShort(addrNew + X86.TSS.TASK_BP);
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cpu.regESI = cpu.getShort(addrNew + X86.TSS.TASK_SI);
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cpu.regEDI = cpu.getShort(addrNew + X86.TSS.TASK_DI);
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cpu.segES.load(cpu.getShort(addrNew + X86.TSS.TASK_ES));
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cpu.segDS.load(cpu.getShort(addrNew + X86.TSS.TASK_DS));
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cpu.setCSIP(cpu.getShort(addrNew + X86.TSS.TASK_IP), cpu.getShort(addrNew + X86.TSS.TASK_CS));
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cpu.regEAX = cpu.getShort(addrNew + X86.TSS286.TASK_AX);
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cpu.regECX = cpu.getShort(addrNew + X86.TSS286.TASK_CX);
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cpu.regEDX = cpu.getShort(addrNew + X86.TSS286.TASK_DX);
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cpu.regEBX = cpu.getShort(addrNew + X86.TSS286.TASK_BX);
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cpu.regEBP = cpu.getShort(addrNew + X86.TSS286.TASK_BP);
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cpu.regESI = cpu.getShort(addrNew + X86.TSS286.TASK_SI);
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cpu.regEDI = cpu.getShort(addrNew + X86.TSS286.TASK_DI);
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cpu.segES.load(cpu.getShort(addrNew + X86.TSS286.TASK_ES));
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cpu.segDS.load(cpu.getShort(addrNew + X86.TSS286.TASK_DS));
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cpu.setCSIP(cpu.getShort(addrNew + X86.TSS286.TASK_IP), cpu.getShort(addrNew + X86.TSS286.TASK_CS));
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var offSS = X86.TSS.TASK_SS;
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var offSP = X86.TSS.TASK_SP;
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var offSS = X86.TSS286.TASK_SS;
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var offSP = X86.TSS286.TASK_SP;
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if (this.cpl < cplOld) {
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offSP = (this.cpl << 2) + X86.TSS.CPL0_SP;
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offSP = (this.cpl << 2) + X86.TSS286.CPL0_SP;
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offSS = offSP + 2;
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}
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cpu.setSS(cpu.getShort(addrNew + offSS), true);
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cpu.setSP(cpu.getShort(addrNew + offSP));
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if (fNest) cpu.setShort(addrNew + X86.TSS.PREV_TSS, selOld);
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if (fNest) cpu.setShort(addrNew + X86.TSS286.PREV_TSS, selOld);
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cpu.regCR0 |= X86.CR0.MSW.TS;
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return true;
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