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Version bump, assorted CPU documentation tweaks, and more machine redirects

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Jeff Parsons 2016-01-29 14:32:54 -08:00
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4
pubs/pc/reference/intel/80286/README.md
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@ -9,7 +9,7 @@ Intel 80286 CPU Information
### 80286 Errata
* [Early 80286 Errata of Interest](early_errata/#early-80286-errata-of-interest)
* [Early Errata: A1 and B1 Steppings](early_errata/)
* [ARPL Behavior](arpl/)
* [Coprocessor Operand Beyond Segment Limit](b2_b3_info/#coprocessor-operand-partially-beyond-limit-of-erc-segment)
* [Instructions Longer than 10 Bytes](extra_prefixes/)
@ -28,7 +28,7 @@ Intel 80286 CPU Information
* [Discrepancies from an iAPX 86/88 Using Emulation](real_mode/#discrepancies-from-an-iapx-86-88-using-emulation)
* [Extending the Address Space of Current iAPX 86 Software](real_mode/#extending-the-address-space-of-current-iapx-86-software)
* [Mixing Real Mode and Protected Mode](real_mode/#mixing-real-mode-and-protected-mode)
* [Exceptions from Undefined Opcodes and String Instructions](early_errata/)
* [Exceptions from Undefined Opcodes and String Instructions](exceptions/)
### Assorted Publications

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@ -17,3 +17,5 @@ but will be described in future revisions of the "iAPX286 Programmer's Reference
This functionality of the ARPL is not believed not to be a problem, and there are no plans to change this functionality
of the ARPL instruction.
[Return to [Intel 80286 CPU Information](/pubs/pc/reference/intel/80286/)]

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@ -199,3 +199,5 @@ handled if the 80286 interrupts are always disabled before programming the inter
is performed no unmasked interrupt is active. The interrupt handler for IR7 can read ISR7 of the 8259A to tell if this was a real
interrupt on IR7. The ISR7 bit will be 0 if at the time the interrupt was acknowledged, no unmasked IR inputs of the 8259A were
active ("phantom" interrupt).
[Return to [Intel 80286 CPU Information](/pubs/pc/reference/intel/80286/)]

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@ -1,82 +1,14 @@
---
layout: page
title: "Intel 80286 CPU Errata: Early Problems"
title: "Intel 80286 CPU Errata: A1 and B1 Steppings"
permalink: /pubs/pc/reference/intel/80286/early_errata/
---
Intel 80286 CPU Errata: Early Problems
Intel 80286 CPU Errata: A1 and B1 Steppings
---
[The following information is from an undated 15-page Intel document titled "Undocumented iAPX 286 Test Instruction".
NOTE: The initial reference to LOADALL as "opcode 0F04H" and the subsequent references to the "0F05H opcode" are exactly
as they appear in the original document. Whether or not they were mistakes is unknown.]
### Exceptions from Undefined Opcodes and String Instructions
The exception 13 handler will probably use a lookup table for the opcode byte of the instruction causing exception
13 to determine the correct action for this instruction. In general, any undefined opcode causes exception 6 and
would therefore not invoke exception 13. However, some implementations may emulate some instructions. The following
explains the empty entries in the opcode map to aid in determining an emulation strategy.
The following is a list of exclusions from the general rule of undefined 80286 opcodes causing exception 6.
* The [LOADALL](../loadall/) instruction (opcode 0F04H) will cause exception 13 in protected mode if executed when
CPL is not 0. [LOADALL](../loadall/) may be executed at any time in real address mode.
* The 0F05H opcode will cause exception 13 in protected mode if executed when CPL is not 0. If 0F05H is executed
in real address mode, or in protected mode when CPL=O, the 80286 stops normal execution. RESET must be used to
restart the CPU in this case. The 0F05H opcode may be executed at any time in real address mode.
* The opcode 82H is an alias for opcode 80H.
* The 0D0H/0D1H opcode with a REG field = 6 is an alias for the SHL instruction (REG = 7).
* The opcode 0D6H is a proprietary single byte instruction. No restrictions apply to its execution.
It can be emulated as a NOP.
* The 0F1H opcode is a prefix which performs no function. It counts like any other prefix towards the maximum
instruction length. No restrictions apply to its execution.
* The 0F6H/0F7H opcode with a REG field = 1 is an alias for the TEST instruction (REG=0).
Restarting string instructions which caused exception 12 (if SS override was used) or exception 13 requires updating
SI, DI, and CX (if repeat was used). Which registers are updated depends on the instruction and when the exception was
detected. The following rules apply:
* For STOS, the DI register must always be updated by the exception handler to restart tne instruction.
The state of the DF bit in the flag word and the operand size determines whether to use +2, +1, -1, or -2 to
update DI. If a repeated STOS was used, add 2 to CX to restart the instruction.
* For INS, the DI register must always be updated by the exception handler to restart the instruction. The state
of the DF bit in the flag word and the operand size determines whether to use +2, +1, -1, or -2 to update DI.
If a repeated INS was used, increment CX to restart the instruction. If exception 13 was not caused by an invalid
IOPL during the first I/O read, then increment CX again if INS was repeated.
* For SCAS, the SI register must always be updated by the exception handler to restart the instruction.
The state of the DF bit in the flag word and the operand size determines whether to use +2, +1, -1, or -2 to
update SI. If SCAS was repeated, add 2 to CX to restart it.
* For OUTS, the SI register must always be updated by the exception handler to restart the instruction. The state
of the DF bit in the flag word and the operand size determines whether to use +2, +1, -1, or -2 to update SI.
If OUTS was repeated, add 2 to CX to restart it. Note that exception 13 may have been caused by an insufficient IOPL.
* For MOVS, the SI register must always be updated by the exception handler to restart the instruction. The state
of the DF bit in the flag word and the operand size determines whether to use +2, +1, -1, or -2 to update SI.
The DI register must also be updated if the source operand (i.e. DS:SI or seg:SI if a segment override prefix was
used) did not cause the exception. After updating SI, look at the source operand address to see if exception 13
would occur. If not, then DI must also be updated the same as SI. Always increment CX to restart MOVS if it was
repeated. IF DI was updated and a repeat prefix was used, then CX must be incremented again for correct instruction
restart.
* For CMPS, the DI register must always be updated by the exception handler to restart the instruction. The state
of the DF bit in the flag word and the operand size determines whether to use +2, +1, -1, or -2 to update DI.
The SI register must also be updated if the ES:DI operand did not cause the exception. After updating DI, look at
ES:DI to see if exception 13 would occur. If not, then SI must also be updated the same as DI. Increment CX if
CMPS was repeated to restart it. IF SI was updated and a repeat prefix was used, then CX must be incremented for
correct instruction restart.
Early 80286 Errata of Interest
---
[The following information is from an undated 15-page Intel document titled "Undocumented iAPX 286 Test Instruction",
p. 15]
Early versions of the 80286 have several errata items which may effect the implementation of software to emulate an
8086/8088 on a protected mode 80286 or expansion of the address space in real mode. These errata are in the A1 and B1
@ -100,8 +32,11 @@ steppings of the 80286 and are fixed in later steppings of the 80286.
instruction. The SI and DI register values will reflect the iterations used by the instruction. Later steppings
of the 80286 will assure the saved value of the CX register reflects the number of iterations performed.
* The [LOADALL](../loadall/) instruction may incorrectly enter protected mode. This only affects systems that use [LOADALL](../loadall/) while
in real mode and want to remain in real mode. Two possible workarounds are possible: execute [LOADALL](../loadall/) using
0-wait memory for the data values or be sure bit 0 of memory location 804H is zero. HOLD requests and processor
extension data transfers should be inhibited while [LOADALL](../loadall/) is running. Later steppings of the 80286 will correctly
load the MSW during [LOADALL](../loadall/) with HOLD and processor extension transfers.
* The [LOADALL](../loadall/) instruction may incorrectly enter protected mode. This only affects systems that use
[LOADALL](../loadall/) while in real mode and want to remain in real mode. Two possible workarounds are possible:
execute [LOADALL](../loadall/) using 0-wait memory for the data values or be sure bit 0 of memory location 804H is
zero. HOLD requests and processor extension data transfers should be inhibited while [LOADALL](../loadall/) is running.
Later steppings of the 80286 will correctly load the MSW during [LOADALL](../loadall/) with HOLD and processor
extension transfers.
[Return to [Intel 80286 CPU Information](/pubs/pc/reference/intel/80286/)]

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@ -0,0 +1,76 @@
---
layout: page
title: "Intel 80286 CPU: Exceptions"
permalink: /pubs/pc/reference/intel/80286/exceptions/
---
Intel 80286 CPU: Exceptions from Undefined Opcodes and String Instructions
---
[The following information is from an undated 15-page Intel document titled "Undocumented iAPX 286 Test Instruction", pp. 13-14.
NOTE: The initial reference to LOADALL as "opcode 0F04H" and the subsequent references to the "0F05H opcode" are exactly
as they appear in the original document. Whether or not they were mistakes is unknown.]
The exception 13 handler will probably use a lookup table for the opcode byte of the instruction causing exception
13 to determine the correct action for this instruction. In general, any undefined opcode causes exception 6 and
would therefore not invoke exception 13. However, some implementations may emulate some instructions. The following
explains the empty entries in the opcode map to aid in determining an emulation strategy.
The following is a list of exclusions from the general rule of undefined 80286 opcodes causing exception 6.
* The [LOADALL](../loadall/) instruction (opcode 0F04H) will cause exception 13 in protected mode if executed when
CPL is not 0. [LOADALL](../loadall/) may be executed at any time in real address mode.
* The 0F05H opcode will cause exception 13 in protected mode if executed when CPL is not 0. If 0F05H is executed
in real address mode, or in protected mode when CPL=O, the 80286 stops normal execution. RESET must be used to
restart the CPU in this case. The 0F05H opcode may be executed at any time in real address mode.
* The opcode 82H is an alias for opcode 80H.
* The 0D0H/0D1H opcode with a REG field = 6 is an alias for the SHL instruction (REG = 7).
* The opcode 0D6H is a proprietary single byte instruction. No restrictions apply to its execution.
It can be emulated as a NOP.
* The 0F1H opcode is a prefix which performs no function. It counts like any other prefix towards the maximum
instruction length. No restrictions apply to its execution.
* The 0F6H/0F7H opcode with a REG field = 1 is an alias for the TEST instruction (REG=0).
Restarting string instructions which caused exception 12 (if SS override was used) or exception 13 requires updating
SI, DI, and CX (if repeat was used). Which registers are updated depends on the instruction and when the exception was
detected. The following rules apply:
* For STOS, the DI register must always be updated by the exception handler to restart tne instruction.
The state of the DF bit in the flag word and the operand size determines whether to use +2, +1, -1, or -2 to
update DI. If a repeated STOS was used, add 2 to CX to restart the instruction.
* For INS, the DI register must always be updated by the exception handler to restart the instruction. The state
of the DF bit in the flag word and the operand size determines whether to use +2, +1, -1, or -2 to update DI.
If a repeated INS was used, increment CX to restart the instruction. If exception 13 was not caused by an invalid
IOPL during the first I/O read, then increment CX again if INS was repeated.
* For SCAS, the SI register must always be updated by the exception handler to restart the instruction.
The state of the DF bit in the flag word and the operand size determines whether to use +2, +1, -1, or -2 to
update SI. If SCAS was repeated, add 2 to CX to restart it.
* For OUTS, the SI register must always be updated by the exception handler to restart the instruction. The state
of the DF bit in the flag word and the operand size determines whether to use +2, +1, -1, or -2 to update SI.
If OUTS was repeated, add 2 to CX to restart it. Note that exception 13 may have been caused by an insufficient IOPL.
* For MOVS, the SI register must always be updated by the exception handler to restart the instruction. The state
of the DF bit in the flag word and the operand size determines whether to use +2, +1, -1, or -2 to update SI.
The DI register must also be updated if the source operand (i.e. DS:SI or seg:SI if a segment override prefix was
used) did not cause the exception. After updating SI, look at the source operand address to see if exception 13
would occur. If not, then DI must also be updated the same as SI. Always increment CX to restart MOVS if it was
repeated. IF DI was updated and a repeat prefix was used, then CX must be incremented again for correct instruction
restart.
* For CMPS, the DI register must always be updated by the exception handler to restart the instruction. The state
of the DF bit in the flag word and the operand size determines whether to use +2, +1, -1, or -2 to update DI.
The SI register must also be updated if the ES:DI operand did not cause the exception. After updating DI, look at
ES:DI to see if exception 13 would occur. If not, then SI must also be updated the same as DI. Increment CX if
CMPS was repeated to restart it. IF SI was updated and a repeat prefix was used, then CX must be incremented for
correct instruction restart.
[Return to [Intel 80286 CPU Information](/pubs/pc/reference/intel/80286/)]

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@ -18,3 +18,5 @@ greater than ten bytes can occur is by using the assembler to intentionally plac
There are no plans to change this functionality of the 80286 and future editions of the "iAPX286 Programmer's Reference
Manual" and 80286 datasheet will accurately describe how 80286 reacts to instructions greater than 10 bytes in length.
[Return to [Intel 80286 CPU Information](/pubs/pc/reference/intel/80286/)]

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@ -1,13 +1,14 @@
---
layout: page
title: "Intel 80286 LOADALL Instruction"
title: "Intel 80286 CPU: LOADALL"
permalink: /pubs/pc/reference/intel/80286/loadall/
---
Intel 80286 LOADALL Instruction
Intel 80286 CPU: LOADALL
---
[The following information is from an undated 15-page Intel document titled "Undocumented iAPX 286 Test Instruction"]
[The following information is from an undated 15-page Intel document titled "Undocumented iAPX 286 Test Instruction",
pp. 1-4]
### LOADALL (0F05H)
@ -61,34 +62,34 @@ requires 190 clocks with no wait states.
### LOADALL Memory Area Format ###
Physical Address (Hex) Associated CPU Register
800-805 None
806-807 MSW
808-815 None
816-817 TR
818-819 Flag word
81A-81B IP
81C-81D LDT
81E-81F DS
820-821 SS
822-823 CS
824-825 ES
826-827 DI
828-829 SI
82A-82B BP
82C-82D SP
82E-82F BX
830-831 DX
832-833 CX
834-835 AX
836-83B ES descriptor cache
83C-841 CS descriptor cache
842-847 SS descriptor cache
848-84D DS descriptor cache
84E-853 GDTR
854-859 LDT descriptor cache
85A-85F IDTR
860-865 TSS descriptor cache
Physical Address (Hex) Associated CPU Register
800-805 None
806-807 MSW
808-815 None
816-817 TR
818-819 Flag word
81A-81B IP
81C-81D LDT
81E-81F DS
820-821 SS
822-823 CS
824-825 ES
826-827 DI
828-829 SI
82A-82B BP
82C-82D SP
82E-82F BX
830-831 DX
832-833 CX
834-835 AX
836-83B ES descriptor cache
83C-841 CS descriptor cache
842-847 SS descriptor cache
848-84D DS descriptor cache
84E-853 GDTR
854-859 LDT descriptor cache
85A-85F IDTR
860-865 TSS descriptor cache
No checks are made between the program visible selector values and the associated descriptor table entry.
LOADALL does not perform any descriptor table accesses. No checks are made regarding the type or access rights
@ -156,3 +157,5 @@ For proper protected mode operation, the following is required:
4. The DPL fields of the ES and DS descriptors should be 3 to prevent their being zeroed by RET or IRET
instructions.
[Return to [Intel 80286 CPU Information](/pubs/pc/reference/intel/80286/)]

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@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<?xml-stylesheet type="text/xsl" href="/versions/pcjs/1.20.7/manifest.xsl"?>
<?xml-stylesheet type="text/xsl" href="/versions/pcjs/1.20.8/manifest.xsl"?>
<manifest type="document">
<title>Intel 80286 References</title>
<document href="https://archive.org/download/bitsavers_intel80286287ProgrammersReferenceManual1987_27505703/210498-005_80286_and_80287_Programmers_Reference_Manual_1987.pdf">

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@ -1,13 +1,14 @@
---
layout: page
title: "Intel 80286 CPU Documentation: Real Mode"
title: "Intel 80286 CPU: Real Mode Emulation"
permalink: /pubs/pc/reference/intel/80286/real_mode/
---
Intel 80286 CPU Documentation: Real Mode
Intel 80286 CPU: Real Mode Emulation
---
[The following information is from an undated 15-page Intel document titled "Undocumented iAPX 286 Test Instruction"]
[The following information is from an undated 15-page Intel document titled "Undocumented iAPX 286 Test Instruction",
pp. 4-12]
### Executing Real Mode Programs in Protected Mode
@ -16,7 +17,7 @@ it and other programs. All segment register semantics of iAPX 86 real mode can b
of the real mode program can also be limited to less than 1 megabyte and be relocated anywhere in the 16 Megabyte
physical address space. The following sections describe several aspects of this emulation.
### Address space relocation and control ###
#### Address space relocation and control ####
iAPX 86 real mode emulation requires any segment register load instruction cause a protection exception.
An error code with bits 1-0 being zero and bits 15-2 being non-zero identify a segment register load exception.
@ -38,9 +39,9 @@ error code of 0. No memory reference will occur. This case can be identified by
contain a value of 0-3. These exceptions are also restartable.
Limits can be enforced on the size of the emulated iAPX 86 address space. An iAPX 86 paragraph ID that is outside
the defined memory area can be loaded, but the segment register can be marked invalid for memory addressing. [LOADALL](../loadall/)
can be used to load the iAPX 86 paragraph ID into the segment register, but the descriptor cache entry is marked
invalid. The paragraph ID can still be read without causing a protection exception.
the defined memory area can be loaded, but the segment register can be marked invalid for memory addressing.
[LOADALL](../loadall/) can be used to load the iAPX 86 paragraph ID into the segment register, but the descriptor
cache entry is marked invalid. The paragraph ID can still be read without causing a protection exception.
If a selector value is loaded whose segment overruns the end of the defined physical memory area, the limit field
can be set less than 65535 to prevent accesses outside the defined memory area with that segment register.
@ -49,7 +50,7 @@ The emulated iAPX 86/88 address space can be relocated anywhere in the 16 Mbyte
adding a 24-bit relocation factor to the 20-bit iAPX 86/88 physical address value associated with the iAPX 86
paragraph ID.
### iAPX 86/88 Interrupt Table Simulation ###
#### iAPX 86/88 Interrupt Table Simulation ####
The [LOADALL](../loadall/) instruction allows a protected mode 80286 to provide a simulated iAPX 86/88 interrupt
table to iAPX 86/88 programs. The protected mode iAPX 286 interrupt table is different from iAPX 86/88 since it must
@ -69,13 +70,13 @@ Interrupt handlers for external interrupts can pass control to an iAPX 86 real m
interrupt handler for an iAPX 86 interrupt must determine if the interrupt is for a real mode program; if so,
then it emulates a real mode interrupt the same way as for the INT instruction.
### Allowing writes into a code segment ###
#### Allowing writes into a code segment ####
Code segment writes are possible by using writable data segment descriptors for the CS cache entry.
Normally the code segment is write protected. If the code segment descriptor is always marked writable,
then writes using the CS prefix will work correctly.
### Allowing temporaries to be placed into segment registers ###
#### Allowing temporaries to be placed into segment registers ####
A temporary value which does not correspond to a valid segment causes exception 13. It is possible to place
that value into the program visible segment register, but mark the descriptor cache entry invalid. The invalid
@ -84,10 +85,10 @@ but prevents any memory reference instruction from using the segment register to
This feature requires an error handler to know that exception 13 with an error code which is an invalid segment
selector value indicates a potential temporary value problem. The exception handler must simulate the segment load
instruction to place the error code into the appropriate segment register and use [LOADALL](../loadall/) to mark the descriptor
cache entry invalid. The program may then be resumed after the segment load instruction.
instruction to place the error code into the appropriate segment register and use [LOADALL](../loadall/) to mark the
descriptor cache entry invalid. The program may then be resumed after the segment load instruction.
### Simulating I/O ###
#### Simulating I/O ####
All I/O instructions of the iAPX 86 program can be simulated. When the IOPL (I/O privilege level) is less than
the CPL of the simulated iAPX 86 program, exception 13 will occur, with an error code of 0, on IN, OUT, STI, CLI,
@ -98,7 +99,7 @@ The LOCK instruction prefix causes exception 13 when CPL is greater than IOPL. F
could be ignored. Restarting the program after the LOCK prefix would be acceptable. In special cases, the LOCKED
instruction may need to be run with a lower CPL.
### Mixing emulated real mode software with native protected mode software ###
#### Mixing emulated real mode software with native protected mode software ####
A system which emulates a real mode program may also run protected mode software. If the GDT and IDT has all
entries marked level 2 or less, the emulated program cannot use them if it runs at level 3. The emulated program
@ -114,8 +115,8 @@ reloaded with protected selectors without a protection exception. Interrupting f
does not affect interrupt latency.
Returning from an interrupt requires some checks. The return from the interrupt handler must check whether an
iAPX 86 real mode program had been executing. If so, the return sequence must use the [LOADALL](../loadall/) instruction to reload
all the registers rather than the normal IRET instruction.
iAPX 86 real mode program had been executing. If so, the return sequence must use the [LOADALL](../loadall/)
instruction to reload all the registers rather than the normal IRET instruction.
Depending on the iAPX 86 paragraph IDs used, the IRET instruction might not cause a protection exception on
returning to an emulated iAPX 86 program. The CS value of an interrupted iAPX 86 program saved on the stack or
@ -127,7 +128,7 @@ code segment at an incorrect address.
The interrupt handler should test whether an emulated iAPX 86 program was executing. An interrupted protected mode
program can be restarted in the normal manner while an emulated program requires [LOADALL](../loadall/).
### Emulating an 8087 with the 80287 ###
#### Emulating an 8087 with the 80287 ####
The instruction and data addresses saved in the protected mode 80287 environment area are in a different format
than from the 8087. In real mode, the 80287 environment is in the same format as the 8087. In protected mode,
@ -252,9 +253,9 @@ Extending the Address Space of Current iAPX 86 Software
---
Current iAPX 86 real mode programs can use the extended address space of the iAPX 286 in a limited manner.
To address the extended memory, [LOADALL](../loadall/) must be used to load the descriptor cache with an base address beyond
the normal 1 Mbyte address range. That segment register must not be changed by software, else the segment register
will point back into the 1 Mbyte address space.
To address the extended memory, [LOADALL](../loadall/) must be used to load the descriptor cache with an base address
beyond the normal 1 Mbyte address range. That segment register must not be changed by software, else the segment
register will point back into the 1 Mbyte address space.
Two types of systems are examined: accessing a single large database in a limited manner, or splitting software
into normal and extended areas. The first is the easiest to implement, while the second is more general.
@ -263,24 +264,25 @@ Access to a large data area outside the 1 Mbyte address space could be provided
scans the large data structure to locate the necessary item, then copy all data between the normal address space
and the extended address space.
Interrupts must be disabled while the subroutine uses segment registers that have been set by [LOADALL](../loadall/). The reload
of segment registers inside an interrupt routine would change the actual physical address from that loaded by [LOADALL](../loadall/)
before the interrupt. After all accesses in the extended area are done, interrupts may be enabled.
Interrupts must be disabled while the subroutine uses segment registers that have been set by [LOADALL](../loadall/).
The reload of segment registers inside an interrupt routine would change the actual physical address from that loaded
by [LOADALL](../loadall/) before the interrupt. After all accesses in the extended area are done, interrupts may be
enabled.
Returning the address of an extended data structure requires passing data through a segment register. For example,
the ES register could have been changed by [LOADALL](../loadall/) to point at a data area outside the bottom megabyte of physical
memory. The subroutine must not reload ES while it runs. The value stored in ES is not important since it is not
related to the physical address. Interrupts must not be allowed since the interrupt routine may reload ES.
the ES register could have been changed by [LOADALL](../loadall/) to point at a data area outside the bottom megabyte
of physical memory. The subroutine must not reload ES while it runs. The value stored in ES is not important since it
is not related to the physical address. Interrupts must not be allowed since the interrupt routine may reload ES.
A second technique uses special paragraph IDs (i.e. FFFFH) to signal that a piece of software is running in extended
mode. All interrupt handlers in the system must look when they return to the interrupted program to see if any of the
segment registers contain FFFFH. If so, then that segment register points at extended memory. [LOADALL](../loadall/) must be used
to load all the registers and the segment base address used last. The [LOADALL](../loadall/) memory area should contain that value
left there from the previous usage. Descriptors for the other segment registers with normal paragraph IDs must be
constructed before executing [LOADALL](../loadall/).
segment registers contain FFFFH. If so, then that segment register points at extended memory. [LOADALL](../loadall/)
must be used to load all the registers and the segment base address used last. The [LOADALL](../loadall/) memory area
should contain that value left there from the previous usage. Descriptors for the other segment registers with normal
paragraph IDs must be constructed before executing [LOADALL](../loadall/).
A semaphore must be placed around software that writes into the [LOADALL](../loadall/) area such that once written into, the software
can execute [LOADALL](../loadall/) without interruption.
A semaphore must be placed around software that writes into the [LOADALL](../loadall/) area such that once written into,
the software can execute [LOADALL](../loadall/) without interruption.
Mixing Real Mode and Protected Mode
---
@ -290,8 +292,8 @@ bottom megabyte of memory, while others execute in protected mode in the upper 1
gate could RESET the 80286, independent of the rest of the system, to force it to enter real mode. A short routine
at the power up address could redirect the software to the correct real mode program.
After executing the real mode program, [LOADALL](../loadall/) could then quickly restart the protected mode software. [LOADALL](../loadall/) can
be used as a form of task switch from real mode to a protected mode task.
After executing the real mode program, [LOADALL](../loadall/) could then quickly restart the protected mode software.
[LOADALL](../loadall/) can be used as a form of task switch from real mode to a protected mode task.
One operating system could service both the real and protected mode software. Any operating system call from the real
mode program would cause a switch to protected mode. The protected mode software could then construct descriptors that
@ -302,3 +304,5 @@ Interrupts must be handled specially. Interrupt handlers for both real mode and
times. If an interrupt handler needs to access a data area, that data area must be addressable from both real and
protected mode. The real mode interrupt table would be would be kept at location 000000H. The protected mode IDT could
be anywhere. [LOADALL](../loadall/) will switch to the protected interrupt table.
[Return to [Intel 80286 CPU Information](/pubs/pc/reference/intel/80286/)]

2
pubs/pc/reference/intel/80286/rep_restart/README.md
View file

@ -48,3 +48,5 @@ The above three problems are being corrected in all future steppings of the 8028
register will hold 0ffffH when the CPU detects a violation due to the conditions above. Note that even when REP MOVS and
REP INS restartability is corrected, CX will correctly continue to be 0000H when these instructions complete without generating
a protection violation.
[Return to [Intel 80286 CPU Information](/pubs/pc/reference/intel/80286/)]