More 8080 opcodes
This commit is contained in:
Jeff Parsons
parent
425f565b11
commit
4173aaca31
4 changed files with 458 additions and 237 deletions
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@ -121,9 +121,9 @@ CPUDef.opMVIB = function()
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*/
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CPUDef.opRLC = function()
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{
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var b = this.regA << 1;
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this.regA = (b & 0xff) | (b >> 8);
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this.resultZeroCarry = (this.resultZeroCarry & 0xff) | (b & 0x100);
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var carry = this.regA << 1;
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this.regA = (carry & 0xff) | (carry >> 8);
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this.resultZeroCarry = (this.resultZeroCarry & 0xff) | (carry & 0x100);
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this.nStepCycles -= 4;
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};
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@ -151,6 +151,223 @@ CPUDef.opLDAXB = function()
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this.nStepCycles -= 7;
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};
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/**
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* op=0x0B (DCX B)
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*
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* @this {CPUSim}
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*/
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CPUDef.opDCXB = function()
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{
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this.setBC(this.getBC() - 1);
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this.nStepCycles -= 5;
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};
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/**
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* op=0x0C (INR C)
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*
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* @this {CPUSim}
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*/
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CPUDef.opINRC = function()
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{
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this.regC = this.incByte(this.regC);
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this.nStepCycles -= 5;
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};
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/**
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* op=0x0D (DCR C)
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*
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* @this {CPUSim}
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*/
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CPUDef.opDCRC = function()
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{
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this.regC = this.decByte(this.regC);
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this.nStepCycles -= 5;
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};
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/**
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* op=0x0E (MVI C,d8)
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*
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* @this {CPUSim}
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*/
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CPUDef.opMVIC = function()
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{
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this.regC = this.getPCByte();
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this.nStepCycles -= 7;
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};
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/**
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* op=0x0F (RRC)
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*
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* @this {CPUSim}
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*/
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CPUDef.opRRC = function()
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{
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var carry = (this.regA << 8) & 0x100;
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this.regA = (carry | this.regA) >> 1;
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this.resultZeroCarry = (this.resultZeroCarry & 0xff) | carry;
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this.nStepCycles -= 4;
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};
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/**
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* op=0x11 (LXI D,d16)
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*
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* @this {CPUSim}
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*/
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CPUDef.opLXID = function()
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{
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this.setDE(this.getPCWord());
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this.nStepCycles -= 10;
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};
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/**
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* op=0x12 (STAX D)
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*
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* @this {CPUSim}
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*/
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CPUDef.opSTAXD = function()
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{
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this.setByte(this.getDE(), this.regA);
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this.nStepCycles -= 7;
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};
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/**
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* op=0x13 (INX D)
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*
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* @this {CPUSim}
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*/
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CPUDef.opINXD = function()
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{
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this.setDE(this.getDE() + 1);
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this.nStepCycles -= 5;
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};
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/**
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* op=0x14 (INR D)
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*
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* @this {CPUSim}
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*/
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CPUDef.opINRD = function()
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{
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this.regD = this.incByte(this.regD);
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this.nStepCycles -= 5;
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};
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/**
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* op=0x15 (DCR D)
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*
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* @this {CPUSim}
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*/
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CPUDef.opDCRD = function()
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{
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this.regD = this.decByte(this.regD);
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this.nStepCycles -= 5;
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};
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/**
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* op=0x16 (MVI D,d8)
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*
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* @this {CPUSim}
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*/
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CPUDef.opMVID = function()
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{
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this.regD = this.getPCByte();
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this.nStepCycles -= 7;
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};
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/**
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* op=0x17 (RAL)
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*
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* @this {CPUSim}
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*/
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CPUDef.opRAL = function()
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{
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var carry = this.regA << 1;
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this.regA = (carry & 0xff) | (this.resultZeroCarry >> 8);
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this.resultZeroCarry = (this.resultZeroCarry & 0xff) | (carry & 0x100);
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this.nStepCycles -= 4;
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};
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/**
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* op=0x19 (DAD D)
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*
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* @this {CPUSim}
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*/
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CPUDef.opDADD = function()
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{
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var w;
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this.setHL(w = this.getHL() + this.getDE());
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this.resultZeroCarry = (this.resultZeroCarry & 0xff) | ((w >> 8) & 0x100);
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this.nStepCycles -= 10;
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};
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/**
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* op=0x1A (LDAX D)
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*
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* @this {CPUSim}
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*/
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CPUDef.opLDAXD = function()
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{
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this.regA = this.getByte(this.getDE());
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this.nStepCycles -= 7;
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};
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/**
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* op=0x1B (DCX D)
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*
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* @this {CPUSim}
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*/
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CPUDef.opDCXD = function()
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{
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this.setDE(this.getDE() - 1);
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this.nStepCycles -= 5;
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};
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/**
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* op=0x1C (INR E)
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*
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* @this {CPUSim}
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*/
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CPUDef.opINRE = function()
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{
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this.regE = this.incByte(this.regE);
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this.nStepCycles -= 5;
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};
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/**
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* op=0x1D (DCR E)
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*
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* @this {CPUSim}
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*/
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CPUDef.opDCRE = function()
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{
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this.regE = this.decByte(this.regE);
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this.nStepCycles -= 5;
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};
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/**
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* op=0x1E (MVI E,d8)
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*
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* @this {CPUSim}
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*/
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CPUDef.opMVIE = function()
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{
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this.regE = this.getPCByte();
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this.nStepCycles -= 7;
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};
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/**
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* op=0x1F (RAR)
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*
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* @this {CPUSim}
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*/
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CPUDef.opRAR = function()
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{
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var carry = (this.regA << 8) & 0x100;
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this.regA = ((this.resultZeroCarry & 0x100) | this.regA) >> 1;
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this.resultZeroCarry = (this.resultZeroCarry & 0xff) | carry;
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this.nStepCycles -= 4;
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};
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/**
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* opTBD()
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*
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@ -173,12 +390,12 @@ CPUDef.opTBD = function()
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CPUDef.aOps = [
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/* 0x00-0x03 */ CPUDef.opNOP, CPUDef.opLXIB, CPUDef.opSTAXB, CPUDef.opINXB,
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/* 0x04-0x07 */ CPUDef.opINRB, CPUDef.opDCRB, CPUDef.opMVIB, CPUDef.opRLC,
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/* 0x08-0x0B */ CPUDef.opNOP, CPUDef.opDADB, CPUDef.opLDAXB, CPUDef.opTBD,
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/* 0x0C-0x0F */ CPUDef.opTBD, CPUDef.opTBD, CPUDef.opTBD, CPUDef.opTBD,
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/* 0x10-0x13 */ CPUDef.opTBD, CPUDef.opTBD, CPUDef.opTBD, CPUDef.opTBD,
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/* 0x14-0x17 */ CPUDef.opTBD, CPUDef.opTBD, CPUDef.opTBD, CPUDef.opTBD,
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/* 0x18-0x1B */ CPUDef.opTBD, CPUDef.opTBD, CPUDef.opTBD, CPUDef.opTBD,
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/* 0x1C-0x1F */ CPUDef.opTBD, CPUDef.opTBD, CPUDef.opTBD, CPUDef.opTBD,
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/* 0x08-0x0B */ CPUDef.opNOP, CPUDef.opDADB, CPUDef.opLDAXB, CPUDef.opDCXB,
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/* 0x0C-0x0F */ CPUDef.opINRC, CPUDef.opDCRC, CPUDef.opMVIC, CPUDef.opRRC,
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/* 0x10-0x13 */ CPUDef.opNOP, CPUDef.opLXID, CPUDef.opSTAXD, CPUDef.opINXD,
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/* 0x14-0x17 */ CPUDef.opINRD, CPUDef.opDCRD, CPUDef.opMVID, CPUDef.opRAL,
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/* 0x18-0x1B */ CPUDef.opNOP, CPUDef.opDADD, CPUDef.opLDAXD, CPUDef.opDCXD,
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/* 0x1C-0x1F */ CPUDef.opINRE, CPUDef.opDCRE, CPUDef.opMVIE, CPUDef.opRAR,
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/* 0x20-0x23 */ CPUDef.opTBD, CPUDef.opTBD, CPUDef.opTBD, CPUDef.opTBD,
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/* 0x24-0x27 */ CPUDef.opTBD, CPUDef.opTBD, CPUDef.opTBD, CPUDef.opTBD,
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/* 0x28-0x2B */ CPUDef.opTBD, CPUDef.opTBD, CPUDef.opTBD, CPUDef.opTBD,
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