Hacked the Bus component to permit devices to access the actual memory map (better solution will be maintain two separate maps: one for the CPU and a separate map for device access)
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parent
469d446ab7
commit
375146f6bb
9 changed files with 733 additions and 698 deletions
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@ -956,6 +956,10 @@ RL11.prototype.processCommand = function()
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}
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addr = (((this.ber & PDP11.RL11.RLBE.MASK)) << 16) | this.bar; // 22 bit mode
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nWords = (0x10000 - this.mpr) & 0xffff;
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if (DEBUG && this.messageEnabled(MessagesPDP11.READ)) {
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var pos = ((((iCylinder << 1) + iHead) * drive.nSectors) + iSector) * 128;
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this.printMessage((fnReadWrite == this.readData? "readData" : "writeData") + "(pos=" + pos + ",addr=" + str.toOct(addr) + ",bytes=" + (nWords * 2) + ")", true, true);
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}
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fInterrupt = fnReadWrite.call(this, drive, iCylinder, iHead, iSector, nWords, addr, this.endReadWrite.bind(this));
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break;
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@ -1140,9 +1144,7 @@ RL11.prototype.readRLCS = function(addr)
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RL11.prototype.writeRLCS = function(data, addr)
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{
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this.csr = (this.csr & ~PDP11.RL11.RLCS.WMASK) | (data & PDP11.RL11.RLCS.WMASK);
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this.bae = (this.bae & ~0x3) | ((data & PDP11.RL11.RLCS.BAE) >> 4);
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this.ber = (this.ber & 0x3C) | ((data & PDP11.RL11.RLCS.BAE) >> PDP11.RL11.RLCS.SHIFT.BAE);
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if (!(this.csr & PDP11.RL11.RLCS.CRDY)) this.processCommand();
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};
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@ -1233,6 +1235,12 @@ RL11.prototype.readRLBE = function(addr)
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/**
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* writeRLBE(data, addr)
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*
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* Curiously, we see RSTS/E v7.0 writing RLBE bits that aren't documented:
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*
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* R0=000000 R1=000000 R2=174410 R3=000000 R4=102076 R5=045166
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* SP=052662 PC=067624 PS=034344 IR=000000 SL=000377 T0 N0 Z1 V0 C0
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* 067624: 012712 000300 MOV #300,@R2
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*
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* @this {RL11}
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* @param {number} data
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* @param {number} addr (eg, PDP11.UNIBUS.RLBE or 174410)
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@ -1240,6 +1248,7 @@ RL11.prototype.readRLBE = function(addr)
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RL11.prototype.writeRLBE = function(data, addr)
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{
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this.ber = data & PDP11.RL11.RLBE.MASK;
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this.csr = (this.csr & ~PDP11.RL11.RLCS.BAE) | ((this.ber & 0x3) << PDP11.RL11.RLCS.SHIFT.BAE);
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};
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/*
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