From 367db069969f5e2a3157a7b07403777fc5256dc5 Mon Sep 17 00:00:00 2001 From: Jeff Parsons Date: Sun, 5 Oct 2014 09:33:45 -0700 Subject: [PATCH] Fixed 5170 diskette drive detection (40-track vs. 80-track drives) --- README.md | 37 +- apps/README.md | 2 +- blog/2014/09/30/README.md | 12 +- configs/pc/disks/README.md | 4 +- devices/pc/bios/5170/1984-01-10.json | 2 +- devices/pc/bios/5170/1984-01-10.map | 8 +- disks/README.md | 2 +- my_modules/diskdump/README.md | 2 +- my_modules/pcjs-client/lib/chipset.js | 538 +++++++++-------- my_modules/pcjs-client/lib/cpu.js | 2 +- my_modules/pcjs-client/lib/debugger.js | 28 +- my_modules/pcjs-client/lib/fdc.js | 562 +++++++++++------- my_modules/pcjs-client/lib/hdc.js | 166 +++--- my_modules/pcjs-client/lib/video.js | 2 +- versions/pcjs/1.15.3/pc-dbg.js | 764 ++++++++++++------------- versions/pcjs/1.15.3/pc.js | 614 ++++++++++---------- 16 files changed, 1490 insertions(+), 1255 deletions(-) diff --git a/README.md b/README.md index fdc3efc3a..874e97315 100644 --- a/README.md +++ b/README.md @@ -52,11 +52,11 @@ and the original machine are available in the [C1Pjs Documentation](/docs/c1pjs/ --- -Development Notes +Developer Notes --- -The [PCjs repository](https://github.com/jeffpar/pcjs) on GitHub contains everything used to create the [pcjs.org](http://www.pcjs.org/) -website, including: +The [PCjs repository](https://github.com/jeffpar/pcjs) on GitHub contains everything needed to start a local +copy of the [PCjs web server](http://www.pcjs.org/) and run PCjs simulations: + A simple Node-based web server ([server.js](server.js)) + Custom Node modules used by the web server ([HTMLOut](my_modules/htmlout/), [MarkOut](my_modules/markout/), [DiskDump](my_modules/diskdump/), [FileDump](my_modules/filedump/)) @@ -64,37 +64,46 @@ website, including: + The [PCjs](my_modules/pcjs-client/lib/) and [C1Pjs](my_modules/c1pjs-client/lib/) client applications, both "compiled" and uncompiled + A smattering of [PCjs](docs/pcjs/) and [C1Pjs](docs/c1pjs/) documentation, along with [blog posts](blog/), related [publications](pubs/) and more +The PCjs web server is *not* required to run most PCjs simulations. Any web server (Node, Apache, Nginx, etc) +that can serve the necessary JavaScript files to your browser will work. However, instructions for doing +that are beyond the scope of this "Quick Start" document. Also, it is possible to create simulations that require +access to PCjs web server APIs; however, none of the simulations in the repository should require API access. + ### Installing PCjs The following instructions were written for OS X users. However, users of other operating systems should have -no problem following along. +no problem following along. There are some prerequisites: -Open Terminal and `cd` to a directory where you'd like to install PCjs, and run the following commands: +- Git (included with OS X Developer Tools; separate download required for Windows) +- Python (used by NPM and included with OS X; separate download required for Windows) +- Node with NPM (download an appropriate installation package from [nodejs.org](http://nodejs.org/download/)) + +Once you have the prerequisites, open a command-line window, `cd` to the directory where you'd like to install PCjs, +and type the following commands: git clone git@github.com:jeffpar/pcjs.git pcjs cd pcjs npm install node server.js -Now open a web browser and go to `http://localhost:8088/`. You're done! +Now open a web browser and go to `http://localhost:8088/`. Done! -NOTE: If you just want to run the server and don't plan to do any development, you can reduce the footprint -slightly by asking NPM to install only "productions" modules: +If you just want to launch the web server or don't plan to do any development, you can reduce the +footprint slightly by asking NPM to install only "productions" modules (which can also eliminate some +errors if, for example, you neglected to install Python): npm install --production -If you ever inadvertently run `npm install` without `--production`, you can easily eliminate any unwanted -"devDependencies" with: +If you ever inadvertently run `npm install` without `--production`, you can easily uninstall all the +"devDependencies" listed in [package.json](package.json) with this command: npm prune --production -Finally, when installing the project on an AWS server, you have complete control of how Node is launched, but you -don't have direct control of NPM; the best you can do is set the following AWS "Environment Property": +Finally, when installing on an AWS server, although you have complete control over how Node is launched, you +don't have direct control over NPM; the best you can do is set the following AWS "Environment Property": NPM_CONFIG_PRODUCTION=true -It's assumed that the OS X Developer Tools (which include Git) have already been installed, as well as -Node and NPM. Node (which now includes NPM) can be downloaded from [nodejs.org](http://nodejs.org/download/). The current version of Node ([0.10.32](http://nodejs.org/dist/v0.10.32/node-v0.10.32.pkg) at the time of this writing) should work fine, but version [0.10.26](http://nodejs.org/dist/v0.10.26/node-v0.10.26.pkg) is what's been used to develop and test PCjs so far. diff --git a/apps/README.md b/apps/README.md index 0beac1a6c..d41e2cc41 100644 --- a/apps/README.md +++ b/apps/README.md @@ -68,7 +68,7 @@ using the following API request: http://www.pcjs.org/api/v1/dump?path=/apps/pc/1981/visicalc/bin/VC.COM;../README.md&format=json -The PCjs `diskdump` module processes the dump request and generates a JSON-encoded DOS 2.x-compatible disk image +The PCjs DiskDump module processes the dump request and generates a JSON-encoded DOS 2.x-compatible disk image containing all the specified files. However, to avoid the PCjs web server re-generating the same disk image for every user-initiated disk load, we diff --git a/blog/2014/09/30/README.md b/blog/2014/09/30/README.md index 4de993703..0f16e6616 100644 --- a/blog/2014/09/30/README.md +++ b/blog/2014/09/30/README.md @@ -1,9 +1,9 @@ My (JavaScript) Coding Conventions --- -Some ramblings about my JavaScript coding conventions. This is not an attempt to change anyone's mind -about anything, just an explanation of why things are they way they are (and will be more useful once PCjs -moves from a private to a public GitHub repository). +Some ramblings about my JavaScript coding conventions. This is not an attempt to convince anyone of +anything, just an explanation of why things are they way they are (and which will be more useful once PCjs +moves from a private to a public GitHub repository in the near future). ### Tabs vs. Spaces @@ -41,10 +41,10 @@ within a given file at least. I still tend to follow Charles Simonyi's "[Hungarian](http://en.wikipedia.org/wiki/Hungarian_notation)" naming conventions -- or rather, a naming convention loosely inspired by Hungarian. I know lots of people sneer at -those conventions and think they're useless, and all I can say is, they're wrong: they are not useless to ME. +those conventions or simply think they're useless, and all I can say is, they're wrong: they are not useless to *me*. I admit they may be useless to anyone who has a phenomenal memory and can remember that an obscure variable named -"foo" was initialized with a string or a number, or whose IDE can answer that question with the press of a key (or two), +"foo" was initialized with a string or a number, or whose IDE can answer the question with the press of a key (or two), but for me, with my non-phenomenal memory and lazy fingers, I prefer being able to simply look at a variable to immediately know what *type* of data it contains, if nothing else. @@ -139,7 +139,7 @@ And finally, speaking of warnings, I've had to tell PhpStorm to "shut up" about - “throw” of exception caught locally I acknowledge those those features can introduce bugs if you're not careful, so I make sure I'm careful. I don't -subscribe to the dogmatic approach that others (eg, the author of JSHint) take about so-called "risky" features. +subscribe to the dogmatic approach that others (eg, the author of JSLint) take about so-called "risky" features. I agree that it's always a good idea to walk to the crosswalk before crossing a street, but I don't agree that it's *never* a good idea to cross in the middle sometimes, too. diff --git a/configs/pc/disks/README.md b/configs/pc/disks/README.md index 8390bb3e9..c15a235f7 100644 --- a/configs/pc/disks/README.md +++ b/configs/pc/disks/README.md @@ -44,7 +44,7 @@ an *href* value to the <disk> section that was used to create the image: VisiCalc License -The PCjs "diskdump" module is used to create all our pre-generated JSON-encoded disk images. In the above example, a +The PCjs DiskDump module is used to create all our pre-generated JSON-encoded disk images. In the above example, a pre-generated disk image could be created from the command-line with either the "--dir" option (which will traverse all subdirectories as well): @@ -54,6 +54,6 @@ or with the "--path" option, which specifies either a single file or a set files node diskdump "--path=./apps/pc/1981/visicalc/bin/vc.com;../readme.md" --format=json --output=./apps/pc/1981/visicalc/disk.json -or via the PCjs server's "diskdump" API: +or via the PCjs server's DiskDump API: http://www.pcjs.org/api/v1/dump?path=/apps/pc/1981/visicalc/bin/vc.com&format=json diff --git a/devices/pc/bios/5170/1984-01-10.json b/devices/pc/bios/5170/1984-01-10.json index 35fd96d50..c47b29478 100644 --- a/devices/pc/bios/5170/1984-01-10.json +++ b/devices/pc/bios/5170/1984-01-10.json @@ -1023,4 +1023,4 @@ 0,0,0,0,-822083584,4683241,2112356352,-1243034839,1558760232,1089063717,49,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0,0,0,14703594,791752944,942616625,-1375993804] -,"symbols":{"POST1":{"o":44,"s":61440},"POST1_TEST01":{"o":166,"s":61440,"c":"TEST.01: 286 PROCESSOR TEST (REAL MODE)"},"POST1_TEST02":{"o":494,"s":61440,"c":"TEST.02: VERIFY CMOS SHUTDOWN BYTE"},"POST1_TEST03":{"o":531,"s":61440,"c":"TEST.03: ROS CHECKSUM TEST"},"POST1_TEST04":{"o":549,"s":61440,"c":"TEST.04: 8253 CHECK TIMER 1 (ALL BITS ON)"},"POST1_TEST05":{"o":604,"s":61440,"c":"TEST.05: 8253 CHECK TIMER 1 (ALL BITS OFF)"},"POST1_TEST06":{"o":635,"s":61440,"c":"TEST.06: 8237 DMA 0 INITIALIZATION"},"POST1_TEST07":{"o":710,"s":61440,"c":"TEST.07: 8237 DMA 1 INITIALIZATION"},"POST1_TEST08":{"o":827,"s":61440,"c":"TEST.08: DMA PAGE REGISTER TEST"},"POST1_TEST09":{"o":910,"s":61440,"c":"TEST.09: STORAGE REFRESH TEST"},"POST1_TEST10":{"o":934,"s":61440,"c":"TEST.10: 8042 TESTS"},"POST1_GETSW":{"o":989,"s":61440,"c":"GET SWITCH SETTINGS"},"POST1_TEST11":{"o":1062,"s":61440,"c":"TEST.11: BASE 64K R/W STORAGE TEST"},"POST1_SETMFG":{"o":1542,"s":61440,"c":"SET MFG_TST"},"POST1_TEST11A":{"o":1549,"s":61440,"c":"TEST.11A: VERIFY GDT/IDT INSTRUCTIONS"},"POST1_TEST12":{"o":1786,"s":61440,"c":"TEST.12: VERIFY CMOS CHECKSUM"},"POST1_TEST13":{"o":2018,"s":61440,"c":"TEST.13: PROTECTED MODE TEST"},"POST1_TEST13A":{"o":2231,"s":61440,"c":"TEST.13A: MEMORY SIZE TEST (ABOVE 1024K)"},"POST1_TEST14":{"o":2740,"s":61440,"c":"TEST.14: INITIALIZE CRT CONTROLLER"},"POST1_TEST15":{"o":2855,"s":61440,"c":"TEST.15: VIDEO LINE TEST"},"POST1_TEST16":{"o":2871,"s":61440,"c":"TEST.16: CRT INTERFACE LINES TEST"},"POST2":{"o":3135,"s":61440,"c":"TEST.17: 8259 PIC TEST"},"POST2_CP27":{"o":3223,"s":61440,"c":"CHECKPOINT 0x27"},"POST2_CP29":{"o":3282,"s":61440,"c":"CHECKPOINT 0x29"},"POST2_TEST18":{"o":3333,"s":61440,"c":"TEST.18: 8253 TIMER TEST (CHECKPOINT 0x2A)"},"POST2_ERR102":{"o":3366,"s":61440,"c":"DISPLAY 102 ERROR"},"POST2_CP2B":{"o":3376,"s":61440,"c":"CHECKPOINT 0x2B"},".263":{"o":3398,"s":61440,"a":"","c":"TIMER COUNTING TOO FAST, DISPLAY 102 ERROR"},"POST2_CP2C":{"o":3408,"s":61440,"c":"CHECKPOINT 0x2C"},"POST2_CP2D":{"o":3448,"s":61440,"c":"CHECKPOINT 0x2D"},"POST2_TEST19":{"o":3469,"s":61440,"c":"TEST.19: ADDITIONAL MEMORY TESTS (CHECKPOINT 0x2F)"},"POST2_TEST20":{"o":4503,"s":61440,"c":"TEST.20: ADDITIONAL PROTECTED-MODE TESTS"},"POST2_TEST21":{"o":4564,"s":61440,"c":"TEST.21: KEYBOARD TEST (CHECKPOINT 0x35)"},"POST2_CP36":{"o":4588,"s":61440,"c":"CHECKPOINT 0x36 (BEGIN KEYBOARD TEST)"},"POST2_CP37":{"o":4661,"s":61440,"c":"CHECKPOINT 0x37 (CHECK KBD_RESET SCAN CODE)"},"POST2_CP38":{"o":4670,"s":61440,"c":"CHECKPOINT 0x38 (RE-ENABLE KEYBOARD)"},"POST2_CP39":{"o":4689,"s":61440,"c":"CHECKPOINT 0x39 (STUCK KEYS)"},"POST2_CP3A":{"o":4756,"s":61440,"c":"CHECKPOINT 0x3A"},"POST2_RTCUP":{"o":5085,"s":61440,"c":"TEST CLOCK UPDATING"},"POST2_COMBOHF":{"o":5196,"s":61440,"c":"CHECK FOR COMBO HARD FILE/DISKETTE CARD"},"POST4":{"o":5971,"s":61440},"KBD_RESET":{"o":6098,"s":61440},"TEMP_ISR":{"o":6149,"s":61440},"HW_INT":{"o":6175,"s":61440},"NOT_SEC":{"o":6203,"s":61440},"SET_INTR_FLAG":{"o":6217,"s":61440},"POST5":{"o":6271,"s":61440},"EXC_13":{"o":6356,"s":61440,"c":"INT 13 (0x0D) GP FAULT HANDLER"},"SYS_32":{"o":6451,"s":61440,"c":"INT 32 (0x20) PROT-MODE TEST HANDLER"},"POST6":{"o":6556,"s":61440},"XMIT_8042":{"o":6949,"s":61440},"POST7":{"o":7213,"s":61440},"POST7_CPF1":{"o":7280,"s":61440,"c":"CHECKPOINT 0xF1"},"POST7_INT20":{"o":7288,"s":61440,"c":"TEST NORMAL SOFTWARE INTERRUPT"},"POST7_INT0D":{"o":7340,"s":61440,"c":"TEST GP FAULT (SEG LIMIT VIOLATION)"},"POST7_LLDT":{"o":7360,"s":61440,"c":"TEST LLDT"},"POST7_BOUND":{"o":7432,"s":61440,"c":"TEST BOUND"},"POST7_PUSHA":{"o":7539,"s":61440,"c":"TEST PUSHA/POPA"},"POST7_VERW":{"o":7623,"s":61440,"c":"TEST VERW/VERR"},"POST7_ARPL":{"o":7705,"s":61440,"c":"TEST ARPL"},"POST7_LAR":{"o":7751,"s":61440,"c":"TEST LAR/LSL"},"POST7_LOWMEG":{"o":7825,"s":61440,"c":"TEST WRITE TO 0x1B0000 VS. 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B000:0000"},"SYSINIT1":{"o":7962,"s":61440},"DISKETTE_IO_1":{"o":8357,"s":61440},"DISK_RETRY":{"o":8507,"s":61440},"DISK_RESET":{"o":8815,"s":61440},"DISK_STATUS":{"o":8881,"s":61440},"DISK_READ":{"o":8882,"s":61440},"DISK_VERF":{"o":8891,"s":61440},"DISK_FORMAT":{"o":8895,"s":61440},"DISK_WRITE":{"o":8933,"s":61440},"RW_OPN":{"o":8945,"s":61440},"GET_PARM":{"o":9255,"s":61440},"NEC_OUTPUT":{"o":9351,"s":61440},"SEEK":{"o":9409,"s":61440},"DMA_SETUP":{"o":9583,"s":61440},"CHK_STAT_2":{"o":9663,"s":61440},"WAIT_INT":{"o":9696,"s":61440},"DISK_INT_1":{"o":9742,"s":61440},"RESULTS":{"o":9765,"s":61440},"NUM_TRANS":{"o":9840,"s":61440},"READ_DSKCHNG":{"o":9897,"s":61440},"DISK_CHANGE":{"o":9963,"s":61440},"DISK_TYPE":{"o":10045,"s":61440},"FORMAT_SET":{"o":10162,"s":61440},"DSKETTE_SETUP":{"o":10262,"s":61440},"DISK_SETUP":{"o":10458,"s":61440},"DISK_IO":{"o":10865,"s":61440},"HD_INT":{"o":12196,"s":61440},"KEYBOARD_IO_1":{"o":12232,"s":61440},"KB_INT_1":{"o":12372,"s":61440},"K16":{"o":12457,"s":61440},"PRINTER_IO_1":{"o":13423,"s":61440},"RS232_IO_1":{"o":13557,"s":61440},"VIDEO_IO_1":{"o":13829,"s":61440},"SET_MODE":{"o":13902,"s":61440},"SET_CTYPE":{"o":14122,"s":61440},"SET_CPOS":{"o":14161,"s":61440},"READ_CURSOR":{"o":14203,"s":61440},"ACT_DISP_PAGE":{"o":14226,"s":61440},"SET_COLOR":{"o":14262,"s":61440},"VIDEO_STATE":{"o":14300,"s":61440},"SCROLL_UP":{"o":14335,"s":61440},"SCROLL_DOWN":{"o":14499,"s":61440},"READ_AC_CURRENT":{"o":14581,"s":61440},"WRITE_AC_CURRENT":{"o":14651,"s":61440},"WRITE_C_CURRENT":{"o":14702,"s":61440},"READ_DOT":{"o":14907,"s":61440},"WRITE_DOT":{"o":14924,"s":61440},"WRITE_TTY":{"o":15672,"s":61440},"READ_LPEN":{"o":15804,"s":61440},"MEMORY_SIZE_DETERMINE_1":{"o":15970,"s":61440},"EQUIPMENT_1":{"o":15980,"s":61440},"NMI_INT_1":{"o":15990,"s":61440},"SET_TOD":{"o":16175,"s":61440,"c":"CONVERT CMOS TIME TO TIMER TICKS"},"CASSETTE_IO_1":{"o":16354,"s":61440},"SHUT9":{"o":16978,"s":61440},"GATE_A20":{"o":17298,"s":61440},"TIME_OF_DAY_1":{"o":17500,"s":61440},"RTC_INT":{"o":17962,"s":61440},"TIMER_INT_1":{"o":18052,"s":61440},"PRINT_SCREEN_1":{"o":18124,"s":61440},"FILL":{"o":18258,"s":61440},"START":{"o":57435,"s":61440},"P_O_R":{"o":65520,"s":61440,"c":"POWER-ON RESET"}}} \ No newline at end of file diff --git a/devices/pc/bios/5170/1984-01-10.map b/devices/pc/bios/5170/1984-01-10.map index e8d1395ad..4989ea060 100644 --- a/devices/pc/bios/5170/1984-01-10.map +++ b/devices/pc/bios/5170/1984-01-10.map @@ -37,8 +37,14 @@ F000:05FF @ POST2_CP38 ; CHECKPOINT 0x38 (RE-ENABLE KEYBOARD) F000:0612 @ POST2_CP39 ; CHECKPOINT 0x39 (STUCK KEYS) F000:0655 @ POST2_CP3A ; CHECKPOINT 0x3A + F000:06E0 @ POST2_TEST23 ; TEST.23: DISKETTE ATTACHMENT TEST F000:079E @ POST2_RTCUP ; TEST CLOCK UPDATING - F000:080D @ POST2_COMBOHF ; CHECK FOR COMBO HARD FILE/DISKETTE CARD + F000:080D @ POST2_COMBOHF ; CHECK FOR COMBO HARD/FLOPPY CARD + F000:0877 @ POST2_TEST22 ; TEST.22: CHECK FOR OPTIONAL ROM + F000:08C3 @ POST2_PRINTER ; SETUP PRINTER_BASE + F000:08E6 @ POST2_PS232 ; SETUP RS232 + F000:0998 @ POST2_SETTOD ; SET TIME OF DAY + F000:0A6C @ POST2_INT19 ; GO TO BOOT LOADER 1753 + F000:0000 @ POST4 F000:007F @ KBD_RESET diff --git a/disks/README.md b/disks/README.md index 9f1f17e50..64e810ca0 100644 --- a/disks/README.md +++ b/disks/README.md @@ -7,7 +7,7 @@ Browse [IBM PC](pc/) and [Challenger 1P](c1p/) disk images. PCjs works best with disk images in a **JSON** format, to save conversion time, so that's the only disk image format you'll find on the PCjs website. -To convert any of our **JSON** disk images back into an **IMG** file, you can use the **diskdump** API +To convert any of our **JSON** disk images back into an **IMG** file, you can use the DiskDump API with the *format* parameter set to `img` instead of `json`. For example: http://www.pcjs.org/api/v1/dump?disk=/disks/pc/dos/ibm/2.00/PCDOS200-DISK1.json&format=img diff --git a/my_modules/diskdump/README.md b/my_modules/diskdump/README.md index 5f64edb6e..5750b415c 100644 --- a/my_modules/diskdump/README.md +++ b/my_modules/diskdump/README.md @@ -6,7 +6,7 @@ commented JSON, and IMG files). Building images from folders/files --- I finally ported the code in [convdisk.php](/bin/convdisk.php) that creates disk images -from the contents of local files/folders, which you can now access via the *diskdump* API. +from the contents of local files/folders, which you can now access via the *DiskDump* API. For example: diff --git a/my_modules/pcjs-client/lib/chipset.js b/my_modules/pcjs-client/lib/chipset.js index 70427203f..283b9dcae 100644 --- a/my_modules/pcjs-client/lib/chipset.js +++ b/my_modules/pcjs-client/lib/chipset.js @@ -128,8 +128,8 @@ if (typeof module !== 'undefined') { * * MODEL_5170 Description * ---------- ----------- - * 070 [3] CMOS Address ChipSet.CMOS_ADDR.PORT - * 071 CMOS Data ChipSet.CMOS_DATA.PORT + * 070 [3] CMOS Address ChipSet.CMOS.ADDR.PORT + * 071 CMOS Data ChipSet.CMOS.DATA.PORT * 0F0 Coprocessor Clear Busy (output 0x00) * 0F1 Coprocessor Reset (output 0x00) * @@ -178,6 +178,10 @@ function ChipSet(parmsChipSet) this.cDMACs = this.cPICs = 1; if (this.model >= ChipSet.MODEL_5170) { this.cDMACs = this.cPICs = 2; + this.regsHFCombo = { + bCtrl: 0x00, // port 0x1F4 + bStatus: 0x7F // port 0x1F7 + }; } this.fScaleTimers = parmsChipSet['scaleTimers'] || false; this.sRTCDate = parmsChipSet['rtcDate']; @@ -220,7 +224,7 @@ ChipSet.MODEL_5160 = 5160; ChipSet.MODEL_5170 = 5170; /* - * Values returned by ChipSet.getSW1VideoMonitor() + * Values returned by ChipSet.getSWVideoMonitor() */ ChipSet.MONITOR = {}; ChipSet.MONITOR.NONE = 0; @@ -514,7 +518,7 @@ ChipSet.PPI_CTRL.A_MODE = 0x60; /* * On the MODEL_5150, the following PPI_SW bits are exposed through PPI_A. * - * On the MODEL_5160, either the low or high 4 bits are exposed through PPI_C_SW, if PPI_B.ENABLE_SW_HI is clear or set. + * On the MODEL_5160, either the low or high 4 bits are exposed through PPI_C.SW, if PPI_B.ENABLE_SW_HI is clear or set. */ ChipSet.PPI_SW = {}; ChipSet.PPI_SW.FDRIVE = {}; @@ -533,7 +537,7 @@ ChipSet.PPI_SW.MONITOR.CGA80 = 0x20; ChipSet.PPI_SW.MONITOR.MDA = 0x30; ChipSet.PPI_SW.MONITOR.MASK = 0x30; ChipSet.PPI_SW.MONITOR.SHIFT = 4; -ChipSet.PPI_SW.FDRIVE.ONE = 0x00; // 1 floppy drive attached (or 0 drives if PPI_SW_FDRIVE_IPL is not set -- MODEL_5150 only) +ChipSet.PPI_SW.FDRIVE.ONE = 0x00; // 1 floppy drive attached (or 0 drives if PPI_SW.FDRIVE_IPL is not set -- MODEL_5150 only) ChipSet.PPI_SW.FDRIVE.TWO = 0x40; // 2 floppy drives attached ChipSet.PPI_SW.FDRIVE.THREE = 0x80; // 3 floppy drives attached ChipSet.PPI_SW.FDRIVE.FOUR = 0xC0; // 4 floppy drives attached @@ -558,7 +562,7 @@ ChipSet.PPI_SW.FDRIVE.SHIFT = 6; * the same register (bPPIB) but install different I/O handlers. It's also bi-directional: at one point, the BIOS * reads KBD_RWREG.REFRESH_BIT (bit 4) to verify that it's alternating. * - * PPI_C and PPI_CTRL are neither documented nor used by the MODEL_5170 BIOS, so I'm assuming they're obsolete. + * PPI_C and PPI_CTRL don't seem to be documented or used by the MODEL_5170 BIOS, so I'm assuming they're obsolete. * * NOTE: For more information on the 8042 Controller, including information on undocumented commands, refer to the * documents in /devices/pc/keyboard/, as well as the following websites: @@ -566,40 +570,36 @@ ChipSet.PPI_SW.FDRIVE.SHIFT = 6; * http://halicery.com/8042/8042_INTERN_TXT.htm * http://www.os2museum.com/wp/?p=589 ("IBM PC/AT 8042 Keyboard Controller Commands") */ -ChipSet.KBD_DATA = { // this.b8042OutBuff (PPI_A on previous models, still referred to as "PORT A" by the MODEL_5170 BIOS) - PORT: 0x60 +ChipSet.KBC = {}; +ChipSet.KBC.DATA = { // this.b8042OutBuff (PPI_A on previous models, still referred to as "PORT A" by the MODEL_5170 BIOS) + PORT: 0x60, + SELF_TEST: { // result of ChipSet.KBC.CMD.SELF_TEST command (0xAA) + OK: 0x55 + }, + INTF_TEST: { // result of ChipSet.KBC.CMD.INTF_TEST command (0xAB) + OK: 0x00, // no error + CLOCK_LO: 0x01, // keyboard clock line stuck low + CLOCK_HI: 0x02, // keyboard clock line stuck high + DATA_LO: 0x03, // keyboard data line stuck low + DATA_HI: 0x04 // keyboard data line stuck high + } }; - -ChipSet.KBD_DATA.CMD = { // this.b8042CmdData (KBD_DATA.CMD "data bytes" written to port 0x60, after writing a KBD_CMD byte to port 0x64) +ChipSet.KBC.DATA.CMD = { // this.b8042CmdData (KBD_DATA.CMD "data bytes" written to port 0x60, after writing a KBD_CMD byte to port 0x64) PC_COMPAT: 0x40, // generate IBM PC-compatible scan codes PC_MODE: 0x20, NO_CLOCK: 0x10, // disable keyboard by driving "clock" line low NO_INHIBIT: 0x08, // disable inhibit function - SYS_FLAG: 0x04, // this value is propagated to ChipSet.KBD_STATUS.SYS_FLAG + SYS_FLAG: 0x04, // this value is propagated to ChipSet.KBC.STATUS.SYS_FLAG INT_ENABLE: 0x01 // generate an interrupt when the controller places data in the output buffer }; - -ChipSet.KBD_DATA.SELF_TEST = { - OK: 0x55 -}; - -ChipSet.KBD_DATA.INTF_TEST = { // result of ChipSet.KBD_CMD.INTF_TEST command (0xAB) - OK: 0x00, // no error - KBD_CLOCK_LO: 0x01, // keyboard clock line stuck low - KBD_CLOCK_HI: 0x02, // keyboard clock line stuck high - KBD_DATA_LO: 0x03, // keyboard data line stuck low - KBD_DATA_HI: 0x04 // keyboard data line stuck high -}; - -ChipSet.KBD_DATA.INPORT = { // this.b8042InPort +ChipSet.KBC.INPORT = { // this.b8042InPort UNDEFINED: 0x0F, // undefined ENABLE_256KB: 0x10, // enable 2nd 256Kb of system board RAM MFG_OFF: 0x20, // manufacturing jumper not installed MONO: 0x40, // monochrome monitor is primary display KBD_ON: 0x80 // keyboard not inhibited }; - -ChipSet.KBD_DATA.OUTPORT = { // this.b8042OutPort +ChipSet.KBC.OUTPORT = { // this.b8042OutPort NO_RESET: 0x01, // set by default A20_ON: 0x02, // set by default OUTBUFF_FULL: 0x10, // output buffer full @@ -607,13 +607,11 @@ ChipSet.KBD_DATA.OUTPORT = { // this.b8042OutPort KBD_CLOCK: 0x40, // keyboard clock (output) KBD_DATA: 0x80 // keyboard data (output) }; - -ChipSet.KBD_DATA.TESTPORT = { // generated "on the fly" +ChipSet.KBC.TESTPORT = { // generated "on the fly" KBD_CLOCK: 0x01, // keyboard clock (input) KBD_DATA: 0x02 // keyboard data (input) }; - -ChipSet.KBD_RWREG = { // this.bPPIB (since CLK_TIMER2 and SPK_TIMER2 are in both PPI_B and KBD_RWREG) +ChipSet.KBC.RWREG = { // this.bPPIB (since CLK_TIMER2 and SPK_TIMER2 are in both PPI_B and KBD_RWREG) PORT: 0x61, CLK_TIMER2: 0x01, // set to enable clock to TIMER2 SPK_TIMER2: 0x02, // set to connect output of TIMER2 to speaker @@ -623,17 +621,7 @@ ChipSet.KBD_RWREG = { // this.bPPIB (since CLK_TIMER2 and SPK_TIMER2 a PARITY_CHK: 0x80, // indicates RAM parity check PARITY_ERR: 0xC0 }; - -ChipSet.KBD_DATA.CMD = { // this.b8042CmdData (KBD_DATA.CMD "data bytes" written to port 0x60, after writing a KBD_CMD byte to port 0x64) - PC_COMPAT: 0x40, // generate IBM PC-compatible scan codes - PC_MODE: 0x20, - NO_CLOCK: 0x10, // disable keyboard by driving "clock" line low - NO_INHIBIT: 0x08, // disable inhibit function - SYS_FLAG: 0x04, // this value is propagated to ChipSet.KBD_STATUS.SYS_FLAG - INT_ENABLE: 0x01 // generate an interrupt when the controller places data in the output buffer -}; - -ChipSet.KBD_CMD = { // this.b8042InBuff (on write to port 0x64, interpret this as a CMD) +ChipSet.KBC.CMD = { // this.b8042InBuff (on write to port 0x64, interpret this as a CMD) PORT: 0x64, READ_CMD: 0x20, WRITE_CMD: 0x60, // followed by a command byte written to KBD_DATA.PORT (see KBD_DATA.CMD) @@ -648,8 +636,7 @@ ChipSet.KBD_CMD = { // this.b8042InBuff (on write to port 0x64, inte READ_TEST: 0xE0, PULSE_OUTPORT: 0xF0 // this is the 1st of 16 commands (0xF0-0xFF) that pulse bits 0-3 of the output port }; - -ChipSet.KBD_STATUS = { // this.b8042Status (on read from port 0x64) +ChipSet.KBC.STATUS = { // this.b8042Status (on read from port 0x64) PORT: 0x64, OUTBUFF_FULL: 0x01, INBUFF_FULL: 0x02, // set if the controller has received but not yet read data written to the input buffer (not normally set) @@ -665,90 +652,89 @@ ChipSet.KBD_STATUS = { // this.b8042Status (on read from port 0x64) /* * MC146818A RTC/CMOS Ports (MODEL_5170) * - * Write a CMOS address to ChipSet.CMOS_ADDR.PORT, then read/write data from/to ChipSet.CMOS_DATA.PORT. + * Write a CMOS address to ChipSet.CMOS.ADDR.PORT, then read/write data from/to ChipSet.CMOS.DATA.PORT. * * The ADDR port also controls NMI: write an address with bit 7 clear to enable NMI or set to disable NMI. */ -ChipSet.CMOS_ADDR = {}; // this.bCMOSAddr -ChipSet.CMOS_ADDR.PORT = 0x70; -ChipSet.CMOS_ADDR.RTC_SEC = 0x00; -ChipSet.CMOS_ADDR.RTC_SEC_ALRM = 0x01; -ChipSet.CMOS_ADDR.RTC_MIN = 0x02; -ChipSet.CMOS_ADDR.RTC_MIN_ALRM = 0x03; -ChipSet.CMOS_ADDR.RTC_HOUR = 0x04; -ChipSet.CMOS_ADDR.RTC_HOUR_ALRM = 0x05; -ChipSet.CMOS_ADDR.RTC_WEEK_DAY = 0x06; -ChipSet.CMOS_ADDR.RTC_MONTH_DAY = 0x07; -ChipSet.CMOS_ADDR.RTC_MONTH = 0x08; -ChipSet.CMOS_ADDR.RTC_YEAR = 0x09; -ChipSet.CMOS_ADDR.RTC_STATUSA = 0x0A; -ChipSet.CMOS_ADDR.RTC_STATUSB = 0x0B; -ChipSet.CMOS_ADDR.RTC_STATUSC = 0x0C; -ChipSet.CMOS_ADDR.RTC_STATUSD = 0x0D; -ChipSet.CMOS_ADDR.DIAG = 0x0E; -ChipSet.CMOS_ADDR.SHUTDOWN = 0x0F; -ChipSet.CMOS_ADDR.FDRIVE = 0x10; -ChipSet.CMOS_ADDR.HDRIVE = 0x12; -ChipSet.CMOS_ADDR.EQUIP = 0x14; -ChipSet.CMOS_ADDR.BASEMEM_LO = 0x15; -ChipSet.CMOS_ADDR.BASEMEM_HI = 0x16; //the BASEMEM values indicate the total Kb of base memory, up to 0x280 (640Kb) -ChipSet.CMOS_ADDR.EXTMEM_LO = 0x17; -ChipSet.CMOS_ADDR.EXTMEM_HI = 0x18; //the EXTMEM values indicate the total Kb of extended memory, up to 0x3C00 (15Mb) -ChipSet.CMOS_ADDR.CHKSUM_HI = 0x2E; -ChipSet.CMOS_ADDR.CHKSUM_LO = 0x2F; // CMOS bytes included in the checksum calculation: 0x10-0x2D -ChipSet.CMOS_ADDR.EXTMEM2_LO = 0x30; -ChipSet.CMOS_ADDR.EXTMEM2_HI = 0x31; -ChipSet.CMOS_ADDR.CENTURY_DATE = 0x32; // BCD value for the current century (eg, 0x19 for 20th century, 0x20 for 21st century) -ChipSet.CMOS_ADDR.BOOT_INFO = 0x33; // 0x80 if 128Kb expansion memory installed, 0x40 if Setup Utility wants an initial setup message -ChipSet.CMOS_ADDR.MASK = 0x3F; -ChipSet.CMOS_ADDR.TOTAL = 0x40; -ChipSet.CMOS_ADDR.NMI_DISABLE = 0x80; +ChipSet.CMOS = {}; +ChipSet.CMOS.ADDR = {}; // this.bCMOSAddr +ChipSet.CMOS.ADDR.PORT = 0x70; +ChipSet.CMOS.ADDR.RTC_SEC = 0x00; +ChipSet.CMOS.ADDR.RTC_SEC_ALRM = 0x01; +ChipSet.CMOS.ADDR.RTC_MIN = 0x02; +ChipSet.CMOS.ADDR.RTC_MIN_ALRM = 0x03; +ChipSet.CMOS.ADDR.RTC_HOUR = 0x04; +ChipSet.CMOS.ADDR.RTC_HOUR_ALRM = 0x05; +ChipSet.CMOS.ADDR.RTC_WEEK_DAY = 0x06; +ChipSet.CMOS.ADDR.RTC_MONTH_DAY = 0x07; +ChipSet.CMOS.ADDR.RTC_MONTH = 0x08; +ChipSet.CMOS.ADDR.RTC_YEAR = 0x09; +ChipSet.CMOS.ADDR.RTC_STATUSA = 0x0A; +ChipSet.CMOS.ADDR.RTC_STATUSB = 0x0B; +ChipSet.CMOS.ADDR.RTC_STATUSC = 0x0C; +ChipSet.CMOS.ADDR.RTC_STATUSD = 0x0D; +ChipSet.CMOS.ADDR.DIAG = 0x0E; +ChipSet.CMOS.ADDR.SHUTDOWN = 0x0F; +ChipSet.CMOS.ADDR.FDRIVE = 0x10; // drive 0 ChipSet.FDRIVE in high nibble, drive 1 ChipSet.FDRIVE value in low nibble +ChipSet.CMOS.ADDR.HDRIVE = 0x12; +ChipSet.CMOS.ADDR.EQUIP = 0x14; +ChipSet.CMOS.ADDR.BASEMEM_LO = 0x15; +ChipSet.CMOS.ADDR.BASEMEM_HI = 0x16; // the BASEMEM values indicate the total Kb of base memory, up to 0x280 (640Kb) +ChipSet.CMOS.ADDR.EXTMEM_LO = 0x17; +ChipSet.CMOS.ADDR.EXTMEM_HI = 0x18; // the EXTMEM values indicate the total Kb of extended memory, up to 0x3C00 (15Mb) +ChipSet.CMOS.ADDR.CHKSUM_HI = 0x2E; +ChipSet.CMOS.ADDR.CHKSUM_LO = 0x2F; // CMOS bytes included in the checksum calculation: 0x10-0x2D +ChipSet.CMOS.ADDR.EXTMEM2_LO = 0x30; +ChipSet.CMOS.ADDR.EXTMEM2_HI = 0x31; +ChipSet.CMOS.ADDR.CENTURY_DATE = 0x32; // BCD value for the current century (eg, 0x19 for 20th century, 0x20 for 21st century) +ChipSet.CMOS.ADDR.BOOT_INFO = 0x33; // 0x80 if 128Kb expansion memory installed, 0x40 if Setup Utility wants an initial setup message +ChipSet.CMOS.ADDR.MASK = 0x3F; +ChipSet.CMOS.ADDR.TOTAL = 0x40; +ChipSet.CMOS.ADDR.NMI_DISABLE = 0x80; -ChipSet.CMOS_DATA = {}; // this.abCMOSData -ChipSet.CMOS_DATA.PORT = 0x71; +ChipSet.CMOS.DATA = {}; // this.abCMOSData +ChipSet.CMOS.DATA.PORT = 0x71; -ChipSet.CMOS_STATUSA = {}; // abCMOSData[ChipSet.CMOS_ADDR.RTC_STATUSA] -ChipSet.CMOS_STATUSA.UIP = 0x80; // bit 7: 1 indicates Update-In-Progress, 0 indicates date/time ready to read -ChipSet.CMOS_STATUSA.DV = 0x70; // bits 6-4 (DV2-DV0) are programmed to 010 to select a 32.768Khz time base -ChipSet.CMOS_STATUSA.RS = 0x0F; // bits 3-0 (RS3-RS0) are programmed to 0110 to select a 976.562us interrupt rate +ChipSet.CMOS.STATUSA = {}; // abCMOSData[ChipSet.CMOS.ADDR.RTC_STATUSA] +ChipSet.CMOS.STATUSA.UIP = 0x80; // bit 7: 1 indicates Update-In-Progress, 0 indicates date/time ready to read +ChipSet.CMOS.STATUSA.DV = 0x70; // bits 6-4 (DV2-DV0) are programmed to 010 to select a 32.768Khz time base +ChipSet.CMOS.STATUSA.RS = 0x0F; // bits 3-0 (RS3-RS0) are programmed to 0110 to select a 976.562us interrupt rate -ChipSet.CMOS_STATUSB = {}; // abCMOSData[ChipSet.CMOS_ADDR.RTC_STATUSB] -ChipSet.CMOS_STATUSB.SET = 0x80; // bit 7: 1 to set any/all of the 14 time-bytes -ChipSet.CMOS_STATUSB.PIE = 0x40; // bit 6: 1 for Periodic Interrupt Enable -ChipSet.CMOS_STATUSB.AIE = 0x20; // bit 5: 1 for Alarm Interrupt Enable -ChipSet.CMOS_STATUSB.UIE = 0x10; // bit 4: 1 for Update-Ended Interrupt Enable -ChipSet.CMOS_STATUSB.SQWE = 0x08; // bit 3: 1 for Square Wave Enabled (as set by the STATUSA rate selection bits) -ChipSet.CMOS_STATUSB.BINARY = 0x04; // bit 2: 1 for binary Date Mode, 0 for BCD Date Mode -ChipSet.CMOS_STATUSB.HOUR24 = 0x02; // bit 1: 1 for 24-hour mode, 0 for 12-hour mode -ChipSet.CMOS_STATUSB.DST = 0x01; // bit 0: 1 for Daylight Savings Time enabled +ChipSet.CMOS.STATUSB = {}; // abCMOSData[ChipSet.CMOS.ADDR.RTC_STATUSB] +ChipSet.CMOS.STATUSB.SET = 0x80; // bit 7: 1 to set any/all of the 14 time-bytes +ChipSet.CMOS.STATUSB.PIE = 0x40; // bit 6: 1 for Periodic Interrupt Enable +ChipSet.CMOS.STATUSB.AIE = 0x20; // bit 5: 1 for Alarm Interrupt Enable +ChipSet.CMOS.STATUSB.UIE = 0x10; // bit 4: 1 for Update-Ended Interrupt Enable +ChipSet.CMOS.STATUSB.SQWE = 0x08; // bit 3: 1 for Square Wave Enabled (as set by the STATUSA rate selection bits) +ChipSet.CMOS.STATUSB.BINARY = 0x04; // bit 2: 1 for binary Date Mode, 0 for BCD Date Mode +ChipSet.CMOS.STATUSB.HOUR24 = 0x02; // bit 1: 1 for 24-hour mode, 0 for 12-hour mode +ChipSet.CMOS.STATUSB.DST = 0x01; // bit 0: 1 for Daylight Savings Time enabled -ChipSet.CMOS_STATUSC = {}; // abCMOSData[ChipSet.CMOS_ADDR.RTC_STATUSC] TODO: Does reading this register clear these interrupt conditions? (see F000:01C6 in the MODEL_5170 BIOS) -ChipSet.CMOS_STATUSC.IRQF = 0x80; // bit 7 -ChipSet.CMOS_STATUSC.PF = 0x40; // bit 6: 1 indicates Periodic Interrupt -ChipSet.CMOS_STATUSC.AF = 0x20; // bit 5: 1 indicates Alarm Interrupt -ChipSet.CMOS_STATUSC.UF = 0x10; // bit 4: 1 indicates Update-Ended Interrupt -ChipSet.CMOS_STATUSC.RESERVED = 0x0F; +ChipSet.CMOS.STATUSC = {}; // abCMOSData[ChipSet.CMOS.ADDR.RTC_STATUSC] TODO: Does reading this register clear these interrupt conditions? (see F000:01C6 in the MODEL_5170 BIOS) +ChipSet.CMOS.STATUSC.IRQF = 0x80; // bit 7 +ChipSet.CMOS.STATUSC.PF = 0x40; // bit 6: 1 indicates Periodic Interrupt +ChipSet.CMOS.STATUSC.AF = 0x20; // bit 5: 1 indicates Alarm Interrupt +ChipSet.CMOS.STATUSC.UF = 0x10; // bit 4: 1 indicates Update-Ended Interrupt +ChipSet.CMOS.STATUSC.RESERVED = 0x0F; -ChipSet.CMOS_STATUSD = {}; // abCMOSData[ChipSet.CMOS_ADDR.RTC_STATUSD] -ChipSet.CMOS_STATUSD.VRB = 0x80; // bit 7: 1 indicates Valid RAM Bit (0 implies power was and/or is lost) -ChipSet.CMOS_STATUSD.RESERVED = 0x7F; +ChipSet.CMOS.STATUSD = {}; // abCMOSData[ChipSet.CMOS.ADDR.RTC_STATUSD] +ChipSet.CMOS.STATUSD.VRB = 0x80; // bit 7: 1 indicates Valid RAM Bit (0 implies power was and/or is lost) +ChipSet.CMOS.STATUSD.RESERVED = 0x7F; -ChipSet.CMOS_DIAG = {}; // abCMOSData[ChipSet.CMOS_ADDR.DIAG] -ChipSet.CMOS_DIAG.RTCFAIL = 0x80; // bit 7: 1 indicates RTC lost power -ChipSet.CMOS_DIAG.CHKSUMFAIL = 0x40; // bit 6: 1 indicates bad CMOS checksum -ChipSet.CMOS_DIAG.CONFIGFAIL = 0x20; // bit 5: 1 indicates bad CMOS configuration info -ChipSet.CMOS_DIAG.MEMSIZEFAIL = 0x10; // bit 4: 1 indicates memory size miscompare -ChipSet.CMOS_DIAG.HDRIVEFAIL = 0x08; // bit 3: 1 indicates hard drive controller or drive init failure -ChipSet.CMOS_DIAG.TIMEFAIL = 0x04; // bit 2: 1 indicates time failure -ChipSet.CMOS_DIAG.RESERVED = 0x03; +ChipSet.CMOS.DIAG = {}; // abCMOSData[ChipSet.CMOS.ADDR.DIAG] +ChipSet.CMOS.DIAG.RTCFAIL = 0x80; // bit 7: 1 indicates RTC lost power +ChipSet.CMOS.DIAG.CHKSUMFAIL = 0x40; // bit 6: 1 indicates bad CMOS checksum +ChipSet.CMOS.DIAG.CONFIGFAIL = 0x20; // bit 5: 1 indicates bad CMOS configuration info +ChipSet.CMOS.DIAG.MEMSIZEFAIL = 0x10; // bit 4: 1 indicates memory size miscompare +ChipSet.CMOS.DIAG.HDRIVEFAIL = 0x08; // bit 3: 1 indicates hard drive controller or drive init failure +ChipSet.CMOS.DIAG.TIMEFAIL = 0x04; // bit 2: 1 indicates time failure +ChipSet.CMOS.DIAG.RESERVED = 0x03; -ChipSet.CMOS_FDRIVE = {}; // abCMOSData[ChipSet.CMOS_ADDR.FDRIVE] -ChipSet.CMOS_FDRIVE.D0 = 0xF0; -ChipSet.CMOS_FDRIVE.D0_DS = 0x10; // double-sided drive (48 TPI) -ChipSet.CMOS_FDRIVE.D0_HC = 0x20; // high-capacity drive (96 TPI) -ChipSet.CMOS_FDRIVE.D1 = 0x0F; -ChipSet.CMOS_FDRIVE.D1_DS = 0x01; // double-sided drive (48 TPI) -ChipSet.CMOS_FDRIVE.D1_HC = 0x02; // high-capacity drive (96 TPI) +ChipSet.FDRIVE = { // abCMOSData[ChipSet.CMOS.ADDR.FDRIVE] values (drive 0 value in high nibble, drive 1 value in low nibble) + NONE: 0, // no drive + DSDD: 1, // double-sided double-density drive (48 TPI, 40-track, 360Kb max) + DSHC: 2 // double-sided high-capacity drive (96 TPI, 80-track, 1.2Mb max) +}; /* * The following HDRIVE types are supported by the MODEL_5170, where C is Cylinders, H is Heads, @@ -772,17 +758,17 @@ ChipSet.CMOS_FDRIVE.D1_HC = 0x02; // high-capacity drive (96 TPI) * 14 733 7 no 733 * 15 (reserved--all zeros) */ -ChipSet.CMOS_HDRIVE = {}; // abCMOSData[ChipSet.CMOS_ADDR.HDRIVE] -ChipSet.CMOS_HDRIVE.D0 = 0xF0; -ChipSet.CMOS_HDRIVE.D1 = 0x0F; +ChipSet.CMOS.HDRIVE = {}; // abCMOSData[ChipSet.CMOS.ADDR.HDRIVE] +ChipSet.CMOS.HDRIVE.D0 = 0xF0; +ChipSet.CMOS.HDRIVE.D1 = 0x0F; /* * The CMOS equipment flags use the same format as the older PPI equipment flags */ -ChipSet.CMOS_EQUIP = {}; // abCMOSData[ChipSet.CMOS_ADDR.EQUIP] -ChipSet.CMOS_EQUIP.MONITOR = ChipSet.PPI_SW.MONITOR; // PPI_SW.MONITOR.MASK == 0x30 -ChipSet.CMOS_EQUIP.COPROC = ChipSet.PPI_SW.COPROC; // PPI_SW.COPROC == 0x02 -ChipSet.CMOS_EQUIP.FDRIVE = ChipSet.PPI_SW.FDRIVE; // PPI_SW.FDRIVE.IPL == 0x01 and PPI_SW.FDRIVE.MASK = 0xC0 +ChipSet.CMOS.EQUIP = {}; // abCMOSData[ChipSet.CMOS.ADDR.EQUIP] +ChipSet.CMOS.EQUIP.MONITOR = ChipSet.PPI_SW.MONITOR; // PPI_SW.MONITOR.MASK == 0x30 +ChipSet.CMOS.EQUIP.COPROC = ChipSet.PPI_SW.COPROC; // PPI_SW.COPROC == 0x02 +ChipSet.CMOS.EQUIP.FDRIVE = ChipSet.PPI_SW.FDRIVE; // PPI_SW.FDRIVE.IPL == 0x01 and PPI_SW.FDRIVE.MASK = 0xC0 /* * Manufacturing Test Ports (MODEL_5170) @@ -819,10 +805,24 @@ ChipSet.COPROC.PORT_RESET = 0xF1; // reset the coprocessor /* * Ports used by MODEL_5170 BIOS for "Combo Hard File/Diskette Card" check (@F000:144C) * - * We're intercepting reads for this card's STATUS port simply to reduce boot time; otherwise, - * our default unknown port response (0xFF) maximizes boot delay. The STATUS port simply needs - * to return a byte with bit 7 clear, so that the BIOS will then attempt to write/read the CTRL - * port, which will immediately fail (since the write will be ignored). + * The ChipSet component provides minimal boot-time support for the "IBM Personal Computer + * AT Fixed Disk and Diskette Drive Adapter", aka the HFCOMBO card, until we're able to fork + * the HDC component into a new HDCombo component to deal with the "Fixed Disk" portion + * of the HFCOMBO card. Fortunately, the "Diskette Drive Adapter" portion of the card is + * quite compatible with the existing FDC component, so that component can be used as-is, + * with minor tweaks. + * + * Initially, we intercepted reads for HFCOMBO's STATUS port simply to reduce boot time; + * otherwise, our default "unknown port" response of 0xFF would maximize boot delay. To solve + * that, the STATUS port simply needs to return a byte with bit 7 clear, so that the BIOS + * will then attempt to write/read the CTRL port. + * + * Next, we initially treated the HFCOMBO's CTRL port as an "unknown port", because again, + * we didn't need HDC support and it didn't seem to affect FDC support. But it turns out + * that FDC support IS affected, because if the BIOS doesn't set the "DUAL" bit (bit 0) of the + * "HFCNTRL" byte at 40:8F, then when it comes time later to report the diskette drive type, + * the "DISK_TYPE" function (@F000:273D) will branch to one of two almost-identical blocks of + * code -- specifically, the block that disallows diskette drive types >= 2 instead of >= 3. */ ChipSet.HFCOMBO = {}; ChipSet.HFCOMBO.CTRL = {PORT: 0x1F4}; @@ -1001,21 +1001,21 @@ ChipSet.prototype.reset = function() * TODO: Consider a UI for the Keyboard INHIBIT switch. By default, our keyboard is never inhibited * (ie, locked). Also, note that the hardware changes this bit only when new data is sent to b8042OutBuff. */ - this.b8042Status = ChipSet.KBD_STATUS.NO_INHIBIT; + this.b8042Status = ChipSet.KBC.STATUS.NO_INHIBIT; this.b8042InBuff = 0; - this.b8042CmdData = ChipSet.KBD_DATA.CMD.NO_CLOCK; + this.b8042CmdData = ChipSet.KBC.DATA.CMD.NO_CLOCK; this.b8042OutBuff = 0; /* * TODO: Provide more control over these 8042 "Input Port" bits (eg, the keyboard lock) */ - this.b8042InPort = ChipSet.KBD_DATA.INPORT.MFG_OFF | ChipSet.KBD_DATA.INPORT.KBD_ON; - if (this.getSWMemorySize() >= 512) this.b8042InPort |= ChipSet.KBD_DATA.INPORT.ENABLE_256KB; - if (this.getSW1VideoMonitor() == ChipSet.MONITOR.MONO) this.b8042InPort |= ChipSet.KBD_DATA.INPORT.MONO; + this.b8042InPort = ChipSet.KBC.INPORT.MFG_OFF | ChipSet.KBC.INPORT.KBD_ON; + if (this.getSWMemorySize() >= 512) this.b8042InPort |= ChipSet.KBC.INPORT.ENABLE_256KB; + if (this.getSWVideoMonitor() == ChipSet.MONITOR.MONO) this.b8042InPort |= ChipSet.KBC.INPORT.MONO; - this.b8042OutPort = ChipSet.KBD_DATA.OUTPORT.NO_RESET | ChipSet.KBD_DATA.OUTPORT.A20_ON; - this.bCMOSAddr = 0; // NMI is enabled, since the ChipSet.CMOS_ADDR.NMI_DISABLE bit is not set in bCMOSAddr - this.abCMOSData = new Array(ChipSet.CMOS_ADDR.TOTAL); + this.b8042OutPort = ChipSet.KBC.OUTPORT.NO_RESET | ChipSet.KBC.OUTPORT.A20_ON; + this.bCMOSAddr = 0; // NMI is enabled, since the ChipSet.CMOS.ADDR.NMI_DISABLE bit is not set in bCMOSAddr + this.abCMOSData = new Array(ChipSet.CMOS.ADDR.TOTAL); this.initRTCDate(this.sRTCDate); this.initCMOSData(); /* @@ -1066,23 +1066,23 @@ ChipSet.prototype.initRTCDate = function(sDate) */ var date = sDate? new Date(sDate) : new Date(); - this.abCMOSData[ChipSet.CMOS_ADDR.RTC_SEC] = date.getSeconds(); - this.abCMOSData[ChipSet.CMOS_ADDR.RTC_SEC_ALRM] = 0; - this.abCMOSData[ChipSet.CMOS_ADDR.RTC_MIN] = date.getMinutes(); - this.abCMOSData[ChipSet.CMOS_ADDR.RTC_MIN_ALRM] = 0; - this.abCMOSData[ChipSet.CMOS_ADDR.RTC_HOUR] = date.getHours(); - this.abCMOSData[ChipSet.CMOS_ADDR.RTC_HOUR_ALRM] = 0; - this.abCMOSData[ChipSet.CMOS_ADDR.RTC_WEEK_DAY] = date.getDay() + 1; - this.abCMOSData[ChipSet.CMOS_ADDR.RTC_MONTH_DAY] = date.getDate(); - this.abCMOSData[ChipSet.CMOS_ADDR.RTC_MONTH] = date.getMonth() + 1; - this.abCMOSData[ChipSet.CMOS_ADDR.RTC_YEAR] = date.getFullYear() % 100; + this.abCMOSData[ChipSet.CMOS.ADDR.RTC_SEC] = date.getSeconds(); + this.abCMOSData[ChipSet.CMOS.ADDR.RTC_SEC_ALRM] = 0; + this.abCMOSData[ChipSet.CMOS.ADDR.RTC_MIN] = date.getMinutes(); + this.abCMOSData[ChipSet.CMOS.ADDR.RTC_MIN_ALRM] = 0; + this.abCMOSData[ChipSet.CMOS.ADDR.RTC_HOUR] = date.getHours(); + this.abCMOSData[ChipSet.CMOS.ADDR.RTC_HOUR_ALRM] = 0; + this.abCMOSData[ChipSet.CMOS.ADDR.RTC_WEEK_DAY] = date.getDay() + 1; + this.abCMOSData[ChipSet.CMOS.ADDR.RTC_MONTH_DAY] = date.getDate(); + this.abCMOSData[ChipSet.CMOS.ADDR.RTC_MONTH] = date.getMonth() + 1; + this.abCMOSData[ChipSet.CMOS.ADDR.RTC_YEAR] = date.getFullYear() % 100; this.nCyclesCMOSLastUpdate = -1; - this.abCMOSData[ChipSet.CMOS_ADDR.RTC_STATUSA] = 0x26; // hard-coded default; refer to ChipSet.CMOS_STATUSA.DV and ChipSet.CMOS_STATUSA.RS - this.abCMOSData[ChipSet.CMOS_ADDR.RTC_STATUSB] = ChipSet.CMOS_STATUSB.HOUR24; // default to BCD mode (ChipSet.CMOS_STATUSB.BINARY not set) - this.abCMOSData[ChipSet.CMOS_ADDR.RTC_STATUSC] = 0x00; - this.abCMOSData[ChipSet.CMOS_ADDR.RTC_STATUSD] = ChipSet.CMOS_STATUSD.VRB; + this.abCMOSData[ChipSet.CMOS.ADDR.RTC_STATUSA] = 0x26; // hard-coded default; refer to ChipSet.CMOS.STATUSA.DV and ChipSet.CMOS.STATUSA.RS + this.abCMOSData[ChipSet.CMOS.ADDR.RTC_STATUSB] = ChipSet.CMOS.STATUSB.HOUR24; // default to BCD mode (ChipSet.CMOS.STATUSB.BINARY not set) + this.abCMOSData[ChipSet.CMOS.ADDR.RTC_STATUSC] = 0x00; + this.abCMOSData[ChipSet.CMOS.ADDR.RTC_STATUSD] = ChipSet.CMOS.STATUSD.VRB; }; /** @@ -1093,14 +1093,14 @@ ChipSet.prototype.initRTCDate = function(sDate) */ ChipSet.prototype.getRTCByte = function(iRTC) { - Component.assert(iRTC >= 0 && iRTC <= ChipSet.CMOS_ADDR.RTC_STATUSD); + Component.assert(iRTC >= 0 && iRTC <= ChipSet.CMOS.ADDR.RTC_STATUSD); var b = this.abCMOSData[iRTC]; - if (iRTC < ChipSet.CMOS_ADDR.RTC_STATUSA) { + if (iRTC < ChipSet.CMOS.ADDR.RTC_STATUSA) { var f12HourValue = false; - if (iRTC == ChipSet.CMOS_ADDR.RTC_HOUR || iRTC == ChipSet.CMOS_ADDR.RTC_HOUR_ALRM) { - if (!(this.abCMOSData[ChipSet.CMOS_ADDR.RTC_STATUSB] & ChipSet.CMOS_STATUSB.HOUR24)) { + if (iRTC == ChipSet.CMOS.ADDR.RTC_HOUR || iRTC == ChipSet.CMOS.ADDR.RTC_HOUR_ALRM) { + if (!(this.abCMOSData[ChipSet.CMOS.ADDR.RTC_STATUSB] & ChipSet.CMOS.STATUSB.HOUR24)) { if (b < 12) { b = (!b? 12 : b); } else { @@ -1110,7 +1110,7 @@ ChipSet.prototype.getRTCByte = function(iRTC) f12HourValue = true; } } - if (!(this.abCMOSData[ChipSet.CMOS_ADDR.RTC_STATUSB] & ChipSet.CMOS_STATUSB.BINARY)) { + if (!(this.abCMOSData[ChipSet.CMOS.ADDR.RTC_STATUSB] & ChipSet.CMOS.STATUSB.BINARY)) { /* * We're in BCD mode, so we must convert b from BINARY to BCD. But first: * @@ -1125,12 +1125,12 @@ ChipSet.prototype.getRTCByte = function(iRTC) b = (b % 10) | ((b / 10) << 4); } } else { - if (iRTC == ChipSet.CMOS_ADDR.RTC_STATUSA) { + if (iRTC == ChipSet.CMOS.ADDR.RTC_STATUSA) { /* * HACK: Perform a mindless toggling of the "Update-In-Progress" bit, so that it's flipped * on the next read; this makes the MODEL_5170 BIOS ("POST2_RTCUP") happy. */ - this.abCMOSData[iRTC] ^= ChipSet.CMOS_STATUSA.UIP; + this.abCMOSData[iRTC] ^= ChipSet.CMOS.STATUSA.UIP; } } return b; @@ -1145,11 +1145,11 @@ ChipSet.prototype.getRTCByte = function(iRTC) */ ChipSet.prototype.setRTCByte = function(iRTC, b) { - Component.assert(iRTC >= 0 && iRTC <= ChipSet.CMOS_ADDR.RTC_STATUSD); + Component.assert(iRTC >= 0 && iRTC <= ChipSet.CMOS.ADDR.RTC_STATUSD); - if (iRTC < ChipSet.CMOS_ADDR.RTC_STATUSA) { + if (iRTC < ChipSet.CMOS.ADDR.RTC_STATUSA) { var fBCD = false; - if (!(this.abCMOSData[ChipSet.CMOS_ADDR.RTC_STATUSB] & ChipSet.CMOS_STATUSB.BINARY)) { + if (!(this.abCMOSData[ChipSet.CMOS.ADDR.RTC_STATUSB] & ChipSet.CMOS.STATUSB.BINARY)) { /* * We're in BCD mode, so we must convert b from BCD to BINARY (we assume it's valid * BCD; ie, that both nibbles contain only 0-9, not A-F). @@ -1157,7 +1157,7 @@ ChipSet.prototype.setRTCByte = function(iRTC, b) b = (b >> 4) * 10 + (b & 0xf); fBCD = true; } - if (iRTC == ChipSet.CMOS_ADDR.RTC_HOUR || iRTC == ChipSet.CMOS_ADDR.RTC_HOUR_ALRM) { + if (iRTC == ChipSet.CMOS.ADDR.RTC_HOUR || iRTC == ChipSet.CMOS.ADDR.RTC_HOUR_ALRM) { if (fBCD) { /* * If the original BCD hour was 0x81-0x92, then the previous BINARY-to-BCD conversion @@ -1168,7 +1168,7 @@ ChipSet.prototype.setRTCByte = function(iRTC, b) b += 0x30; } } - if (!(this.abCMOSData[ChipSet.CMOS_ADDR.RTC_STATUSB] & ChipSet.CMOS_STATUSB.HOUR24)) { + if (!(this.abCMOSData[ChipSet.CMOS.ADDR.RTC_STATUSB] & ChipSet.CMOS.STATUSB.HOUR24)) { if (b <= 12) { b = (b == 12? 0 : b); } else { @@ -1209,19 +1209,19 @@ ChipSet.prototype.updateRTCDate = function() */ Component.assert(nSecondsDelta <= 1); if (nSecondsDelta) { - if (++this.abCMOSData[ChipSet.CMOS_ADDR.RTC_SEC] >= 60) { - this.abCMOSData[ChipSet.CMOS_ADDR.RTC_SEC] = 0; - if (++this.abCMOSData[ChipSet.CMOS_ADDR.RTC_MIN] >= 60) { - this.abCMOSData[ChipSet.CMOS_ADDR.RTC_MIN] = 0; - if (++this.abCMOSData[ChipSet.CMOS_ADDR.RTC_HOUR] >= 24) { - this.abCMOSData[ChipSet.CMOS_ADDR.RTC_HOUR] = 0; - this.abCMOSData[ChipSet.CMOS_ADDR.RTC_WEEK_DAY] = (this.abCMOSData[ChipSet.CMOS_ADDR.RTC_WEEK_DAY] % 7) + 1; - var nDayMax = usr.getMonthDays(this.abCMOSData[ChipSet.CMOS_ADDR.RTC_MONTH], this.abCMOSData[ChipSet.CMOS_ADDR.RTC_YEAR]); - if (++this.abCMOSData[ChipSet.CMOS_ADDR.RTC_MONTH_DAY] > nDayMax) { - this.abCMOSData[ChipSet.CMOS_ADDR.RTC_MONTH_DAY] = 1; - if (++this.abCMOSData[ChipSet.CMOS_ADDR.RTC_MONTH] > 12) { - this.abCMOSData[ChipSet.CMOS_ADDR.RTC_MONTH] = 1; - this.abCMOSData[ChipSet.CMOS_ADDR.RTC_YEAR] = (this.abCMOSData[ChipSet.CMOS_ADDR.RTC_YEAR] + 1) % 100; + if (++this.abCMOSData[ChipSet.CMOS.ADDR.RTC_SEC] >= 60) { + this.abCMOSData[ChipSet.CMOS.ADDR.RTC_SEC] = 0; + if (++this.abCMOSData[ChipSet.CMOS.ADDR.RTC_MIN] >= 60) { + this.abCMOSData[ChipSet.CMOS.ADDR.RTC_MIN] = 0; + if (++this.abCMOSData[ChipSet.CMOS.ADDR.RTC_HOUR] >= 24) { + this.abCMOSData[ChipSet.CMOS.ADDR.RTC_HOUR] = 0; + this.abCMOSData[ChipSet.CMOS.ADDR.RTC_WEEK_DAY] = (this.abCMOSData[ChipSet.CMOS.ADDR.RTC_WEEK_DAY] % 7) + 1; + var nDayMax = usr.getMonthDays(this.abCMOSData[ChipSet.CMOS.ADDR.RTC_MONTH], this.abCMOSData[ChipSet.CMOS.ADDR.RTC_YEAR]); + if (++this.abCMOSData[ChipSet.CMOS.ADDR.RTC_MONTH_DAY] > nDayMax) { + this.abCMOSData[ChipSet.CMOS.ADDR.RTC_MONTH_DAY] = 1; + if (++this.abCMOSData[ChipSet.CMOS.ADDR.RTC_MONTH] > 12) { + this.abCMOSData[ChipSet.CMOS.ADDR.RTC_MONTH] = 1; + this.abCMOSData[ChipSet.CMOS.ADDR.RTC_YEAR] = (this.abCMOSData[ChipSet.CMOS.ADDR.RTC_YEAR] + 1) % 100; } } } @@ -1249,7 +1249,7 @@ ChipSet.prototype.initCMOSData = function() * Make sure all the "checksummed" CMOS bytes get initialized (not just the handful we set below) to ensure * that the checksum will be valid. */ - for (var iCMOS = ChipSet.CMOS_ADDR.DIAG; iCMOS < ChipSet.CMOS_ADDR.CHKSUM_HI; iCMOS++) { + for (var iCMOS = ChipSet.CMOS.ADDR.DIAG; iCMOS < ChipSet.CMOS.ADDR.CHKSUM_HI; iCMOS++) { this.abCMOSData[iCMOS] = 0; } @@ -1263,29 +1263,21 @@ ChipSet.prototype.initCMOSData = function() * incomplete; for example, does the FDC component have a way of specifying the number of drives, and do we honor that? * I think not.... */ - this.abCMOSData[ChipSet.CMOS_ADDR.EQUIP] = this.sw1 & (ChipSet.PPI_SW.MONITOR.MASK | ChipSet.PPI_SW.COPROC | ChipSet.PPI_SW.FDRIVE.IPL | ChipSet.PPI_SW.FDRIVE.MASK); + this.abCMOSData[ChipSet.CMOS.ADDR.EQUIP] = this.sw1 & (ChipSet.PPI_SW.MONITOR.MASK | ChipSet.PPI_SW.COPROC | ChipSet.PPI_SW.FDRIVE.IPL | ChipSet.PPI_SW.FDRIVE.MASK); - /* - * TODO: We default all floppy diskette drives to High Capacity, but MODEL_5170 machines will need more control - * over settings like this. - */ - var bDisketteTypes = 0; - var cDisketteDrives = this.getSW1FloppyDrives(); - if (cDisketteDrives > 0) bDisketteTypes |= ChipSet.CMOS_FDRIVE.D0_HC; - if (cDisketteDrives > 1) bDisketteTypes |= ChipSet.CMOS_FDRIVE.D1_HC; - this.abCMOSData[ChipSet.CMOS_ADDR.FDRIVE] = bDisketteTypes; + this.abCMOSData[ChipSet.CMOS.ADDR.FDRIVE] = (this.getSWFloppyDriveType(0) << 4) | this.getSWFloppyDriveType(1); var wBaseMemKb = this.getSWMemorySize(); - this.abCMOSData[ChipSet.CMOS_ADDR.BASEMEM_LO] = wBaseMemKb & 0xff; - this.abCMOSData[ChipSet.CMOS_ADDR.BASEMEM_HI] = wBaseMemKb >> 8; + this.abCMOSData[ChipSet.CMOS.ADDR.BASEMEM_LO] = wBaseMemKb & 0xff; + this.abCMOSData[ChipSet.CMOS.ADDR.BASEMEM_HI] = wBaseMemKb >> 8; /* * The final step is calculating the CMOS checksum, which we then store into the CMOS as a courtesy, so that the * user doesn't get unnecessary CMOS errors. */ var wChecksum = this.getCMOSChecksum(); - this.abCMOSData[ChipSet.CMOS_ADDR.CHKSUM_LO] = wChecksum & 0xff; - this.abCMOSData[ChipSet.CMOS_ADDR.CHKSUM_HI] = wChecksum >> 8; + this.abCMOSData[ChipSet.CMOS.ADDR.CHKSUM_LO] = wChecksum & 0xff; + this.abCMOSData[ChipSet.CMOS.ADDR.CHKSUM_HI] = wChecksum >> 8; }; /** @@ -1303,7 +1295,7 @@ ChipSet.prototype.initCMOSData = function() ChipSet.prototype.getCMOSChecksum = function() { var wChecksum = 0; - for (var iCMOS = ChipSet.CMOS_ADDR.FDRIVE; iCMOS < ChipSet.CMOS_ADDR.CHKSUM_HI; iCMOS++) { + for (var iCMOS = ChipSet.CMOS.ADDR.FDRIVE; iCMOS < ChipSet.CMOS.ADDR.CHKSUM_HI; iCMOS++) { wChecksum += this.abCMOSData[iCMOS]; } return wChecksum; @@ -1643,26 +1635,44 @@ ChipSet.prototype.getSWMemorySize = function(fInit) }; /** - * getSW1FloppyDrives(fInit) + * getSWFloppyDrives(fInit) * * @this {ChipSet} * @param {boolean|undefined} [fInit] is true for init switch value(s) only, current value(s) otherwise * @return {number} number of floppy drives specified by SW1 (range is 0 to 4) */ -ChipSet.prototype.getSW1FloppyDrives = function(fInit) +ChipSet.prototype.getSWFloppyDrives = function(fInit) { var sw1 = (fInit? this.sw1Init : this.sw1); return ((this.model != ChipSet.MODEL_5150) || (sw1 & ChipSet.PPI_SW.FDRIVE.IPL))? ((sw1 & ChipSet.PPI_SW.FDRIVE.MASK) >> ChipSet.PPI_SW.FDRIVE.SHIFT) + 1 : 0; }; /** - * getSW1VideoMonitor(fInit) + * getSWFloppyDriveType(iDrive) + * + * @this {ChipSet} + * @param {number} iDrive (0-based) + * @return {number} one of the ChipSet.FDRIVE values (ie, NONE: 0, DSDD: 1, DSHC: 2) + */ +ChipSet.prototype.getSWFloppyDriveType = function(iDrive) +{ + /* + * TODO: For MODEL_5170, we default all floppy drive types to High Capacity, but more control would be nice. + */ + if (iDrive < this.getSWFloppyDrives()) { + return (this.model < ChipSet.MODEL_5170? ChipSet.FDRIVE.DSDD : ChipSet.FDRIVE.DSHC); + } + return ChipSet.FDRIVE.NONE; +}; + +/** + * getSWVideoMonitor(fInit) * * @this {ChipSet} * @param {boolean|undefined} [fInit] is true for init switch value(s) only, current value(s) otherwise * @return {number} one of ChipSet.MONITOR.* */ -ChipSet.prototype.getSW1VideoMonitor = function(fInit) +ChipSet.prototype.getSWVideoMonitor = function(fInit) { var sw1 = (fInit? this.sw1Init : this.sw1); return (sw1 & ChipSet.PPI_SW.MONITOR.MASK) >> ChipSet.PPI_SW.MONITOR.SHIFT; @@ -1786,8 +1796,8 @@ ChipSet.prototype.updateSwitchDesc = function() if (controlDesc !== undefined) { var sHTML = ""; sHTML += this.getSWMemorySize(true) + "Kb"; - sHTML += ", " + asMonitorTypes[this.getSW1VideoMonitor(true)] + " Monitor"; - sHTML += ", " + this.getSW1FloppyDrives(true) + " Floppy Drives"; + sHTML += ", " + asMonitorTypes[this.getSWVideoMonitor(true)] + " Monitor"; + sHTML += ", " + this.getSWFloppyDrives(true) + " Floppy Drives"; if (this.sw1 !== undefined && this.sw1 != this.sw1Init || this.sw2 !== undefined && this.sw2 != this.sw2Init) sHTML += " (Reset required)"; controlDesc.innerHTML = sHTML; @@ -3397,7 +3407,7 @@ ChipSet.prototype.inPPIC = function(port, addrFrom) /* * If you ever wanted to simulate I/O channel errors or R/W memory parity errors, you could - * add either PPI_C_IO_CHANNEL_CHK (0x40) or PPI_C_RW_PARITY_CHK (0x80) to the return value (b). + * add either PPI_C.IO_CHANNEL_CHK (0x40) or PPI_C.RW_PARITY_CHK (0x80) to the return value (b). */ if (this.model == ChipSet.MODEL_5150) { if (this.bPPIB & ChipSet.PPI_B.ENABLE_SW2) { @@ -3486,7 +3496,7 @@ ChipSet.prototype.in8042OutBuff = function(port, addrFrom) { var b = this.b8042OutBuff; this.messagePort(port, null, addrFrom, "8042_OUTBUFF", ChipSet.MESSAGE_CHIPSET, b); - this.b8042Status &= ~(ChipSet.KBD_STATUS.OUTBUFF_FULL | ChipSet.KBD_STATUS.OUTBUFF_DELAY); + this.b8042Status &= ~(ChipSet.KBC.STATUS.OUTBUFF_FULL | ChipSet.KBC.STATUS.OUTBUFF_DELAY); var bNext = this.kbd && this.kbd.readScanCode(true); if (bNext) this.set8042OutBuff(bNext); return b; @@ -3508,16 +3518,16 @@ ChipSet.prototype.out8042InBuffData = function(port, bOut, addrFrom) { this.messagePort(port, bOut, addrFrom, "8042_INBUF.DATA", ChipSet.MESSAGE_CHIPSET); - if (this.b8042Status & ChipSet.KBD_STATUS.CMD_FLAG) { + if (this.b8042Status & ChipSet.KBC.STATUS.CMD_FLAG) { switch (this.b8042InBuff) { - case ChipSet.KBD_CMD.WRITE_CMD: + case ChipSet.KBC.CMD.WRITE_CMD: this.b8042CmdData = bOut; - Component.assert(ChipSet.KBD_DATA.CMD.SYS_FLAG === ChipSet.KBD_STATUS.SYS_FLAG); - this.b8042Status = (this.b8042Status & ~ChipSet.KBD_STATUS.SYS_FLAG) | (bOut & ChipSet.KBD_DATA.CMD.SYS_FLAG); + Component.assert(ChipSet.KBC.DATA.CMD.SYS_FLAG === ChipSet.KBC.STATUS.SYS_FLAG); + this.b8042Status = (this.b8042Status & ~ChipSet.KBC.STATUS.SYS_FLAG) | (bOut & ChipSet.KBC.DATA.CMD.SYS_FLAG); break; - case ChipSet.KBD_CMD.WRITE_OUTPORT: + case ChipSet.KBC.CMD.WRITE_OUTPORT: this.set8042OutPort(bOut); break; @@ -3586,13 +3596,13 @@ ChipSet.prototype.out8042InBuffData = function(port, bOut, addrFrom) * error, but "TEST.21" assumes that it is. */ default: - this.b8042CmdData &= ~ChipSet.KBD_DATA.CMD.NO_CLOCK; + this.b8042CmdData &= ~ChipSet.KBC.DATA.CMD.NO_CLOCK; if (this.kbd) this.set8042OutBuff(this.kbd.sendCmd(bOut)); break; } } this.b8042InBuff = bOut; - this.b8042Status &= ~ChipSet.KBD_STATUS.CMD_FLAG; + this.b8042Status &= ~ChipSet.KBC.STATUS.CMD_FLAG; }; /** @@ -3609,12 +3619,12 @@ ChipSet.prototype.in8042RWReg = function(port, addrFrom) * Normally, we return whatever was last written to this port, but we do need to mask the * two upper-most bits (KBD_RWREG.PARITY_ERR), because we never want to report a parity error. */ - var b = this.bPPIB & ~ChipSet.KBD_RWREG.PARITY_ERR; + var b = this.bPPIB & ~ChipSet.KBC.RWREG.PARITY_ERR; this.messagePort(port, null, addrFrom, "8042_RWREG", ChipSet.MESSAGE_CHIPSET, b); /* * "TEST.09" of the MODEL_5170 BIOS expects the following bit ("REFRESH_BIT") to alternate, so we oblige. */ - this.bPPIB ^= ChipSet.KBD_RWREG.REFRESH_BIT; + this.bPPIB ^= ChipSet.KBC.RWREG.REFRESH_BIT; return b; }; @@ -3659,9 +3669,9 @@ ChipSet.prototype.in8042Status = function(port, addrFrom) * If longer delays are needed down the road, we may need to set a delay count in the upper (hidden) * bits of b8042Status, instead of using a single "OUTBUFF_DELAY" bit. */ - if (this.b8042Status & ChipSet.KBD_STATUS.OUTBUFF_DELAY) { - this.b8042Status |= ChipSet.KBD_STATUS.OUTBUFF_FULL; - this.b8042Status &= ~ChipSet.KBD_STATUS.OUTBUFF_DELAY; + if (this.b8042Status & ChipSet.KBC.STATUS.OUTBUFF_DELAY) { + this.b8042Status |= ChipSet.KBC.STATUS.OUTBUFF_FULL; + this.b8042Status &= ~ChipSet.KBC.STATUS.OUTBUFF_DELAY; } return b; }; @@ -3681,34 +3691,34 @@ ChipSet.prototype.in8042Status = function(port, addrFrom) ChipSet.prototype.out8042InBuffCmd = function(port, bOut, addrFrom) { this.messagePort(port, bOut, addrFrom, "8042_INBUFF.CMD", ChipSet.MESSAGE_CHIPSET); - Component.assert(!(this.b8042Status & ChipSet.KBD_STATUS.INBUFF_FULL)); + Component.assert(!(this.b8042Status & ChipSet.KBC.STATUS.INBUFF_FULL)); this.b8042InBuff = bOut; - this.b8042Status |= ChipSet.KBD_STATUS.CMD_FLAG; + this.b8042Status |= ChipSet.KBC.STATUS.CMD_FLAG; var bPulseBits = 0; - if (this.b8042InBuff >= ChipSet.KBD_CMD.PULSE_OUTPORT) { + if (this.b8042InBuff >= ChipSet.KBC.CMD.PULSE_OUTPORT) { bPulseBits = (this.b8042InBuff ^ 0xf); /* * Now that we have isolated the bit(s) to pulse, map all pulse commands to KBD_CMD.PULSE_OUTPORT */ - this.b8042InBuff = ChipSet.KBD_CMD.PULSE_OUTPORT; + this.b8042InBuff = ChipSet.KBC.CMD.PULSE_OUTPORT; } switch (this.b8042InBuff) { - case ChipSet.KBD_CMD.WRITE_CMD: // 0x60 - case ChipSet.KBD_CMD.WRITE_OUTPORT: // 0xD1 + case ChipSet.KBC.CMD.WRITE_CMD: // 0x60 + case ChipSet.KBC.CMD.WRITE_OUTPORT: // 0xD1 /* * No further action required for this first group of commands; more data is expected via out8042InBuffData() */ break; - case ChipSet.KBD_CMD.READ_INPORT: // 0xC0 + case ChipSet.KBC.CMD.READ_INPORT: // 0xC0 this.set8042OutBuff(this.b8042InPort); break; - case ChipSet.KBD_CMD.DISABLE_KBD: // 0xAD - this.b8042CmdData |= ChipSet.KBD_DATA.CMD.NO_CLOCK; + case ChipSet.KBC.CMD.DISABLE_KBD: // 0xAD + this.b8042CmdData |= ChipSet.KBC.DATA.CMD.NO_CLOCK; if (DEBUG) this.messageDebugger("keyboard disabled", ChipSet.MESSAGE_KBD); /* * TODO: Determine where to honor KBD_DATA.CMD.NO_CLOCK; note that the MODEL_5170 BIOS calls "KBD_RESET" (F000:17D2) @@ -3716,24 +3726,24 @@ ChipSet.prototype.out8042InBuffCmd = function(port, bOut, addrFrom) */ break; - case ChipSet.KBD_CMD.ENABLE_KBD: // 0xAE - this.b8042CmdData &= ~ChipSet.KBD_DATA.CMD.NO_CLOCK; + case ChipSet.KBC.CMD.ENABLE_KBD: // 0xAE + this.b8042CmdData &= ~ChipSet.KBC.DATA.CMD.NO_CLOCK; if (DEBUG) this.messageDebugger("keyboard re-enabled", ChipSet.MESSAGE_KBD); break; - case ChipSet.KBD_CMD.SELF_TEST: // 0xAA + case ChipSet.KBC.CMD.SELF_TEST: // 0xAA if (this.kbd) this.kbd.shiftScanCode(true); - this.b8042CmdData |= ChipSet.KBD_DATA.CMD.NO_CLOCK; + this.b8042CmdData |= ChipSet.KBC.DATA.CMD.NO_CLOCK; if (DEBUG) this.messageDebugger("keyboard disabled on reset", ChipSet.MESSAGE_KBD); - this.set8042OutBuff(ChipSet.KBD_DATA.SELF_TEST.OK); - this.set8042OutPort(ChipSet.KBD_DATA.OUTPORT.NO_RESET | ChipSet.KBD_DATA.OUTPORT.A20_ON); + this.set8042OutBuff(ChipSet.KBC.DATA.SELF_TEST.OK); + this.set8042OutPort(ChipSet.KBC.OUTPORT.NO_RESET | ChipSet.KBC.OUTPORT.A20_ON); break; - case ChipSet.KBD_CMD.READ_TEST: // 0xE0 - this.set8042OutBuff((this.b8042CmdData & ChipSet.KBD_DATA.CMD.NO_CLOCK)? 0 : ChipSet.KBD_DATA.TESTPORT.KBD_CLOCK); + case ChipSet.KBC.CMD.READ_TEST: // 0xE0 + this.set8042OutBuff((this.b8042CmdData & ChipSet.KBC.DATA.CMD.NO_CLOCK)? 0 : ChipSet.KBC.TESTPORT.KBD_CLOCK); break; - case ChipSet.KBD_CMD.PULSE_OUTPORT: // 0xF0-0xFF + case ChipSet.KBC.CMD.PULSE_OUTPORT: // 0xF0-0xFF if (bPulseBits & 0x1) { /* * Bit 0 of the 8042's output port is connected to RESET. If it's pulsed, the processor resets. @@ -3763,8 +3773,8 @@ ChipSet.prototype.set8042OutBuff = function(b) { if (b >= 0) { this.b8042OutBuff = b; - this.b8042Status &= ~ChipSet.KBD_STATUS.OUTBUFF_FULL; - this.b8042Status |= ChipSet.KBD_STATUS.OUTBUFF_DELAY; + this.b8042Status &= ~ChipSet.KBC.STATUS.OUTBUFF_FULL; + this.b8042Status |= ChipSet.KBC.STATUS.OUTBUFF_DELAY; } }; @@ -3777,8 +3787,8 @@ ChipSet.prototype.set8042OutBuff = function(b) ChipSet.prototype.set8042OutPort = function(b) { this.b8042OutPort = b; - this.bus.setA20(!!(b & ChipSet.KBD_DATA.OUTPORT.A20_ON)); - if (!(b & ChipSet.KBD_DATA.OUTPORT.NO_RESET)) { + this.bus.setA20(!!(b & ChipSet.KBC.OUTPORT.A20_ON)); + if (!(b & ChipSet.KBC.OUTPORT.NO_RESET)) { /* * Bit 0 of the 8042's output port is connected to RESET. Normally, it's "pulsed" with the * KBD_CMD.PULSE_OUTPORT command, so if a RESET is detected via this command, we should try to @@ -3818,7 +3828,7 @@ ChipSet.prototype.outCMOSAddr = function(port, bOut, addrFrom) { this.messagePort(port, bOut, addrFrom, "CMOS_ADDR", ChipSet.MESSAGE_CHIPSET); this.bCMOSAddr = bOut; - this.bNMI = (bOut & ChipSet.CMOS_ADDR.NMI_DISABLE)? ChipSet.NMI.DISABLE : ChipSet.NMI.ENABLE; + this.bNMI = (bOut & ChipSet.CMOS.ADDR.NMI_DISABLE)? ChipSet.NMI.DISABLE : ChipSet.NMI.ENABLE; }; /** @@ -3831,8 +3841,8 @@ ChipSet.prototype.outCMOSAddr = function(port, bOut, addrFrom) */ ChipSet.prototype.inCMOSData = function(port, addrFrom) { - var bAddr = this.bCMOSAddr & ChipSet.CMOS_ADDR.MASK; - var bIn = (bAddr <= ChipSet.CMOS_ADDR.RTC_STATUSD? this.getRTCByte(bAddr) : this.abCMOSData[bAddr]); + var bAddr = this.bCMOSAddr & ChipSet.CMOS.ADDR.MASK; + var bIn = (bAddr <= ChipSet.CMOS.ADDR.RTC_STATUSD? this.getRTCByte(bAddr) : this.abCMOSData[bAddr]); this.messagePort(port, null, addrFrom, "CMOS_DATA[" + str.toHexByte(bAddr) + "]", ChipSet.MESSAGE_CHIPSET, bIn); return bIn; }; @@ -3847,9 +3857,9 @@ ChipSet.prototype.inCMOSData = function(port, addrFrom) */ ChipSet.prototype.outCMOSData = function(port, bOut, addrFrom) { - var bAddr = this.bCMOSAddr & ChipSet.CMOS_ADDR.MASK; + var bAddr = this.bCMOSAddr & ChipSet.CMOS.ADDR.MASK; this.messagePort(port, bOut, addrFrom, "CMOS_DATA[" + str.toHexByte(bAddr) + "]", ChipSet.MESSAGE_CHIPSET); - this.abCMOSData[bAddr] = (bAddr <= ChipSet.CMOS_ADDR.RTC_STATUSD? this.setRTCByte(bAddr, bOut) : bOut); + this.abCMOSData[bAddr] = (bAddr <= ChipSet.CMOS.ADDR.RTC_STATUSD? this.setRTCByte(bAddr, bOut) : bOut); }; /** @@ -3896,6 +3906,50 @@ ChipSet.prototype.outNMI = function(port, bOut, addrFrom) this.bNMI = bOut; }; +/** + * inHFCCtrl(port, addrFrom) + * + * @this {ChipSet} + * @param {number} port (0x1F4) + * @param {number|undefined} addrFrom (not defined if the Debugger is trying to read the specified port) + * @return {number} simulated port value + */ +ChipSet.prototype.inHFCCtrl = function(port, addrFrom) +{ + var b = this.regsHFCombo.bCtrl; + this.messagePort(port, null, addrFrom, "HFC_CTRL", ChipSet.MESSAGE_CHIPSET, b); + return b; +}; + +/** + * outHFCCtrl(port, bOut, addrFrom) + * + * @this {ChipSet} + * @param {number} port (0x1F4) + * @param {number} bOut + * @param {number|undefined} addrFrom (not defined if the Debugger is trying to write the specified port) + */ +ChipSet.prototype.outHFCCtrl = function(port, bOut, addrFrom) +{ + this.messagePort(port, bOut, addrFrom, "HFC_CTRL", ChipSet.MESSAGE_CHIPSET); + this.regsHFCombo.bCtrl = bOut; +}; + +/** + * inHFCStatus(port, addrFrom) + * + * @this {ChipSet} + * @param {number} port (0x1F7) + * @param {number|undefined} addrFrom (not defined if the Debugger is trying to read the specified port) + * @return {number} simulated port value + */ +ChipSet.prototype.inHFCStatus = function(port, addrFrom) +{ + var b = this.regsHFCombo.bStatus; + this.messagePort(port, null, addrFrom, "HFC_STATUS", ChipSet.MESSAGE_CHIPSET, b); + return b; +}; + /** * parseSwitches(s, def) * @@ -4076,7 +4130,8 @@ ChipSet.aPortInput5170 = { 0xCC: /** @this {ChipSet} */ function(port, addrFrom) { return this.inDMAChannelAddr(ChipSet.DMA1.INDEX, 3, port, addrFrom); }, 0xCE: /** @this {ChipSet} */ function(port, addrFrom) { return this.inDMAChannelCount(ChipSet.DMA1.INDEX, 3, port, addrFrom); }, 0xD0: /** @this {ChipSet} */ function(port, addrFrom) { return this.inDMAStatus(ChipSet.DMA1.INDEX, port, addrFrom); }, - 0x1F7: /** @this {ChipSet} */ function(port, addrFrom) { return 0x7F; } // refer to comments regarding HFCOMBO.STATUS + 0x1F4: ChipSet.prototype.inHFCCtrl, // refer to comments regarding HFCOMBO.CTRL + 0x1F7: ChipSet.prototype.inHFCStatus // refer to comments regarding HFCOMBO.STATUS }; /* @@ -4150,7 +4205,8 @@ ChipSet.aPortOutput5170 = { 0xD4: /** @this {ChipSet} */ function(port, bOut, addrFrom) { this.outDMAMask(ChipSet.DMA1.INDEX, port, bOut, addrFrom); }, 0xD6: /** @this {ChipSet} */ function(port, bOut, addrFrom) { this.outDMAMode(ChipSet.DMA1.INDEX, port, bOut, addrFrom); }, 0xD8: /** @this {ChipSet} */ function(port, bOut, addrFrom) { this.outDMAIndex(ChipSet.DMA1.INDEX, port, bOut, addrFrom); }, - 0xDA: /** @this {ChipSet} */ function(port, bOut, addrFrom) { this.outDMAClear(ChipSet.DMA1.INDEX, port, bOut, addrFrom); } + 0xDA: /** @this {ChipSet} */ function(port, bOut, addrFrom) { this.outDMAClear(ChipSet.DMA1.INDEX, port, bOut, addrFrom); }, + 0x1F4: ChipSet.prototype.outHFCCtrl // refer to comments regarding HFCOMBO.CTRL }; /** diff --git a/my_modules/pcjs-client/lib/cpu.js b/my_modules/pcjs-client/lib/cpu.js index 584e4c825..f5072f0f9 100644 --- a/my_modules/pcjs-client/lib/cpu.js +++ b/my_modules/pcjs-client/lib/cpu.js @@ -152,7 +152,7 @@ Component.subclass(Component, CPU); */ CPU.YIELDS_PER_SECOND = 30; CPU.VIDEO_UPDATES_PER_SECOND = 60; // WARNING: if you change this, beware of side-effects in the Video component -CPU.STATUS_UPDATES_PER_SECOND = 5; +CPU.STATUS_UPDATES_PER_SECOND = 2; /** * initBus(cmp, bus, cpu, dbg) diff --git a/my_modules/pcjs-client/lib/debugger.js b/my_modules/pcjs-client/lib/debugger.js index 3dd863d55..ce6bf2767 100644 --- a/my_modules/pcjs-client/lib/debugger.js +++ b/my_modules/pcjs-client/lib/debugger.js @@ -1518,14 +1518,15 @@ if (DEBUGGER) { }; /** - * stepCPU(nCycles, fRegs) + * stepCPU(nCycles, fRegs, fUpdateCPU) * * @this {Debugger} * @param {number} nCycles (0 for one instruction without checking breakpoints) * @param {boolean} [fRegs] is true to display registers after step (default is false) + * @param {boolean} [fUpdateCPU] is false to disable calls to updateCPU() (default is true) * @return {boolean} */ - Debugger.prototype.stepCPU = function(nCycles, fRegs) + Debugger.prototype.stepCPU = function(nCycles, fRegs, fUpdateCPU) { if (!this.isCPUAvail()) return false; @@ -1556,9 +1557,11 @@ if (DEBUGGER) { /* * Because we called cpu.stepCPU() and not cpu.runCPU(), we must nudge the cpu's update code, - * and then update our own state. + * and then update our own state. Normally, the only time fUpdateCPU will be false is when doStep() + * is calling us in a loop, in which case it will perform its own updateCPU() when it's done. */ - this.cpu.updateCPU(); + if (fUpdateCPU !== false) this.cpu.updateCPU(); + this.updateStatus(!fRegs); return (this.nCycles > 0); }; @@ -1593,7 +1596,6 @@ if (DEBUGGER) { if (fStep || this.fProcStep == 1) this.doUnassemble(); else { - // if (fStep === false) this.println(); this.doRegisters(); } }; @@ -1768,7 +1770,9 @@ if (DEBUGGER) { if (this.nCycles) { var msTotal = ms - this.msStart; var nCyclesPerSecond = (msTotal > 0? Math.round(this.nCycles * 1000 / msTotal) : 0); - sStopped += " (" + this.cInstructions + " ops, " + this.nCycles + " cycles, " + msTotal + "ms, " + nCyclesPerSecond + "hz)"; + sStopped += " ("; + if (this.checksEnabled()) sStopped += this.cInstructions + " ops, "; + sStopped += this.nCycles + " cycles, " + msTotal + " ms, " + nCyclesPerSecond + " hz)"; if (MAXDEBUG && this.chipset) { var i, c, n; for (i = 0; i < this.chipset.acInterrupts.length; i++) { @@ -4069,7 +4073,9 @@ if (DEBUGGER) { this.println("updated registers:"); } } - this.println(this.getRegStr(fProt)); + + this.println('\n' + this.getRegStr(fProt)); + if (fIns) { this.aAddrNextCode = this.newAddr(this.cpu.regIP, this.cpu.segCS.sel); this.doUnassemble(this.hexAddr(this.aAddrNextCode)); @@ -4219,9 +4225,15 @@ if (DEBUGGER) { web.onCountRepeat( count, function onCountStep() { - return dbg.setBusy(true) && dbg.stepCPU(nCycles, fRegs); + return dbg.setBusy(true) && dbg.stepCPU(nCycles, fRegs, false); }, function onCountStepComplete() { + /* + * We explicitly called stepCPU() with fUpdateCPU === false, because repeatedly + * calling updateCPU() is very slow, so once the repeat count has been exhausted, + * we need to perform a final updateCPU(). + */ + dbg.cpu.updateCPU(); dbg.setBusy(false); } ); diff --git a/my_modules/pcjs-client/lib/fdc.js b/my_modules/pcjs-client/lib/fdc.js index 5eec07659..c7ae152d6 100644 --- a/my_modules/pcjs-client/lib/fdc.js +++ b/my_modules/pcjs-client/lib/fdc.js @@ -44,6 +44,62 @@ if (typeof module !== 'undefined') { var State = require("./state"); } +/* + * FDC Terms + * + * C Cylinder Number the current or selected cylinder number + * + * D Data the data pattern to be written to a sector + * + * DS Drive Select the selected driver number encoded the same as bits 0 and 1 of the Digital Output + * Register (DOR); eg, DS0, DS1, DS2, or DS3 + * + * DTL Data Length when N is 00, DTL is the data length to be read from or written to a sector + * + * EOT End Of Track the final sector number on a cylinder + * + * GPL Gap Length the length of gap 3 (spacing between sectors excluding the VCO synchronous field) + * + * H Head Address the head number, either 0 or 1, as specified in the ID field + * + * HD Head the selected head number, 0 or 1 (H = HD in all command words) + * + * HLT Head Load Time the head load time in the selected drive (2 to 256 milliseconds in 2-millisecond + * increments for the 1.2M-byte drive and 4 to 512 milliseconds in 4 millisecond increments + * for the 320K-byte drive) + * + * HUT Head Unload Time the head unload time after a read or write operation (0 to 240 milliseconds in + * 16-millisecond increments for the 1.2M-byte drive and 0 to 480 milliseconds in + * 32-millisecond increments for the 320K-byte drive) + * + * MF FM or MFM Mode 0 selects FM mode and 1 selects MFM (MFM is selected only if it is implemented) + * + * MT Multitrack 1 selects multitrack operation (Both HD0 and HD1 will be read or written) + * + * N Number the number of data bytes written in a sector + * + * NCN New Cylinder the new cylinder number for a seek operation + * + * ND Non-Data Mode indicates an operation in the non-data mode + * + * PCN Present Cylinder Number the cylinder number at the completion of a Sense interrupt status command + * (present position of the head) + * + * R Record the sector number to be read or written + * + * SC Sectors Per Cylinder the number of sectors per cylinder + * + * SK Skip this stands for skip deleted-data address mark + * + * SRT Stepping Rate this 4 bit byte indicates the stepping rate for the diskette drive as follows: + * 1.2M-Byte Diskette Drive: 1111=1ms, 1110=2ms, 1101=3ms + * 320K-Byte Diskette Drive: 1111=2ms, 1110=4ms, 1101=6ms + * + * STP STP Scan Test if STP is 1, the data in contiguous sectors is compared with the data sent + * by the processor during a scan operation; if STP is 2, then alternate sections + * are read and compared + */ + /** * FDC(parmsFDC) * @@ -136,28 +192,29 @@ FDC.BIOS.DISKETTE_INT = 0x13; FDC.DEFAULT_DRIVE_NAME = "Floppy Drive"; /* - * FDC Output Register (0x3F2, write-only) + * FDC Digital Output Register (DOR) (0x3F2, write-only) * - * NOTE: A drive's MOTOR bit must be ON before the the drive can be selected. Motor start time is 500ms. + * NOTE: Reportedly, a drive's MOTOR bit had to be ON before the the drive could be selected, so outFDCOutput() + * verifies that. Also, motor start time for early model drives was 500ms, but we make no attempt to simulate that. * * On the MODEL_5170 "PC AT Fixed Disk and Diskette Drive Adapter", this port is called the Digital Output Register * or DOR. It uses the same bit definitions as the original FDC Output Register, except that only two diskette drives - * are supported, hence bit 1 is always 0 (FDC.REG_OUTPUT.SELECT_C and FDC.REG_OUTPUT.SELECT_D are not supported) - * and bits 6 and 7 are unused (FDC.REG_OUTPUT.MOTOR_C and FDC.REG_OUTPUT.MOTOR_D are not supported). + * are supported, hence bit 1 is always 0 (ie, FDC.REG_OUTPUT.DS2 and FDC.REG_OUTPUT.DS3 are not supported) and bits + * 6 and 7 are unused (FDC.REG_OUTPUT.MOTOR_D2 and FDC.REG_OUTPUT.MOTOR_D3 are not supported). */ FDC.REG_OUTPUT = {}; FDC.REG_OUTPUT.PORT = 0x3F2; -FDC.REG_OUTPUT.SELECT = 0x03; -FDC.REG_OUTPUT.SELECT_A = 0x00; -FDC.REG_OUTPUT.SELECT_B = 0x01; -FDC.REG_OUTPUT.SELECT_C = 0x02; // reserved on the MODEL_5170 -FDC.REG_OUTPUT.SELECT_D = 0x03; // reserved on the MODEL_5170 +FDC.REG_OUTPUT.DS = 0x03; // drive select bits +FDC.REG_OUTPUT.DS0 = 0x00; +FDC.REG_OUTPUT.DS1 = 0x01; +FDC.REG_OUTPUT.DS2 = 0x02; // reserved on the MODEL_5170 +FDC.REG_OUTPUT.DS3 = 0x03; // reserved on the MODEL_5170 FDC.REG_OUTPUT.ENABLE = 0x04; // clearing this bit resets the FDC FDC.REG_OUTPUT.INT_ENABLE = 0x08; // enables both FDC and DMA (Channel 2) interrupt requests (IRQ 6) -FDC.REG_OUTPUT.MOTOR_A = 0x10; -FDC.REG_OUTPUT.MOTOR_B = 0x20; -FDC.REG_OUTPUT.MOTOR_C = 0x40; // reserved on the MODEL_5170 -FDC.REG_OUTPUT.MOTOR_D = 0x80; // reserved on the MODEL_5170 +FDC.REG_OUTPUT.MOTOR_D0 = 0x10; +FDC.REG_OUTPUT.MOTOR_D1 = 0x20; +FDC.REG_OUTPUT.MOTOR_D2 = 0x40; // reserved on the MODEL_5170 +FDC.REG_OUTPUT.MOTOR_D3 = 0x80; // reserved on the MODEL_5170 /* * FDC Main Status Register (0x3F4, read-only) @@ -247,32 +304,42 @@ FDC.REG_DATA.CMD.MF = 0x40; // MF (Modified Frequency Modulation FDC.REG_DATA.CMD.MT = 0x80; // MT (Multi-Track; ie, data under both heads will be processed) /* - * FDC error conditions, generally assigned according to the corresponding ST0, ST1 or ST2 error bit. + * FDC status/error results, generally assigned according to the corresponding ST0, ST1, ST2 or ST3 status bit. + * + * TODO: Determine when EQUIP_CHECK is *really* set; "77 step pulses" sounds suspiciously like a typo. */ -FDC.REG_DATA.ERR = {}; -FDC.REG_DATA.ERR.NONE = 0x000000; // ST0 (IC): Normal termination of command (NT) -FDC.REG_DATA.ERR.NOT_READY = 0x000008; // ST0 (NR): When the FDD is in the not-ready state and a read or write command is issued, this flag is set; if a read or write command is issued to side 1 of a single sided drive, then this flag is set -FDC.REG_DATA.ERR.EQUIP_CHECK = 0x000010; // ST0 (EC): If a fault signal is received from the FDD, or if the track 0 signal fails to occur after 77 step pulses (recalibrate command), then this flag is set -FDC.REG_DATA.ERR.SEEK_END = 0x000020; // ST0 (SE): When the FDC completes the Seek command, this flag is set to 1 (high) -FDC.REG_DATA.ERR.INCOMPLETE = 0x000040; // ST0 (IC): Abnormal termination of command (AT); execution of command was started, but was not successfully completed -FDC.REG_DATA.ERR.RESET = 0x0000C0; // ST0 (IC): Abnormal termination because during command execution the ready signal from FOO changed state -FDC.REG_DATA.ERR.INVALID = 0x000080; // ST0 (IC): Invalid command issue (IC); command which was issued was never started -FDC.REG_DATA.ERR.ST0 = 0x0000FF; -FDC.REG_DATA.ERR.NO_ID_MARK = 0x000100; // ST1 (MA): If the FDC cannot detect the ID Address Mark, this flag is set; at the same time, the MD (Missing Address Mark in Data Field) of Status Register 2 is set -FDC.REG_DATA.ERR.NOT_WRITABLE = 0x000200; // ST1 (NW): During Execution of a Write Data, Write Deleted Data, or Format a Cylinder command, if the FDC detects a write protect signal from the FDD, then this flag is set -FDC.REG_DATA.ERR.NO_DATA = 0x000400; // ST1 (ND): FDC cannot find specified sector (or specified ID if READ_ID command) -FDC.REG_DATA.ERR.DMA_OVERRUN = 0x001000; // ST1 (OR): If the FDC is not serviced by the main systems during data transfers within a certain time interval, this flag is set -FDC.REG_DATA.ERR.CRC_ERROR = 0x002000; // ST1 (DE): When the FDC detects a CRC error in either the ID field or the data field, this flag is set -FDC.REG_DATA.ERR.END_OF_CYL = 0x008000; // ST1 (EN): When the FDC tries to access a sector beyond the final sector of a cylinder, this flag is set -FDC.REG_DATA.ERR.ST1 = 0x00FF00; -FDC.REG_DATA.ERR.NO_DATA_MARK = 0x010000; // ST2 (MD): When data is read from the medium, if the FDC cannot find a Data Address Mark or Deleted Data Address Mark, then this flag is set -FDC.REG_DATA.ERR.BAD_CYL = 0x020000; // ST2 (BC): This bit is related to the ND bit, and when the contents of C on the medium are different from that stored in the ID Register, and the content of C is FF, then this flag is set -FDC.REG_DATA.ERR.SCAN_FAILED = 0x040000; // ST2 (SN): During execution of the Scan command, if the FDC cannot find a sector on the cylinder which meets the condition, then this flag is set -FDC.REG_DATA.ERR.SCAN_EQUAL = 0x080000; // ST2 (SH): During execution of the Scan command, if the condition of "equal" is satisfied, this flag is set -FDC.REG_DATA.ERR.WRONG_CYL = 0x100000; // ST2 (WC): This bit is related to the ND bit, and when the contents of C on the medium are different from that stored in the ID Register, this flag is set -FDC.REG_DATA.ERR.DATA_FIELD = 0x200000; // ST2 (DD): If the FDC detects a CRC error in the data, then this flag is set -FDC.REG_DATA.ERR.STRL_MARK = 0x400000; // ST2 (CM): During execution of the Read Data or Scan command, if the FDC encounters a sector which contains a Deleted Data Address Mark, this flag is set -FDC.REG_DATA.ERR.ST2 = 0xFF0000; +FDC.REG_DATA.RES = {}; +FDC.REG_DATA.RES.NONE = 0x00000000; // ST0 (IC): Normal termination of command (NT) +FDC.REG_DATA.RES.NOT_READY = 0x00000008; // ST0 (NR): When the FDD is in the not-ready state and a read or write command is issued, this flag is set; if a read or write command is issued to side 1 of a single sided drive, then this flag is set +FDC.REG_DATA.RES.EQUIP_CHECK = 0x00000010; // ST0 (EC): If a fault signal is received from the FDD, or if the track 0 signal fails to occur after 77 step pulses (recalibrate command), then this flag is set +FDC.REG_DATA.RES.SEEK_END = 0x00000020; // ST0 (SE): When the FDC completes the Seek command, this flag is set to 1 (high) +FDC.REG_DATA.RES.INCOMPLETE = 0x00000040; // ST0 (IC): Abnormal termination of command (AT); execution of command was started, but was not successfully completed +FDC.REG_DATA.RES.RESET = 0x000000C0; // ST0 (IC): Abnormal termination because during command execution the ready signal from the drive changed state +FDC.REG_DATA.RES.INVALID = 0x00000080; // ST0 (IC): Invalid command issue (IC); command which was issued was never started +FDC.REG_DATA.RES.ST0 = 0x000000FF; +FDC.REG_DATA.RES.NO_ID_MARK = 0x00000100; // ST1 (MA): If the FDC cannot detect the ID Address Mark, this flag is set; at the same time, the MD (Missing Address Mark in Data Field) of Status Register 2 is set +FDC.REG_DATA.RES.NOT_WRITABLE = 0x00000200; // ST1 (NW): During Execution of a Write Data, Write Deleted Data, or Format a Cylinder command, if the FDC detects a write protect signal from the FDD, then this flag is set +FDC.REG_DATA.RES.NO_DATA = 0x00000400; // ST1 (ND): FDC cannot find specified sector (or specified ID if READ_ID command) +FDC.REG_DATA.RES.DMA_OVERRUN = 0x00001000; // ST1 (OR): If the FDC is not serviced by the main systems during data transfers within a certain time interval, this flag is set +FDC.REG_DATA.RES.CRC_ERROR = 0x00002000; // ST1 (DE): When the FDC detects a CRC error in either the ID field or the data field, this flag is set +FDC.REG_DATA.RES.END_OF_CYL = 0x00008000; // ST1 (EN): When the FDC tries to access a sector beyond the final sector of a cylinder, this flag is set +FDC.REG_DATA.RES.ST1 = 0x0000FF00; +FDC.REG_DATA.RES.NO_DATA_MARK = 0x00010000; // ST2 (MD): When data is read from the medium, if the FDC cannot find a Data Address Mark or Deleted Data Address Mark, then this flag is set +FDC.REG_DATA.RES.BAD_CYL = 0x00020000; // ST2 (BC): This bit is related to the ND bit, and when the contents of C on the medium are different from that stored in the ID Register, and the content of C is FF, then this flag is set +FDC.REG_DATA.RES.SCAN_FAILED = 0x00040000; // ST2 (SN): During execution of the Scan command, if the FDC cannot find a sector on the cylinder which meets the condition, then this flag is set +FDC.REG_DATA.RES.SCAN_EQUAL = 0x00080000; // ST2 (SH): During execution of the Scan command, if the condition of "equal" is satisfied, this flag is set +FDC.REG_DATA.RES.WRONG_CYL = 0x00100000; // ST2 (WC): This bit is related to the ND bit, and when the contents of C on the medium are different from that stored in the ID Register, this flag is set +FDC.REG_DATA.RES.DATA_FIELD = 0x00200000; // ST2 (DD): If the FDC detects a CRC error in the data, then this flag is set +FDC.REG_DATA.RES.STRL_MARK = 0x00400000; // ST2 (CM): During execution of the Read Data or Scan command, if the FDC encounters a sector which contains a Deleted Data Address Mark, this flag is set +FDC.REG_DATA.RES.ST2 = 0x00FF0000; +FDC.REG_DATA.RES.DRIVE = 0x03000000; // ST3 (Ux): Status of the "Drive Select" signals from the diskette drive +FDC.REG_DATA.RES.HEAD = 0x04000000; // ST3 (HD): Status of the "Side Select" signal from the diskette drive +FDC.REG_DATA.RES.TWOSIDE = 0x08000000; // ST3 (TS): Status of the "Two Side" signal from the diskette drive +FDC.REG_DATA.RES.TRACK0 = 0x10000000; // ST3 (T0): Status of the "Track 0" signal from the diskette drive +FDC.REG_DATA.RES.READY = 0x20000000; // ST3 (RY): Status of the "Ready" signal from the diskette drive +FDC.REG_DATA.RES.WRITEPROT = 0x40000000; // ST3 (WP): Status of the "Write Protect" signal from the diskette drive +FDC.REG_DATA.RES.FAULT = 0x80000000; // ST3 (FT): Status of the "Fault" signal from the diskette drive +FDC.REG_DATA.RES.ST3 = 0xFF000000; /* * FDC Command Sequences @@ -466,7 +533,15 @@ FDC.prototype.powerUp = function(data, fRepower) if (!this.restore(data)) return false; } if (this.chipset) { - this.nDrives = this.chipset.getSW1FloppyDrives(); + var iDrive; + this.nDrives = this.chipset.getSWFloppyDrives(); + for (iDrive = 0; iDrive < this.nDrives; iDrive++) { + var drive = this.aDrives[iDrive]; + drive.bType = this.chipset.getSWFloppyDriveType(iDrive); + if (drive.bType == ChipSet.FDRIVE.DSHC) { + drive.nCylinders = 80; + } + } /* * Now that we finally have the SW1 settings, we can populate the HTML control * to match the actual (well, um, specified) number of floppy drives in the system. @@ -477,7 +552,7 @@ FDC.prototype.powerUp = function(data, fRepower) controlDrives.removeChild(controlDrives.firstChild); } controlDrives.innerHTML = ""; - for (var iDrive = 0; iDrive < this.nDrives; iDrive++) { + for (iDrive = 0; iDrive < this.nDrives; iDrive++) { var controlOption = window.document.createElement("option"); controlOption['value'] = iDrive; /* @@ -507,7 +582,7 @@ FDC.prototype.powerUp = function(data, fRepower) */ FDC.prototype.powerDown = function(fSave) { - return fSave && this.save ? this.save() : true; + return fSave && this.save? this.save() : true; }; /** @@ -577,25 +652,25 @@ FDC.prototype.initController = function(data) * Selected drive (from reOutput), which can only be selected if its motor is on (see regOutput). */ this.iDrive = data[i++]; - /* - * FDC commands select a unit, which I assume should always match the selected drive, but since they're - * independent, we'll use independent variables. - */ - this.iUnit = data[i++]; + i++; // unused slot (if reused, bias by +4, since it was formerly a unit #) + /* * Defaults to FDC.REG_STATUS.RQM set (ready for command) and FDC.REG_STATUS.READ_DATA clear (data direction * is from processor to the FDC Data Register). */ this.regStatus = data[i++]; + /* * There can be up to 9 command bytes, and 7 result bytes, so 9 data registers are sufficient for communicating * in both directions (hence, the new Array(9) default above). */ this.regDataArray = data[i++]; + /* * Determines the next data byte to be received. */ this.regDataIndex = data[i++]; + /* * Determines the next data byte to be sent (internally, we use regDataIndex to read data bytes, up to this total). */ @@ -615,6 +690,7 @@ FDC.prototype.initController = function(data) * the SW1 switch settings. */ if (this.aDrives === undefined) { + this.nDrives = 0; // this will be set later to the number of ACTUAL drives this.aDrives = new Array(4); } for (var iDrive = 0; iDrive < this.aDrives.length; iDrive++) { @@ -653,7 +729,7 @@ FDC.prototype.saveController = function() var i = 0; var data = []; data[i++] = this.iDrive; - data[i++] = this.iUnit; + data[i++] = 0; data[i++] = this.regStatus; data[i++] = this.regDataArray; data[i++] = this.regDataIndex; @@ -668,7 +744,7 @@ FDC.prototype.saveController = function() /** * initDrive(drive, iDrive, data) - * + * * @this {FDC} * @param {Object} drive * @param {number} iDrive @@ -684,23 +760,32 @@ FDC.prototype.initDrive = function(drive, iDrive, data) if (data === undefined) { /* - * We set a default of two heads (MODEL_5150 PCs originally shipped with single-sided drives only, + * We set a default of two heads (MODEL_5150 PCs originally shipped with single-sided drives, * but the ROM BIOS appears to have always supported both drive types). */ - data = [FDC.REG_DATA.ERR.RESET, true, 0, 2, 0]; + data = [FDC.REG_DATA.RES.RESET, true, 0, 2, 0]; } if (typeof data[1] == "boolean") { - data[1] = [FDC.DEFAULT_DRIVE_NAME, 40, data[3], 9, 512, data[1]]; + /* + * Note that when no data is provided (eg, when the controller is being reinitialized), we now take + * care to use drive.nCylinders as the default, falling back to a 40-track maximum ONLY when the drive + * hasn't been initialized. This preserves whatever maximum the powerUp() function may have obtained + * from the ChipSet component. + * + * TODO: We may need to make a similar accommodation for drive.nHeads and drive.nSectors down the road; + * they currently default to a maximum of 2 heads (see above) and 9 sectors/track (see below). + */ + data[1] = [FDC.DEFAULT_DRIVE_NAME, drive.nCylinders || 40, data[3], 9, 512, data[1]]; } /* - * errorCode used to be an FDC global, but in order to insulate FDC state from the operation of various functions that operate on drive - * objects (eg, readByte and writeByte), I've made it a per-drive variable. This choice, similar to my choice for handling PCN, is - * probably contrary to how the actual hardware works, but I prefer this approach, as long as it doesn't expose any incompatibilities that - * any software actually cares about. + * resCode used to be an FDC global, but in order to insulate FDC state from the operation of various functions + * that operate on drive objects (eg, readByte and writeByte), I've made it a per-drive variable. This choice, + * similar to my choice for handling PCN, may be contrary to how the actual hardware works, but I prefer this + * approach, as long as it doesn't expose any incompatibilities that any software actually cares about. */ - drive.errorCode = data[i++]; + drive.resCode = data[i++]; /* * Some additional drive properties/defaults that are largely for the Disk component's benefit. @@ -720,12 +805,36 @@ FDC.prototype.initDrive = function(drive, iDrive, data) * awaiting their first FDC command. We do this because the initial INT_STATUS command returns a PCN, which will also * be undefined unless we have at least zeroed both the current drive and the "present" cylinder on that drive. * - * Alternatively, I could make PCN a global FDC variable. That's probably closer to how the actual hardware operates, - * but I'm eschewing global FDC variables so that the FDC component can be a good client to both the CPU and other components. + * Alternatively, I could make PCN a global FDC variable. That may be closer to how the actual hardware operates, + * but I'm using per-drive variables so that the FDC component can be a good client to both the CPU and other components. + * + * COMPATIBILITY ALERT: The MODEL_5170 BIOS ("DSKETTE_SETUP") attempts to discern the drive type (double-density vs. + * high-capacity) by "slapping" the heads around. Literally (it uses a constant named "TRK_SLAP" equal to 48). + * After seeking to "TRK_SLAP", the BIOS performs a series of seeks, looking for the precise point where the heads + * return to track 0. + * + * Here's how it works: the BIOS seeks to track 48 (which is fine on an 80-track 1.2Mb high-capacity drive, but 9 tracks + * too far on a 40-track 360Kb double-density drive), then seeks to track 10, and then seeks in single-track increments + * up to 10 more times until the DRIVE_STATUS command returns ST3 with the TRACK0 bit set. + * + * This implies that SEEK isn't really seeking to a specified cylinder, but rather it is calculating a delta from + * the previous cylinder to the specified cylinder, and stepping over that number of tracks. Which means that SEEK + * is updating a "logical" cylinder number, not the "physical" (actual) cylinder number. Presumably a RECALIBRATE + * command will bring the logical and physical values into sync, but once an out-of-bounds cylinder is requested, they + * will be out of sync. + * + * To simulate this, bCylinder is now treated as the "physical" cylinder (since that's how it's ALWAYS been used here), + * and bCylinderSeek will now track (pun intended) the "logical" cylinder that's programmed via SEEK commands. */ + drive.bType = ChipSet.FDRIVE.DSDD; // default; updated later once we have the actual ChipSet object drive.bHead = data[i++]; - i++; // skip the data[] slot where we used to store drive.nHeads (no longer used) + drive.bCylinderSeek = data[i++]; // the data[] slot where we used to store drive.nHeads (or -1) drive.bCylinder = data[i++]; + if (drive.bCylinderSeek >= 100) { // verify that the saved bCylinderSeek is valid, otherwise sync it with bCylinder + drive.bCylinderSeek -= 100; + } else { + drive.bCylinderSeek -= drive.bCylinder; + } drive.bSector = data[i++]; drive.bSectorEnd = data[i++]; // aka EOT drive.nBytes = data[i++]; @@ -735,7 +844,7 @@ FDC.prototype.initDrive = function(drive, iDrive, data) * * NOTE: I now avoid reinitializing drive.disk in order to retain any previously mounted diskette across resets. * - * drive.disk = null; // when a "disk" is "inserted" into the "drive", this variable contains a Disk object + * drive.disk = null; // when a "disk" is "inserted" into the "drive", this is a Disk object */ /* @@ -813,10 +922,14 @@ FDC.prototype.saveDrive = function(drive) { var i = 0; var data = []; - data[i++] = drive.errorCode; + data[i++] = drive.resCode; data[i++] = [drive.name, drive.nCylinders, drive.nHeads, drive.nSectors, drive.cbSector, drive.fRemovable]; data[i++] = drive.bHead; - data[i++] = -1; // where we used to store drive.nHeads (no longer used) + /* + * We used to store drive.nHeads in the next slot, but now we store bCylinderSeek, + * and we bias it by +100 so that initDrive() can distinguish it from older values. + */ + data[i++] = drive.bCylinderSeek + 100; data[i++] = drive.bCylinder; data[i++] = drive.bSector; data[i++] = drive.bSectorEnd; @@ -922,7 +1035,7 @@ FDC.prototype.seekDrive = function(drive, iSector, nSectors) * do anything with bSectorEnd at this point. Perhaps someday, when we faithfully honor/restrict requests * to a single track (or a single cylinder, in the case of multi-track requests). */ - drive.errorCode = FDC.REG_DATA.ERR.NONE; + drive.resCode = FDC.REG_DATA.RES.NONE; /* * At this point, we've finished simulating what an FDC.REG_DATA.CMD.READ_DATA command would have performed, * up through doRead(). Now it's the caller responsibility to call readByte(), just like the DMA Controller would. @@ -1228,17 +1341,41 @@ FDC.prototype.outFDCOutput = function(port, bOut, addrFrom) this.messagePort(port, bOut, addrFrom, "OUTPUT"); if (!(bOut & FDC.REG_OUTPUT.ENABLE)) { this.initController(); - } else if (!(this.regOutput & FDC.REG_OUTPUT.ENABLE)) { /* - * When FDC.REG_OUTPUT.ENABLE transitions from 0 to 1, generate an interrupt + * initController() resets, among other things, the selected drive (this.iDrive), so if we were + * still updating this.iDrive below based on the "drive select" bits in regOutput, we would want + * to make sure those bits now match what initController() set. But since we no longer do that + * (see below), this is no longer needed either. + */ + // bOut = (bOut & ~FDC.REG_OUTPUT.DS) | this.iDrive; + } + else if (!(this.regOutput & FDC.REG_OUTPUT.ENABLE)) { + /* + * When FDC.REG_OUTPUT.ENABLE transitions from 0 to 1, generate an interrupt. */ if (this.regOutput & FDC.REG_OUTPUT.INT_ENABLE) { if (this.chipset) this.chipset.setIRR(ChipSet.IRQ.FDC); } } - var iDrive = bOut & FDC.REG_OUTPUT.SELECT; - if (bOut & (FDC.REG_OUTPUT.MOTOR_A << iDrive)) - this.iDrive = iDrive; + /* + * This no longer updates the internally selected drive (this.iDrive) based on regOutput, because (a) there seems + * to be no point, as all drive-related commands include their own "drive select" bits, and (b) it breaks the + * MODEL_5170 boot code. Here's why: + * + * Unlike previous models, the MODEL_5170 BIOS probes all installed diskette drives to determine drive type; + * ie, DSDD (40-track) or DSHC (80-track). So if there are two drives, the last selected drive will be drive 1. + * Immediately before booting, the BIOS issues an INT 0x3/AH=0 reset, which writes regOutput two times: first + * with FDC.REG_OUTPUT.ENABLE clear, and then with it set. However, both times, it ALSO loads the last selected + * drive # into regOutput's "drive select" bits. + * + * If we switched our selected drive to match regOutput, then the ST0 value we returned on an INT_STATUS command + * following the regOutput reset operation would indicate drive 1 instead of drive 0. But the BIOS requires + * the ST0 result from the INT_STATUS command ALWAYS be 0xC0, not 0xC1, so the controller must not be propagating + * regOutput's "drive select" bits in the way I originally assumed. + */ + // var iDrive = bOut & FDC.REG_OUTPUT.DS; + // if (bOut & (FDC.REG_OUTPUT.MOTOR_D0 << iDrive)) this.iDrive = iDrive; + this.regOutput = bOut; }; @@ -1404,7 +1541,7 @@ FDC.prototype.intBIOSDisketteReturn = function(nCycles, nLevel) { if (DEBUGGER) { nCycles = this.cpu.getCycles() - nCycles; - this.messageDebugger("FDC.intBIOSReturn(" + nLevel + "): C=" + (this.cpu.getCF() ? 1 : 0) + " (cycles=" + nCycles + ")"); + this.messageDebugger("FDC.intBIOSReturn(" + nLevel + "): C=" + (this.cpu.getCF()? 1 : 0) + " (cycles=" + nCycles + ")"); // if (DEBUG && nCycles > 10000) this.cpu.haltCPU(); } }; @@ -1419,7 +1556,7 @@ FDC.prototype.doCmd = function() var fIRQ = false; this.regDataIndex = 0; var bCmd = this.popCmd(); - var iUnitSelect, drive, bHeadSelect, bHead, n; + var drive, bDrive, bHeadSelect, bHead, bCylinder, n; /* * NOTE: We currently ignore the FDC.REG_DATA.CMD.SK, FDC.REG_DATA.CMD.MF and FDC.REG_DATA.CMD.MT bits of every command. @@ -1428,109 +1565,129 @@ FDC.prototype.doCmd = function() * data without any formatting data. * * Similarly, we ignore parameters like SRT, HUT, HLT and the like, since our "motors" don't require physical delays; - * however, if timing issues become compatibility issues, we might have to start honoring those delays. In any case, - * the maximum speed of the simulation will still be limited by various spin-loops in the ROM BIOS that wait prescribed - * times, so even with infinitely fast hardware, the simulation will never run as fast as it theoretically could, - * unless we opt to identify those spin-loops and either patch them or skip over them. + * however, if timing issues become compatibility issues, we'll have to revisit those delays. In any case, the maximum + * speed of the simulation will still be limited by various spin-loops in the ROM BIOS that wait prescribed times, so even + * with infinitely fast hardware, the simulation will never run as fast as it theoretically could, unless we opt to identify + * those spin-loops and either patch them or skip over them. */ var bCmdMasked = bCmd & FDC.REG_DATA.CMD.MASK; + switch (bCmdMasked) { - case FDC.REG_DATA.CMD.SPECIFY: // 0x03 - this.popSRT(); // SRT and HUT (encodings?) - this.popHLT(); // HLT and ND (encodings?) - this.beginResult(); // no results are provided by this command, and fIRQ should remain false - break; - case FDC.REG_DATA.CMD.DRIVE_STATUS: // 0x04 - iUnitSelect = this.popCmd("US"); - bHeadSelect = (iUnitSelect >> 2) & 0x1; - this.iUnit = (iUnitSelect &= 0x3); - drive = this.aDrives[iUnitSelect]; - this.beginResult(); - this.pushST3(drive); - break; - case FDC.REG_DATA.CMD.WRITE_DATA: // 0x05 - case FDC.REG_DATA.CMD.READ_DATA: // 0x06 - iUnitSelect = this.popCmd("US"); - bHeadSelect = (iUnitSelect >> 2) & 0x1; - iUnitSelect &= 0x3; - this.iUnit = iUnitSelect; - drive = this.aDrives[iUnitSelect]; - drive.bHead = bHeadSelect; - drive.bCylinder = this.popCmd("C"); // C - bHead = this.popCmd("H"); // H - Component.assert(bHead == bHeadSelect); - drive.bSector = this.popCmd("R"); // R - n = this.popCmd("N"); // N - drive.nBytes = 128 << n; // 0 => 128, 1 => 256, 2 => 512, 3 => 1024 - drive.bSectorEnd = this.popCmd("EOT"); // EOT (final sector number on a cylinder) - this.popCmd("GPL"); // GPL (spacing between sectors, excluding VCO Sync Field; 3) - this.popCmd("DTL"); // DTL (when N is 0, DTL stands for the data length to read out or write into the sector) - if (bCmdMasked == FDC.REG_DATA.CMD.READ_DATA) - this.doRead(drive); - else - this.doWrite(drive); - this.beginResult(); - this.pushST0(drive.errorCode); - this.pushST1(drive.errorCode); - this.pushST2(drive.errorCode); - this.pushResult(drive.bCylinder, "C"); - this.pushResult(drive.bHead, "H"); - this.pushResult(drive.bSector, "R"); - this.pushResult(n, "N"); - fIRQ = true; - break; - case FDC.REG_DATA.CMD.RECALIBRATE: // 0x07 - this.iUnit = iUnitSelect = this.popCmd("US") & 0x3; - drive = this.aDrives[iUnitSelect]; - drive.bCylinder = 0; - drive.errorCode = FDC.REG_DATA.ERR.SEEK_END; - this.beginResult(); // no results are provided; this command is typically followed by FDC.REG_DATA.CMD.INT_STATUS - fIRQ = true; - break; - case FDC.REG_DATA.CMD.INT_STATUS: // 0x08 - this.iUnit = this.iDrive; - drive = this.aDrives[this.iUnit]; - this.beginResult(); - this.pushST0(drive.errorCode); - this.pushResult(drive.bCylinder, "PCN");// no interrupt is generated by this command, so fIRQ should remain false - break; - case FDC.REG_DATA.CMD.FORMAT_TRACK: // 0x0D - iUnitSelect = this.popCmd("US"); - bHeadSelect = (iUnitSelect >> 2) & 0x1; - iUnitSelect &= 0x3; - this.iUnit = iUnitSelect; - drive = this.aDrives[iUnitSelect]; - drive.bHead = bHeadSelect; - n = this.popCmd("N"); // N - drive.nBytes = 128 << n; // 0 => 128, 1 => 256, 2 => 512, 3 => 1024 (bytes/sector) - drive.bSectorEnd = this.popCmd("SC"); // SC (sectors/track) - this.popCmd("GPL"); // GPL (spacing between sectors, excluding VCO Sync Field; 3) - drive.bFiller = this.popCmd("D"); // D (filler byte) - this.doFormat(drive); - this.beginResult(); - this.pushST0(drive.errorCode); - this.pushST1(drive.errorCode); - this.pushST2(drive.errorCode); - this.pushResult(drive.bCylinder, "C"); - this.pushResult(drive.bHead, "H"); - this.pushResult(drive.bSector, "R"); - this.pushResult(n, "N"); - fIRQ = true; - break; - case FDC.REG_DATA.CMD.SEEK: // 0x0F - iUnitSelect = this.popCmd("US"); - bHeadSelect = (iUnitSelect >> 2) & 0x1; - this.iUnit = (iUnitSelect &= 0x3); - drive = this.aDrives[iUnitSelect]; - drive.bHead = bHeadSelect; - drive.bCylinder = this.popCmd("NCN"); - drive.errorCode = FDC.REG_DATA.ERR.SEEK_END; - this.beginResult(); // like FDC.REG_DATA.CMD.RECALIBRATE, no results are provided - fIRQ = true; - break; - default: - if (DEBUG) this.messageDebugger("FDC operation unsupported (command=0x: " + str.toHexByte(bCmd) + ")"); - break; + case FDC.REG_DATA.CMD.SPECIFY: // 0x03 + this.popSRT(); // SRT and HUT (encodings?) + this.popHLT(); // HLT and ND (encodings?) + this.beginResult(); // no results are provided by this command, and fIRQ should remain false + break; + case FDC.REG_DATA.CMD.DRIVE_STATUS: // 0x04 (SENSE DRIVE STATUS) + bDrive = this.popCmd("DS"); + bHeadSelect = (bDrive >> 2) & 0x1; + this.iDrive = (bDrive & 0x3); + drive = this.aDrives[this.iDrive]; + this.beginResult(); + this.pushST3(drive); + break; + case FDC.REG_DATA.CMD.WRITE_DATA: // 0x05 + case FDC.REG_DATA.CMD.READ_DATA: // 0x06 + bDrive = this.popCmd("DS"); + bHeadSelect = (bDrive >> 2) & 0x1; + this.iDrive = (bDrive & 0x3); + drive = this.aDrives[this.iDrive]; + drive.bHead = bHeadSelect; + drive.bCylinder = this.popCmd("C"); // C + bHead = this.popCmd("H"); // H + Component.assert(bHead == bHeadSelect); + drive.bSector = this.popCmd("R"); // R + n = this.popCmd("N"); // N + drive.nBytes = 128 << n; // 0 => 128, 1 => 256, 2 => 512, 3 => 1024 + drive.bSectorEnd = this.popCmd("EOT"); // EOT (final sector number on a cylinder) + this.popCmd("GPL"); // GPL (spacing between sectors, excluding VCO Sync Field; 3) + this.popCmd("DTL"); // DTL (when N is 0, DTL stands for the data length to read out or write into the sector) + if (bCmdMasked == FDC.REG_DATA.CMD.READ_DATA) + this.doRead(drive); + else + this.doWrite(drive); + this.beginResult(); + this.pushST0(drive); + this.pushST1(drive); + this.pushST2(drive); + this.pushResult(drive.bCylinder, "C"); + this.pushResult(drive.bHead, "H"); + this.pushResult(drive.bSector, "R"); + this.pushResult(n, "N"); + fIRQ = true; + break; + case FDC.REG_DATA.CMD.RECALIBRATE: // 0x07 + bDrive = this.popCmd("DS"); + this.iDrive = (bDrive & 0x3); + drive = this.aDrives[this.iDrive]; + drive.bCylinder = drive.bCylinderSeek = 0; + drive.resCode = FDC.REG_DATA.RES.SEEK_END | FDC.REG_DATA.RES.TRACK0; + this.beginResult(); // no results are provided; this command is typically followed by FDC.REG_DATA.CMD.INT_STATUS + fIRQ = true; + break; + case FDC.REG_DATA.CMD.INT_STATUS: // 0x08 (SENSE INTERRUPT STATUS) + drive = this.aDrives[this.iDrive]; + this.beginResult(); + this.pushST0(drive); + this.pushResult(drive.bCylinder, "PCN");// no interrupt is generated by this command, so fIRQ should remain false + break; + case FDC.REG_DATA.CMD.FORMAT_TRACK: // 0x0D + bDrive = this.popCmd("DS"); + bHeadSelect = (bDrive >> 2) & 0x1; + this.iDrive = (bDrive & 0x3); + drive = this.aDrives[this.iDrive]; + drive.bHead = bHeadSelect; + n = this.popCmd("N"); // N + drive.nBytes = 128 << n; // 0 => 128, 1 => 256, 2 => 512, 3 => 1024 (bytes/sector) + drive.bSectorEnd = this.popCmd("SC"); // SC (sectors/track) + this.popCmd("GPL"); // GPL (spacing between sectors, excluding VCO Sync Field; 3) + drive.bFiller = this.popCmd("D"); // D (filler byte) + this.doFormat(drive); + this.beginResult(); + this.pushST0(drive); + this.pushST1(drive); + this.pushST2(drive); + this.pushResult(drive.bCylinder, "C"); + this.pushResult(drive.bHead, "H"); + this.pushResult(drive.bSector, "R"); + this.pushResult(n, "N"); + fIRQ = true; + break; + case FDC.REG_DATA.CMD.SEEK: // 0x0F + bDrive = this.popCmd("DS"); + bHeadSelect = (bDrive >> 2) & 0x1; + this.iDrive = (bDrive & 0x3); + drive = this.aDrives[this.iDrive]; + drive.bHead = bHeadSelect; + /* + * As discussed in initDrive(), we can no longer simply set bCylinder to the specified NCN; + * instead, we must calculate the delta between bCylinderSeek and the NCN, and adjust bCylinder + * by that amount. Then we simply move the NCN into bCylinderSeek without any range checking. + * + * Since bCylinder is now expressly defined as the "physical" cylinder number, it must never be + * allowed to exceed the physical boundaries of the drive (ie, never lower than 0, and never greater + * than or equal to nCylinders). + */ + bCylinder = this.popCmd("NCN"); + drive.bCylinder += bCylinder - drive.bCylinderSeek; + if (drive.bCylinder < 0) drive.bCylinder = 0; + if (drive.bCylinder >= drive.nCylinders) drive.bCylinder = drive.nCylinders - 1; + drive.bCylinderSeek = bCylinder; + drive.resCode = FDC.REG_DATA.RES.SEEK_END; + /* + * TODO: To properly support ALL the ST3 result bits (not just TRACK0), we need a resCode + * update() function that all FDC commands can use. This code is merely sufficient to get us + * through the "DSKETTE_SETUP" gauntlet in the MODEL_5170 BIOS. + */ + if (drive.bCylinder == 0) { + drive.resCode |= FDC.REG_DATA.RES.TRACK0; + } + this.beginResult(); // like FDC.REG_DATA.CMD.RECALIBRATE, no results are provided + fIRQ = true; + break; + default: + if (DEBUG) this.messageDebugger("FDC operation unsupported (command=0x: " + str.toHexByte(bCmd) + ")"); + break; } if (this.regDataTotal > 0) this.regStatus |= (FDC.REG_STATUS.READ_DATA | FDC.REG_STATUS.BUSY); @@ -1541,10 +1698,10 @@ FDC.prototype.doCmd = function() * result has been read, the interrupt is cleared (see inFDCData). * * TODO: Technically, interrupt request status should be cleared by the FDC.REG_DATA.CMD.INT_STATUS command; in fact, - * if that command is issued and no interrupt was pending, then FDC.REG_DATA.ERR.INVALID should be returned (via ST0). + * if that command is issued and no interrupt was pending, then FDC.REG_DATA.RES.INVALID should be returned (via ST0). */ if (this.regOutput & FDC.REG_OUTPUT.INT_ENABLE) { - if (drive && !(drive.errorCode & FDC.REG_DATA.ERR.NOT_READY) && fIRQ) { + if (drive && !(drive.resCode & FDC.REG_DATA.RES.NOT_READY) && fIRQ) { if (this.chipset) this.chipset.setIRR(ChipSet.IRQ.FDC); } } @@ -1561,10 +1718,10 @@ FDC.prototype.popCmd = function(name) { Component.assert((!this.regDataIndex || name !== undefined) && this.regDataIndex < this.regDataTotal); var bCmd = this.regDataArray[this.regDataIndex]; - if (DEBUG && DEBUGGER && this.dbg && this.dbg.messageEnabled((this.regDataIndex > 0 ? this.dbg.MESSAGE_PORT : 0) | this.dbg.MESSAGE_FDC)) { + if (DEBUG && DEBUGGER && this.dbg && this.dbg.messageEnabled((this.regDataIndex > 0? this.dbg.MESSAGE_PORT : 0) | this.dbg.MESSAGE_FDC)) { var bCmdMasked = bCmd & FDC.REG_DATA.CMD.MASK; if (!name && !this.regDataIndex && FDC.aCmdSeqs[bCmdMasked]) name = FDC.aCmdSeqs[bCmdMasked].name; - this.dbg.message("FDC.CMD[" + (name !== undefined ? name : this.regDataIndex) + "]: 0x" + str.toHexByte(bCmd)); + this.dbg.message("FDC.CMD[" + (name || this.regDataIndex) + "]: 0x" + str.toHexByte(bCmd)); } this.regDataIndex++; return bCmd; @@ -1615,41 +1772,41 @@ FDC.prototype.beginResult = function() */ FDC.prototype.pushResult = function(bResult, name) { - if (DEBUG && DEBUGGER && this.dbg && this.dbg.messageEnabled(this.dbg.MESSAGE_PORT | this.dbg.MESSAGE_FDC)) this.dbg.message("FDC.RES[" + (name !== undefined ? name : this.regDataTotal) + "]: 0x" + str.toHexByte(bResult)); + if (DEBUG && DEBUGGER && this.dbg && this.dbg.messageEnabled(this.dbg.MESSAGE_PORT | this.dbg.MESSAGE_FDC)) this.dbg.message("FDC.RES[" + (name || this.regDataTotal) + "]: 0x" + str.toHexByte(bResult)); this.regDataArray[this.regDataTotal++] = bResult; }; /** - * pushST0(errorCode) + * pushST0(drive) * * @this {FDC} - * @param {number} errorCode + * @param {Object} drive */ -FDC.prototype.pushST0 = function(errorCode) +FDC.prototype.pushST0 = function(drive) { - this.pushResult(this.iUnit | this.aDrives[this.iUnit].bHead | (errorCode & FDC.REG_DATA.ERR.ST0), "ST0"); + this.pushResult(drive.iDrive | drive.bHead | (drive.resCode & FDC.REG_DATA.RES.ST0), "ST0"); }; /** - * pushST1(errorCode) + * pushST1(drive) * * @this {FDC} - * @param {number} errorCode + * @param {Object} drive */ -FDC.prototype.pushST1 = function(errorCode) +FDC.prototype.pushST1 = function(drive) { - this.pushResult((errorCode & FDC.REG_DATA.ERR.ST1) >> 8, "ST1"); + this.pushResult((drive.resCode & FDC.REG_DATA.RES.ST1) >>> 8, "ST1"); }; /** - * pushST2(errorCode) + * pushST2(drive) * * @this {FDC} - * @param {number} errorCode + * @param {Object} drive */ -FDC.prototype.pushST2 = function(errorCode) +FDC.prototype.pushST2 = function(drive) { - this.pushResult((errorCode & FDC.REG_DATA.ERR.ST2) >> 16, "ST2"); + this.pushResult((drive.resCode & FDC.REG_DATA.RES.ST2) >>> 16, "ST2"); }; /** @@ -1660,10 +1817,7 @@ FDC.prototype.pushST2 = function(errorCode) */ FDC.prototype.pushST3 = function(drive) { - // - // WARNING: Unimplemented - // - this.pushResult(0x00, "ST3"); + this.pushResult((drive.resCode & FDC.REG_DATA.RES.ST3) >>> 24, "ST3"); }; /** @@ -1737,13 +1891,13 @@ FDC.prototype.doRead = function(drive) * With only NOT_READY and INCOMPLETE set, an empty drive causes DOS to report "General Failure"; * with the addition of NO_DATA, DOS reports "Sector not found". */ - drive.errorCode = FDC.REG_DATA.ERR.NOT_READY | FDC.REG_DATA.ERR.INCOMPLETE; + drive.resCode = FDC.REG_DATA.RES.NOT_READY | FDC.REG_DATA.RES.INCOMPLETE; if (DEBUG) this.messageDebugger("FDC.doRead(" + drive.bCylinder + ":" + drive.bHead + ":" + drive.bSector + ":" + drive.nBytes + ")"); if (drive.disk) { drive.sector = null; - drive.errorCode = FDC.REG_DATA.ERR.NONE; + drive.resCode = FDC.REG_DATA.RES.NONE; if (this.chipset) { this.chipset.connectDMA(ChipSet.DMA_FDC, this, 'dmaRead', drive); this.chipset.requestDMA(ChipSet.DMA_FDC); @@ -1759,17 +1913,17 @@ FDC.prototype.doRead = function(drive) */ FDC.prototype.doWrite = function(drive) { - drive.errorCode = FDC.REG_DATA.ERR.NOT_READY | FDC.REG_DATA.ERR.INCOMPLETE; + drive.resCode = FDC.REG_DATA.RES.NOT_READY | FDC.REG_DATA.RES.INCOMPLETE; if (DEBUG) this.messageDebugger("FDC.doWrite(" + drive.bCylinder + ":" + drive.bHead + ":" + drive.bSector + ":" + drive.nBytes + ")"); if (drive.disk) { if (drive.disk.fWriteProtected) { - drive.errorCode = FDC.REG_DATA.ERR.NOT_WRITABLE | FDC.REG_DATA.ERR.INCOMPLETE; + drive.resCode = FDC.REG_DATA.RES.NOT_WRITABLE | FDC.REG_DATA.RES.INCOMPLETE; return; } drive.sector = null; - drive.errorCode = FDC.REG_DATA.ERR.NONE; + drive.resCode = FDC.REG_DATA.RES.NONE; if (this.chipset) { this.chipset.connectDMA(ChipSet.DMA_FDC, this, 'dmaWrite', drive); this.chipset.requestDMA(ChipSet.DMA_FDC); @@ -1794,13 +1948,13 @@ FDC.prototype.doWrite = function(drive) */ FDC.prototype.doFormat = function(drive) { - drive.errorCode = FDC.REG_DATA.ERR.NOT_READY | FDC.REG_DATA.ERR.INCOMPLETE; + drive.resCode = FDC.REG_DATA.RES.NOT_READY | FDC.REG_DATA.RES.INCOMPLETE; //if (DEBUG) this.messageDebugger("doFormat()"); if (drive.disk) { drive.sector = null; - drive.errorCode = FDC.REG_DATA.ERR.NONE; + drive.resCode = FDC.REG_DATA.RES.NONE; if (this.chipset) { drive.cbFormat = 0; drive.abFormat = new Array(4); @@ -1840,7 +1994,7 @@ FDC.prototype.doFormat = function(drive) FDC.prototype.readByte = function(drive, done) { var b = -1; - if (!drive.errorCode && drive.disk) { + if (!drive.resCode && drive.disk) { do { if (drive.sector) { if ((b = drive.disk.read(drive.sector, drive.ibSector++)) >= 0) @@ -1851,7 +2005,7 @@ FDC.prototype.readByte = function(drive, done) */ drive.sector = drive.disk.seek(drive.bCylinder, drive.bHead, drive.bSector); if (!drive.sector) { - drive.errorCode = FDC.REG_DATA.ERR.NO_DATA | FDC.REG_DATA.ERR.INCOMPLETE; + drive.resCode = FDC.REG_DATA.RES.NO_DATA | FDC.REG_DATA.RES.INCOMPLETE; break; } drive.ibSector = 0; @@ -1888,7 +2042,7 @@ FDC.prototype.readByte = function(drive, done) */ FDC.prototype.writeByte = function(drive, b) { - if (drive.errorCode || !drive.disk) return -1; + if (drive.resCode || !drive.disk) return -1; do { if (drive.sector) { if (drive.disk.write(drive.sector, drive.ibSector++, b)) @@ -1900,9 +2054,9 @@ FDC.prototype.writeByte = function(drive, b) drive.sector = drive.disk.seek(drive.bCylinder, drive.bHead, drive.bSector); if (!drive.sector) { /* - * TODO: Determine whether this should be FDC.REG_DATA.ERR.CRC_ERROR or FDC.REG_DATA.ERR.DATA_FIELD + * TODO: Determine whether this should be FDC.REG_DATA.RES.CRC_ERROR or FDC.REG_DATA.RES.DATA_FIELD */ - drive.errorCode = FDC.REG_DATA.ERR.CRC_ERROR | FDC.REG_DATA.ERR.INCOMPLETE; + drive.resCode = FDC.REG_DATA.RES.CRC_ERROR | FDC.REG_DATA.RES.INCOMPLETE; b = -1; break; } @@ -1922,7 +2076,7 @@ FDC.prototype.writeByte = function(drive, b) */ FDC.prototype.writeFormat = function(drive, b) { - if (drive.errorCode) return -1; + if (drive.resCode) return -1; drive.abFormat[drive.cbFormat++] = b; if (drive.cbFormat == drive.abFormat.length) { drive.bCylinder = drive.abFormat[0]; // C diff --git a/my_modules/pcjs-client/lib/hdc.js b/my_modules/pcjs-client/lib/hdc.js index e1fc53972..eb45e1bf4 100644 --- a/my_modules/pcjs-client/lib/hdc.js +++ b/my_modules/pcjs-client/lib/hdc.js @@ -1228,49 +1228,51 @@ HDC.prototype.doCmd = function() { * processed in the first group, and all the rest should be processed in the second group. */ switch (bCmd) { - case HDC.REG_DATA.CMD.REQUEST_SENSE: // 0x03 - this.beginResult(drive? drive.errorCode : HDC.REG_DATA.ERR.NOT_READY); - this.pushResult(b1); - this.pushResult(b2); - this.pushResult(b3); - /* - * Although not terribly clear from IBM's "Fixed Disk Adapter" documentation, - * a data "status byte" also follows the 4 "sense bytes". Interestingly, The HDC BIOS - * checks that data status byte for REG_DATA.STATUS_ERROR, but I have to wonder if it - * would have ever been set for this command.... - * - * The whole point of the HDC.REG_DATA.CMD.REQUEST_SENSE command is to obtain details about a - * previous error, so if HDC.REG_DATA.CMD.REQUEST_SENSE itself reports an error, what would that mean? - */ - this.pushResult(HDC.REG_DATA.STATUS_OK | bDrive); - bCmd = -1; // mark the command as complete - break; - case HDC.REG_DATA.CMD.INIT_DRIVE: // 0x0C - /* - * Pop off all the extra "Initialize Drive Characteristics" bytes and store them, - * for the benefit of other functions, like verifyDrive(). - */ - var i = 0; - while ((bParm = this.popCmd()) >= 0) { - if (drive && i < drive.abDriveParms.length) { - drive.abDriveParms[i++] = bParm; - } + case HDC.REG_DATA.CMD.REQUEST_SENSE: // 0x03 + this.beginResult(drive? drive.errorCode : HDC.REG_DATA.ERR.NOT_READY); + this.pushResult(b1); + this.pushResult(b2); + this.pushResult(b3); + /* + * Although not terribly clear from IBM's "Fixed Disk Adapter" documentation, + * a data "status byte" also follows the 4 "sense bytes". Interestingly, The HDC BIOS + * checks that data status byte for REG_DATA.STATUS_ERROR, but I have to wonder if it + * would have ever been set for this command.... + * + * The whole point of the HDC.REG_DATA.CMD.REQUEST_SENSE command is to obtain details about a + * previous error, so if HDC.REG_DATA.CMD.REQUEST_SENSE itself reports an error, what would that mean? + */ + this.pushResult(HDC.REG_DATA.STATUS_OK | bDrive); + bCmd = -1; // mark the command as complete + break; + case HDC.REG_DATA.CMD.INIT_DRIVE: // 0x0C + /* + * Pop off all the extra "Initialize Drive Characteristics" bytes and store them, + * for the benefit of other functions, like verifyDrive(). + */ + var i = 0; + while ((bParm = this.popCmd()) >= 0) { + if (drive && i < drive.abDriveParms.length) { + drive.abDriveParms[i++] = bParm; } - if (drive) this.verifyDrive(drive); - bDataStatus = HDC.REG_DATA.STATUS_OK; - if (!drive && this.iDriveAllowFail == iDrive) { - this.iDriveAllowFail = -1; - if (DEBUG) this.messageDebugger("HDC.doCmd(): fake failure triggered"); - bDataStatus = HDC.REG_DATA.STATUS_ERROR; - } - this.beginResult(bDataStatus | bDrive); - bCmd = -1; // mark the command as complete - break; - case HDC.REG_DATA.CMD.RAM_DIAGNOSTIC: // 0xE0 - case HDC.REG_DATA.CMD.CTL_DIAGNOSTIC: // 0xE4 - this.beginResult(HDC.REG_DATA.STATUS_OK | bDrive); - bCmd = -1; // mark the command as complete - break; + } + if (drive) this.verifyDrive(drive); + bDataStatus = HDC.REG_DATA.STATUS_OK; + if (!drive && this.iDriveAllowFail == iDrive) { + this.iDriveAllowFail = -1; + if (DEBUG) this.messageDebugger("HDC.doCmd(): fake failure triggered"); + bDataStatus = HDC.REG_DATA.STATUS_ERROR; + } + this.beginResult(bDataStatus | bDrive); + bCmd = -1; // mark the command as complete + break; + case HDC.REG_DATA.CMD.RAM_DIAGNOSTIC: // 0xE0 + case HDC.REG_DATA.CMD.CTL_DIAGNOSTIC: // 0xE4 + this.beginResult(HDC.REG_DATA.STATUS_OK | bDrive); + bCmd = -1; // mark the command as complete + break; + default: + break; } if (bCmd >= 0) { @@ -1286,46 +1288,46 @@ HDC.prototype.doCmd = function() { drive.senseCode = 0; } switch (bCmd) { - case HDC.REG_DATA.CMD.TEST_READY: // 0x00 - this.beginResult(HDC.REG_DATA.STATUS_OK | bDrive); - break; - case HDC.REG_DATA.CMD.RECALIBRATE: // 0x01 - drive.bControl = bControl; - if (DEBUG) this.messageDebugger("HDC.doCmd(): drive " + iDrive + " control byte: 0x" + str.toHexByte(bControl)); - this.beginResult(HDC.REG_DATA.STATUS_OK | bDrive); - break; - case HDC.REG_DATA.CMD.READ_VERIFY: // 0x05 - /* - * This is a non-DMA operation, so we simply pretend everything is OK for now; TODO: Revisit. - */ - this.beginResult(HDC.REG_DATA.STATUS_OK | bDrive); - break; - case HDC.REG_DATA.CMD.READ_DATA: // 0x08 - this.doRead(drive, function(bStatus) { - hdc.beginResult(bStatus | bDrive); - }); - break; - case HDC.REG_DATA.CMD.WRITE_DATA: // 0x0A - /* - * QUESTION: The IBM TechRef (p1-188) implies that bCount is used as part of HDC.REG_DATA.CMD.WRITE_DATA command, - * but it is omitted from the HDC.REG_DATA.CMD.READ_DATA command. Is that correct? Note that, as far as the length - * of the transfer is concerned, we rely exclusively on the DMA controller being programmed with the - * appropriate byte count. - */ - this.doWrite(drive, function(bStatus) { - hdc.beginResult(bStatus | bDrive); - }); - break; - case HDC.REG_DATA.CMD.WRITE_BUFFER: // 0x0F - this.doWriteToBuffer(drive, function(bStatus) { - hdc.beginResult(bStatus | bDrive); - }); - break; - default: - if (DEBUG) this.messageDebugger((bCmd < 0? "HDC.doCmd(): invalid drive" : "unsupported operation") + " (command=0x" + str.toHexByte(bCmdOrig) + ",drive=" + iDrive + ")"); - this.beginResult(HDC.REG_DATA.STATUS_ERROR | bDrive); - if (DEBUG && DEBUGGER && this.dbg && this.dbg.messageEnabled(this.dbg.MESSAGE_HDC) && bCmd >= 0) this.cpu.haltCPU(); - break; + case HDC.REG_DATA.CMD.TEST_READY: // 0x00 + this.beginResult(HDC.REG_DATA.STATUS_OK | bDrive); + break; + case HDC.REG_DATA.CMD.RECALIBRATE: // 0x01 + drive.bControl = bControl; + if (DEBUG) this.messageDebugger("HDC.doCmd(): drive " + iDrive + " control byte: 0x" + str.toHexByte(bControl)); + this.beginResult(HDC.REG_DATA.STATUS_OK | bDrive); + break; + case HDC.REG_DATA.CMD.READ_VERIFY: // 0x05 + /* + * This is a non-DMA operation, so we simply pretend everything is OK for now; TODO: Revisit. + */ + this.beginResult(HDC.REG_DATA.STATUS_OK | bDrive); + break; + case HDC.REG_DATA.CMD.READ_DATA: // 0x08 + this.doRead(drive, function(bStatus) { + hdc.beginResult(bStatus | bDrive); + }); + break; + case HDC.REG_DATA.CMD.WRITE_DATA: // 0x0A + /* + * QUESTION: The IBM TechRef (p1-188) implies that bCount is used as part of HDC.REG_DATA.CMD.WRITE_DATA command, + * but it is omitted from the HDC.REG_DATA.CMD.READ_DATA command. Is that correct? Note that, as far as the length + * of the transfer is concerned, we rely exclusively on the DMA controller being programmed with the + * appropriate byte count. + */ + this.doWrite(drive, function(bStatus) { + hdc.beginResult(bStatus | bDrive); + }); + break; + case HDC.REG_DATA.CMD.WRITE_BUFFER: // 0x0F + this.doWriteToBuffer(drive, function(bStatus) { + hdc.beginResult(bStatus | bDrive); + }); + break; + default: + if (DEBUG) this.messageDebugger((bCmd < 0? "HDC.doCmd(): invalid drive" : "unsupported operation") + " (command=0x" + str.toHexByte(bCmdOrig) + ",drive=" + iDrive + ")"); + this.beginResult(HDC.REG_DATA.STATUS_ERROR | bDrive); + if (DEBUG && DEBUGGER && this.dbg && this.dbg.messageEnabled(this.dbg.MESSAGE_HDC) && bCmd >= 0) this.cpu.haltCPU(); + break; } } }; diff --git a/my_modules/pcjs-client/lib/video.js b/my_modules/pcjs-client/lib/video.js index 4475b0f2c..967584421 100644 --- a/my_modules/pcjs-client/lib/video.js +++ b/my_modules/pcjs-client/lib/video.js @@ -2268,7 +2268,7 @@ Video.prototype.reset = function() * on the EGA's own switch settings instead. */ if (this.chipset) { - nMonitorType = this.chipset.getSW1VideoMonitor(); + nMonitorType = this.chipset.getSWVideoMonitor(); } var fEGA = false; diff --git a/versions/pcjs/1.15.3/pc-dbg.js b/versions/pcjs/1.15.3/pc-dbg.js index 024280b08..ab9b033bf 100644 --- a/versions/pcjs/1.15.3/pc-dbg.js +++ b/versions/pcjs/1.15.3/pc-dbg.js @@ -7,95 +7,95 @@ n.send(r)}else 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-16,this.Ob=2,this.ac=this.jb=7,this.gh=0,this.Ck=7,this.Ek=13,this.Gk=7,this.Fk=11,this.Dk=16,this.Ak=3,this.zi=6,this.Bk=2,this.zk=13,this.Ai=this.Bi=5,this.Zf=2,this.Yf=7,this.Uk=23,this.Vk=0,this.Wk=1,this.Xk=3,this.Tk=17,this.Ci=7,this.Zk=11,this.Pb=7,this.Qb=3,this.al=7,this.$k=11,this.Yk=15,this.ub=2,this.bl=3,this.Di=7,this.dl=this.Ii=this.cl=8,this.Ji=this.Hi=4,this.il=2,this.hl=3,this.fl=5,this.gl=2,this.el=3,this.Ki=5,this.Li=3,this.Ik=14,this.Kk=22,this.Hk=17,this.Jk=25,this.Mk=17,this.Ok= -25,this.Lk=20,this.Nk=28,this.kl=13,this.ml=21,this.jl=16,this.ll=24,this.Qk=13,this.Sk=21,this.Pk=16,this.Rk=24,this.ag=2,this.$f=7,this.Pi=this.Qi=5,this.nl=19,this.ol=this.bc=5,this.pl=17,this.hc=3,this.ql=5,this.bg=3,this.Gb=0,this.wi=8,this.xi=5,this.yi=9,this.Fi=this.Ei=5,this.Gi=4,this.Ni=this.Mi=5,this.Oi=4,this.Ri=7,this.Si=5,this.Ti=8,this.Xi=3,this.Yi=4,this.Zi=3,this.ul=this.rl=11,this.tl=this.sl=15,this.vl=7,this.Vi=5,this.Ui=8,this.Wi=0,this.bj=2,this.cg=6,this.aj=3,this.$i=6,this.dj= -3,this.wl=this.cj=5));this.vg=[];this.uf=[];this.Hg=0;this.ya=[];this.oe=this.Ab=this.hb=this.Ya=this.se=0;this.T=this.pm;this.U=this.qm;this.N=this.nn;this.O=this.on;this.Q=this.Eo;this.R=this.Fo;xc(this)}w(zb,$b);k=$b.prototype;k.ki=function(a,b,c,d,e){this.ya=a;this.oe=this.Ab=b;this.hb=c;this.Ya=d;this.se=e};k.reset=function(){this.Fb&&this.sb();xc(this);Bb(this);this.ad=!1}; -function xc(a){a.G=0;a.B=0;a.I=0;a.J=0;a.X=0;a.H=0;a.F=0;a.D=0;a.Sc=65520;a.Wc=0;a.ne=1023;a.yc={hj:0,na:0,Sa:0,Zg:-1};a.qa=new Pb(a,"CS");a.Hb=new Pb(a,"DS");a.wb=new Pb(a,"SS");a.Ua=new Pb(a,"ES");a.Ml=new Pb(a,"ZERO");yc(a,0,65535);80286<=a.Ha&&(a.Gc=a.Re=0,a.Fd=new Pb(a,"LDT",!0),a.mg=new Pb(a,"TSS",!0),a.Ib=new Pb(a,"VER",!0),yc(a,65520,61440),a.qa.Ia=16711680);zc(a,0);Ac(a);a.bb=0;a.vb=a.gg=-1;a.Bg=0;a.ga=a.Fa=-1;a.C=a.Hb;a.M=a.wb;a.Z=a.va=0} -k.jk=function(){var a=this.G+this.B+this.I+this.J+this.X+this.H+this.F+this.D|0;return a=a+this.pa+this.qa.na+this.Hb.na+this.wb.na+this.Ua.na+Bc(this)|0};function Cc(a,b,c,d){void 0!==d&&(void 0===a.vg[b]&&(a.vg[b]=[]),a.vg[b].push([c,d]))}function Dc(a,b,c){void 0!==c&&(void 0===a.uf[b]&&(a.uf[b]=[]),a.uf[b].push(c),a.Hg++)}function Ec(a,b){var c=a.uf[b];if(void 0!==c){for(;0>1?128:0} +0,0,1,1,0,1,0,0,1];function Pb(a,b,c){this.S=a;this.Ia=this.na=0;this.Ec=65535;this.Dc=this.Ua=0;this.jg=b;Qb(this,c)}function Rb(a){this.na=a;this.Ec=65535;return this.Ia=a<<4} +function Sb(a){var b,c;a&4?(b=this.S.Id.Ia,c=this.S.Id.Ec):(b=this.S.Jc,c=this.S.Re);var d=b+(a&65528);if(d+7<=c){this.Nc=Tb;this.Vb=Ub;this.S.A-=15;c=this.S.Ha(d+0);b=this.S.Ha(d+4);var d=this.S.Ha(d+2)|(b&255)<<16,e=b&7936;if(e&4096){2048==(e&2560)&&(this.Vb=Vb);if(e&2048||!(e&512))this.Vb=Wb;this.na=a;this.Ec=c;this.Ua=b;this.Dc=(b&24576)>>13;return this.Ia=d}if(e&&768>=e)return this.na=a,this.Ec=c,this.Ua=b,this.Dc=(b&24576)>>13,this.Ia=d}return-1}function Xb(a){return this.Ia+a} +function Yb(a){return this.Ia+a}function Tb(a,b,c){return a+b<=this.Ec?this.Ia+a:Vb.call(this,0,0,c)}function Vb(a,b,c){c||Zb.call(this.S,13,0);return-1}function Ub(a,b,c){return a+b<=this.Ec?this.Ia+a:Wb.call(this,0,0,c)}function Wb(a,b,c){c||Zb.call(this.S,13,0);return-1}Pb.prototype.save=function(){return[this.na,this.Ia,this.Ec,this.Ua,this.Dc,this.jg]};Pb.prototype.restore=function(a){"number"==typeof a?this.load(a):(this.na=a[0],this.Ia=a[1],this.Ec=a[2],this.Ua=a[3],this.Dc=a[4],this.jg=a[5])}; +function Qb(a,b){void 0===b&&(b=!!(a.S.Vc&1));b?(a.load=Sb,a.Nc=Tb,a.Vb=Ub):(a.load=Rb,a.Nc=Xb,a.Vb=Yb)} +function $b(a){this.Ea=a.model||8088;var b=0;switch(this.Ea){default:case 8088:b=4772727;break;case 80286:b=6E6}zb.call(this,a,b);this.Ej=61442;this.tg=4;this.jf=255;this.hj=4;this.$=5;this.ta=6;this.ea=7;this.fa=8;this.P=9;this.V=11;this.W=12;this.Be=4;this.zk=60;this.Ak=83;this.Rb=3;this.kb=9;this.dc=16;this.hh=1;this.Ek=19;this.Gk=28;this.Ik=16;this.Hk=21;this.Fk=37;this.Ck=2;this.Ai=9;this.Dk=5;this.Bk=33;this.Ci=10;this.Bi=8;this.Zf=3;this.Yf=15;this.Wk=51;this.Xk=1;this.Yk=2;this.Zk=4;this.Vk= +32;this.al=this.Di=15;this.Sb=16;this.Tb=4;this.cl=11;this.bl=18;this.$k=24;this.wb=4;this.dl=2;this.Ei=16;this.el=17;this.Ji=18;this.fl=19;this.Ii=5;this.Ki=6;this.kl=2;this.jl=8;this.hl=9;this.Mi=this.Li=this.gl=this.il=10;this.Kk=80;this.Mk=144;this.Jk=86;this.Lk=154;this.Ok=101;this.Qk=165;this.Nk=107;this.Pk=171;this.ml=70;this.ol=113;this.ll=76;this.nl=124;this.Sk=80;this.Uk=128;this.Rk=86;this.Tk=134;this.ag=3;this.$f=16;this.Ri=10;this.Qi=8;this.pl=51;this.ec=8;this.ql=17;this.rl=36;this.kc= +11;this.sl=16;this.bg=10;this.Kb=2;this.xi=18;this.yi=9-this.Kb;this.zi=17-this.Kb;this.Fi=12;this.Gi=9-this.Kb;this.Hi=13-this.Kb;this.Ni=18;this.Oi=9-this.Kb;this.Pi=17-this.Kb;this.Si=15;this.Ti=9-this.Kb;this.Ui=15-this.Kb;this.Yi=11;this.Zi=9-this.Kb;this.$i=10-this.Kb;this.tl=8;this.wl=12;this.ul=18;this.vl=17;this.xl=15;this.Wi=8;this.Vi=20;this.Xi=2;this.cj=3;this.cg=9;this.bj=5;this.aj=11;this.ej=4;this.dj=17;this.yl=11;this.La=ac.slice();80186<=this.Ea&&(this.jf=31,this.La[15]=H,this.La[96]= +bc,this.La[97]=cc,this.La[98]=dc,this.La[99]=H,this.La[100]=H,this.La[101]=H,this.La[102]=H,this.La[103]=H,this.La[104]=ec,this.La[105]=fc,this.La[106]=gc,this.La[107]=hc,this.La[108]=ic,this.La[109]=jc,this.La[110]=kc,this.La[111]=lc,this.La[192]=mc,this.La[193]=nc,this.La[200]=oc,this.La[200]=pc,this.La[241]=qc,rc[7]=sc,tc[7]=sc,80286<=this.Ea&&(this.Ej=2,this.tg=0,this.La[15]=uc,this.La[99]=vc,this.La[84]=wc,this.P=this.fa=this.ea=this.ta=this.$=this.hj=0,this.W=this.V=1,this.Be=3,this.zk=14,this.Ak= +16,this.Rb=2,this.dc=this.kb=7,this.hh=0,this.Ek=7,this.Gk=13,this.Ik=7,this.Hk=11,this.Fk=16,this.Ck=3,this.Ai=6,this.Dk=2,this.Bk=13,this.Bi=this.Ci=5,this.Zf=2,this.Yf=7,this.Wk=23,this.Xk=0,this.Yk=1,this.Zk=3,this.Vk=17,this.Di=7,this.al=11,this.Sb=7,this.Tb=3,this.cl=7,this.bl=11,this.$k=15,this.wb=2,this.dl=3,this.Ei=7,this.fl=this.Ji=this.el=8,this.Ki=this.Ii=4,this.kl=2,this.jl=3,this.hl=5,this.il=2,this.gl=3,this.Li=5,this.Mi=3,this.Kk=14,this.Mk=22,this.Jk=17,this.Lk=25,this.Ok=17,this.Qk= +25,this.Nk=20,this.Pk=28,this.ml=13,this.ol=21,this.ll=16,this.nl=24,this.Sk=13,this.Uk=21,this.Rk=16,this.Tk=24,this.ag=2,this.$f=7,this.Qi=this.Ri=5,this.pl=19,this.ql=this.ec=5,this.rl=17,this.kc=3,this.sl=5,this.bg=3,this.Kb=0,this.xi=8,this.yi=5,this.zi=9,this.Gi=this.Fi=5,this.Hi=4,this.Oi=this.Ni=5,this.Pi=4,this.Si=7,this.Ti=5,this.Ui=8,this.Yi=3,this.Zi=4,this.$i=3,this.wl=this.tl=11,this.vl=this.ul=15,this.xl=7,this.Wi=5,this.Vi=8,this.Xi=0,this.cj=2,this.cg=6,this.bj=3,this.aj=6,this.ej= +3,this.yl=this.dj=5));this.vg=[];this.uf=[];this.Hg=0;this.ya=[];this.oe=this.Db=this.ib=this.Za=this.se=0;this.T=this.nm;this.U=this.om;this.N=this.nn;this.O=this.on;this.Q=this.Fo;this.R=this.Go;xc(this)}w(zb,$b);k=$b.prototype;k.li=function(a,b,c,d,e){this.ya=a;this.oe=this.Db=b;this.ib=c;this.Za=d;this.se=e};k.reset=function(){this.Ib&&this.ub();xc(this);Bb(this);this.ed=!1}; +function xc(a){a.G=0;a.B=0;a.I=0;a.J=0;a.X=0;a.H=0;a.F=0;a.D=0;a.Vc=65520;a.Zc=0;a.ne=1023;a.Ac={ij:0,na:0,Ua:0,Zg:-1};a.qa=new Pb(a,"CS");a.Lb=new Pb(a,"DS");a.yb=new Pb(a,"SS");a.Wa=new Pb(a,"ES");a.Ol=new Pb(a,"ZERO");yc(a,0,65535);80286<=a.Ea&&(a.Jc=a.Re=0,a.Id=new Pb(a,"LDT",!0),a.mg=new Pb(a,"TSS",!0),a.Mb=new Pb(a,"VER",!0),yc(a,65520,61440),a.qa.Ia=16711680);zc(a,0);Ac(a);a.cb=0;a.xb=a.gg=-1;a.Bg=0;a.ga=a.Ga=-1;a.C=a.Lb;a.M=a.yb;a.Z=a.va=0} +k.mk=function(){var a=this.G+this.B+this.I+this.J+this.X+this.H+this.F+this.D|0;return a=a+this.pa+this.qa.na+this.Lb.na+this.yb.na+this.Wa.na+Bc(this)|0};function Cc(a,b,c,d){void 0!==d&&(void 0===a.vg[b]&&(a.vg[b]=[]),a.vg[b].push([c,d]))}function Dc(a,b,c){void 0!==c&&(void 0===a.uf[b]&&(a.uf[b]=[]),a.uf[b].push(c),a.Hg++)}function Ec(a,b){var c=a.uf[b];if(void 0!==c){for(;0>1?128:0} function Wc(a){return(a.ia^a.ka^a.ia>>1)&a.ba>>1?2048:0}function Xc(a){a.Y&=~a.ba}function Yc(a){a.ka=a.ia&16|a.ka&-17}function Zc(a){a.Y|=a.ba-1}function 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+function Gi(a){var b=[];if(void 0!==a.Wf){b[0]=a.Sb;b[1]=a.bc;b[2]=a.Oe;b[3]=a.uf;b[4]=a.lc|a.Vf<<8;b[5]=a.Ob;if(5==a.Wf){var c=[];c[0]=a.pd;c[1]=a.Td;c[2]=a.Dd;c[3]=a.vi;c[4]=a.ag;c[5]=a.eh;c[6]=a.pe;c[7]=a.Bf;c[8]=a.hh;c[9]=a.ih;c[10]=a.oe;c[11]=a.de;c[12]=a.cb;c[13]=a.tc;var d;a:if(d=a.Gd){var e=0,f=[];if(void 0!==d[0])for(var l=0;2>l;l++)for(var k=l;k>1;f[e++]=m;k=n}if(f.length>1&255,d=d>>8&-129,d>>4==(d&15)&&(d^=15)):(c=d&255,d=(d&256?7:112)|8&d>>8),Va(this.la,b,c|d<<8);gb(this,!0)}};function Ni(a){a.ha.ag&1?(a.sc=a.Jg,a.Hb=a.ha):(a.sc=a.ha,a.Hb=a.Kf)}g.save=function(){var a=new I(this);a.set(0,Gi(this.Jg));a.set(1,Gi(this.Kf));a.set(2,[this.ud,this.Hc,this.td]);a.set(3,Gi(this.ha));return a.data()}; +g.restore=function(a){var b=a[2];this.ud=b[0];this.Hc=b[1];this.td=b[2];this.xa=null;this.sc=this.Jg=new Ai(this,1,a[0]);this.Hb=this.Kf=new Ai(this,3,a[1]);this.ha=new Ai(this,5,a[3],this.tc);this.ha.Sb&&Ni(this);Oi(this);if(!Qi(this))return!1;Ri(this);return!0}; g.em=function(a,b,c){if(c)C(this,"Unable to load font ROM image (error "+c+")");else{try{var d=eval("("+b+")");if(!d.length){this.error("Empty font ROM image: "+a);return}if(1==d.length){this.error(d[0]);return}if(8192==d.length)gi(this,d,[0,6144]);else{C(this,"Unrecognized font data length ("+d.length+")");return}}catch(e){C(this,"Font ROM data error: "+e.message);return}this.Ka()}}; -function Si(a,b){if(1==b)return a.Ic[0]=W[0],a.Ic[1]=W[7],a.Ic;if(2==b){var c=a.xa.Oe;if(a.xa===a.ha){var d=a.ha.Dd[0],c=d&7;d&16&&(c|=8);18!=a.ha.Dd[1]&&(c|=32)}a.Ic[0]=W[c&15];c=c&32?xi:wi;for(d=0;dfb||!aa?fb:8,kd=Oh.createImageData(n.Nb,n.Ob),sa=0;256>sa;sa++){for(Ra= -0;Ra=fb-2,Rj=oc[Ra>(8<=rb&&176<=sa&&223>=sa?7:rb)?r:jd;Vi(kd,Ph,Qh,Rh);K&&Vi(kd,Ph+1,Qh,Rh)}Oh.putImageData(kd,(sa&15)*n.Nb,(sa>>4)*n.Ob)}n.ce[x]="#"+ba(r[0])+ba(r[1])+ba(r[2]);n.Ci[x]=r;n.wg[x]=pc;n=!0}}a.bd[b]=s;return n}function Wi(a){0a.Nd&&(a.Nd=0):a.Nd=-1} -function Ri(a){if(a.tb){for(var b=10;15>=b;b++)if(null==a.xa.Lb[b])return;var c=a.xa.Lb[10],b=c&31,d=a.xa.Lb[11]&31,e=a.xa.Lb[9]&31,f=!1;a.xa===a.ha&&(f=!0,7!=e||4!=b||d||(d=7));if(c&32||b>d&&!f||b>e)Xi(a);else{c=a.xa.Lb[15]+((a.xa.Lb[14]&63)<<8);a.jc!=c&&(Xi(a),a.jc=c);d=d-b+1;if(a.Gk!=b||a.Ri!=d)a.Gk=b,a.Ri=d;a.kd=e+1;Wi(a)}}} -function Xi(a){if(0<=a.jc){if(void 0!==a.Bb){var b=a.Bb[a.jc];if(b&131072){var b=b&-131073,c=a.jc%a.cb,d=Math.floor(a.jc/a.cb);a.tb&&a.bd[a.tb]&&(a.je&&Yi(a,c,d,b,a.je),Yi(a,c,d,b));a.Bb[a.jc]=b}}a.jc=-1}} -function Zi(a){var b;a=a.xa;var c=a.de[5];if(null!=c){b=2;var d=512,e=a.de[3]&31;switch(c&3){case 0:if(e){d=1024;switch(e&24){case 8:d=1536;break;case 16:d=2560;break;case 24:d=3584}a.Dc=e&7}break;case 1:d=4096;break;case 2:switch(e&24){default:d=8192;break;case 8:d=24576;break;case 16:d=40960;break;case 24:d=57344}}c&8&&(b=16);c&16&&(b|=1,d|=256);b|=d}return b}g.zd=function(a){var b=this.xa;null!=a&&b&&a!=b.mh&&(b.rg(a),this.la.rg(b.Ra,b.Ub,b.Ge))}; -function Qi(a,b){var c,d=a.sd,e=a.xa;if(e)if(1==e.Wf)d=ri;else if(5==e.Wf){var d=null,f=e.qc>>2,l=32768f&&(d=c?13:14):c&&(d-=2));c=Zi(a)}}else e.Zb&8&&(e.Zb&2?(d=e.Zb&16?6:5,e.Zb&4||(d-=1)):(d=e.Zb&1?3:1,e.Zb&4&&(d-= -1)));else a.sd=null,null==d&&(d=a.Ec);if(!Pi(a,d,b))return!1;a.zd(c);return!0} -function Pi(a,b,c){if(null!=b&&(b!=a.sd||c)){a.Pk=0;a.sd=b;b=a.xa||(b==ri?a.pc:a.Eb);if(b!=a.xa||b.Ra!=a.Ra||b.Ub!=a.Ub){Xi(a);if(a.Ra){if(!Qa(a.la,a.Ra,a.Ub))return!1;a.xa&&(a.xa.Pb=!1)}a.xa=b;b.Pb=!0;a.Ra=b.Ra;a.Ub=b.Ub;if(!Oa(a.la,b.Ra,b.Ub,!1,b===a.ha?b:null))return!1}a.tb=0;a.cb=a.gg;a.Sb=a.th;a.oh=V[ri][2];b=0;var d=V[a.sd];d&&(a.cb=d[0],a.Sb=d[1],a.oh=d[2],b=d[3]||0,a.tb=d[4],4==a.td&&a.xa===a.ha&&3==a.tb&&(7==a.ha.Lb[9]?a.Sb=43:a.tb=5));a.kj=a.cb*a.Sb;a.dg=a.kj/a.oh;a.Jg=(a.dg<<1)+b;a.Pi= -b?a.Jg+b>>1:0;13<=a.sd&&(a.dg<<=1);a.bd.length&&(a.Oc=Math.floor(a.Nc/a.cb),a.Pc=Math.floor(a.ld/a.Sb),a.tb?(b=a.bd[a.tb],d=a.bd[a.tb<<1],a.Wk&&80==a.cb?d&&a.Oc>=3*d.Nb>>2&&(a.tb<<=1,b=d):(d&&a.Oc>=d.Nb&&(a.tb<<=1,b=d),b&&(a.Oc=b.Nb,a.Pc=b.Ob)),a.Re=a.Se=0,b&&(a.Re=a.cb*b.Nb,a.Se=a.Sb*b.Ob)):(a.Oc=a.Pc=1,a.Re=a.cb,a.Se=a.Sb),a.Yf=a.rc.createImageData(a.Re,a.Se),a.ie=window.document.createElement("canvas"),a.ie.width=a.Re,a.ie.height=a.Se,a.je=a.ie.getContext("2d"),a.wi=a.xi=0,a.Lg=a.Nc,a.Mg=a.ld, -b=a.Nc-a.cb*a.Oc,d=a.ld-a.Sb*a.Pc,0>1,a.Lg-=b),0>1,a.Mg-=d),b||d)&&(a.rc.fillStyle=a.jb.style.backgroundColor,a.rc.fillRect(0,0,a.Nc,a.ld));!1!==c?gb(a,!0):$i(a,!0)}return!0}function Vi(a,b,c,d){b=(b+c*a.width)*d.length;a.data[b+0]=d[0];a.data[b+1]=d[1];a.data[b+2]=d[2];a.data[b+3]=d[3]}function $i(a,b){var c;if(b){if(c=a.dg,void 0===a.Bb||a.Bb.length!=c)a.Bb=Array(c)}else{if(void 0===a.Bb)return;c=a.Bb.length}for(var d=0;d>8;d=l&15;var k=a.bd[a.tb];k.Ce&&(d=k.Ce[d]);var m=l>>4&15;k.Ce&&(m=k.Ce[m]);e?(b*=k.Nb,c*=k.Ob,e.fillStyle=k.ce[m],e.fillRect(b,c,k.Nb,k.Ob)):(b=b*a.Oc+a.wi,c=c*a.Pc+a.xi,a.rc.fillStyle=k.ce[m],a.rc.fillRect(b,c,a.Oc,a.Pc));l&256&&(m=(f&15)*k.Nb,f=(f>>4)*k.Ob,e?e.drawImage(k.wg[d],m,f,k.Nb,k.Ob,b,c,k.Nb,k.Ob):a.rc.drawImage(k.wg[d],m,f,k.Nb,k.Ob,b,c,a.Oc,a.Pc));l&512&&(f=a.Gk,l=a.Ri,e?(a.kd&&a.kd!==k.Ob&&(f=Math.floor(f*k.Ob/a.kd),l=Math.floor(l*k.Ob/a.kd)), -e.fillStyle=k.ce[d],e.fillRect(b,c+f,k.Nb,l)):(a.kd&&a.kd!==a.Pc&&(f=Math.floor(f*a.Pc/a.kd),l=Math.floor(l*a.Pc/a.kd)),a.rc.fillStyle=k.ce[d],a.rc.fillRect(b,c+f,a.Oc,l)))} -function gb(a,b){if(a.rb){var c=!1;a.xa&&(a.xa===a.ha?a.ha.Td&32&&(c=!0):a.xa.Zb&8&&(c=!0));if(c||b){if(b)$i(a,!0);else if(void 0===a.Bb)return;var d=!1;!(b||++a.Pk&15)&&0<=a.Nd&&(a.Nd++,d=!0);var e=0,f=a.kj,c=a.xa.Ra,l=c+a.xa.Ub,k=(a.xa.Lb[12]<<8)+a.xa.Lb[13];a.tb&&(k<<=1);var c=c+k,m=a.Jg;c+m>l&&(m=l-c,0>m&&(m=0));l=c+m;if(k=!b){for(var k=a.la,n=!0,q=c>>k.yb;0a.jc)return;e=a.jc;f=e+1}}if(a.tb){if(a.bd[a.tb]){d= -0;k=a.Md=0;m=1048575;a.xa.Zb&32&&(k=32768,m&=~k,a.Nd&2||(m&=-65537));for(c+=e<<1;c>8| -(s&255)<<8;r=k;var fb=16;q>=m))>>(fb-=m);Vi(a.Yf,q++,x,n[jd])}q>T&&(T=q);x=eb&&(eb=x+1)}e+=2;l++;if(q>=a.cb){q=0;x+=2;if(x>a.Sb)break;x==a.Sb&&(x=1,e=c+a.Pi)}}Kaa;aa++)eb=X[T&2155905152], -Vi(a.Yf,k++,m,l[eb]),T<<=1;k>q&&(q=k);m=K&&(K=m+1)}e++;if(k>=a.cb&&(k=0,++m>a.Sb))break}n>2),a=this.ha.ti&-17|(this.Ef&1<e&&(e=0);e%b.rh>b.Zl&&(c|=1);e%=b.nj;e>b.am&&(c|=8);b.wh=d-e;b===a.ha?(c|=b.uf&48^48,b.md=!1):c=(b.uf^=9)|240;return b.uf=c} -var Hi={948:U.prototype.Dl,949:U.prototype.Cl,952:U.prototype.El,954:U.prototype.Fl,980:U.prototype.il,981:U.prototype.hl,984:U.prototype.jl,985:U.prototype.gl,986:U.prototype.kl},Ii={948:U.prototype.Gm,949:U.prototype.Fm,952:U.prototype.Hm,980:U.prototype.nm,981:U.prototype.mm,984:U.prototype.om,985:U.prototype.lm},Ji={960:U.prototype.gj,961:U.prototype.gj,962:U.prototype.Pl,964:U.prototype.Ol,965:U.prototype.Nl,970:U.prototype.tl,972:U.prototype.sl,974:U.prototype.rl,975:U.prototype.ql},Ki={954:U.prototype.rk, -960:U.prototype.qk,961:U.prototype.qk,962:U.prototype.Jm,964:U.prototype.Qm,965:U.prototype.Pm,970:U.prototype.xm,972:U.prototype.wm,974:U.prototype.vm,975:U.prototype.um,986:U.prototype.rk}; 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