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This commit is contained in:
Jeff Parsons
parent
faf179d2d3
commit
34992a1d74
1 changed files with 23 additions and 23 deletions
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@ -1196,7 +1196,7 @@ Card.STATUS1 = {
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* 5: SecRed
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* 5: SecRed
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*/
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*/
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Card.ATC = {
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Card.ATC = {
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PORT: 0x3C0,
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PORT: 0x3C0, // ATC Index/Data Port
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INDX_MASK: 0x1F,
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INDX_MASK: 0x1F,
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INDX_PAL_ENABLE: 0x20, // must be clear when loading palette registers
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INDX_PAL_ENABLE: 0x20, // must be clear when loading palette registers
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PALETTE: {
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PALETTE: {
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@ -1211,7 +1211,7 @@ Card.ATC = {
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},
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},
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PALETTE_REGS: 0x10, // 16 total palette registers
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PALETTE_REGS: 0x10, // 16 total palette registers
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MODE: {
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MODE: {
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INDX: 0x10, // Mode Control Register
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INDX: 0x10, // ATC Mode Control Register
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GRAPHICS: 0x01, // bit 0: set for graphics mode, clear for alphanumeric mode
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GRAPHICS: 0x01, // bit 0: set for graphics mode, clear for alphanumeric mode
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MONOEM: 0x02, // bit 1: set for monochrome emulation mode, clear for color emulation
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MONOEM: 0x02, // bit 1: set for monochrome emulation mode, clear for color emulation
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TEXTGRCC: 0x04, // bit 2: set for line graphics in character codes 0xC0-0xDF, clear otherwise
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TEXTGRCC: 0x04, // bit 2: set for line graphics in character codes 0xC0-0xDF, clear otherwise
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@ -1222,20 +1222,20 @@ Card.ATC = {
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COLORSEL: 0x80 // bit 7: set for P5,P4 mapped to bits 1,0 of the Color Select register
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COLORSEL: 0x80 // bit 7: set for P5,P4 mapped to bits 1,0 of the Color Select register
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},
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},
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OVERSCAN: {
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OVERSCAN: {
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INDX: 0x11 // Overscan Color Register
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INDX: 0x11 // ATC Overscan Color Register
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},
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},
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PLANES: {
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PLANES: {
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INDX: 0x12, // Color Plane Enable Register
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INDX: 0x12, // ATC Color Plane Enable Register
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MASK: 0x0F,
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MASK: 0x0F,
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MUX: 0x30,
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MUX: 0x30,
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RESERVED: 0xC0
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RESERVED: 0xC0
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},
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},
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HORZPAN: {
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HORZPAN: {
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INDX: 0x13, // Horizontal PEL Panning Register
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INDX: 0x13, // ATC Horizontal PEL Panning Register
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SHIFT_LEFT: 0x0F // bits 0-3 indicate # of PELs to shift left
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SHIFT_LEFT: 0x0F // bits 0-3 indicate # of PELs to shift left
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},
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},
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COLORSEL: {
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COLORSEL: {
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INDX: 0x14, // VGA ONLY: Color Select Register
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INDX: 0x14, // ATC Color Select Register (VGA only)
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S_COLOR_7: 0x08, // selects bit 7 of 8-bit color values sent to DAC (except 256-color modes)
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S_COLOR_7: 0x08, // selects bit 7 of 8-bit color values sent to DAC (except 256-color modes)
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S_COLOR_6: 0x04, // selects bit 6 of 8-bit color values sent to DAC (except 256-color modes)
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S_COLOR_6: 0x04, // selects bit 6 of 8-bit color values sent to DAC (except 256-color modes)
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S_COLOR_5: 0x02, // selects bit 5 of 8-bit color values sent to DAC
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S_COLOR_5: 0x02, // selects bit 5 of 8-bit color values sent to DAC
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@ -1305,11 +1305,11 @@ Card.VGA_ENABLE = {
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*/
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*/
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Card.SEQ = {
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Card.SEQ = {
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INDX: {
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INDX: {
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PORT: 0x3C4,
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PORT: 0x3C4, // Sequencer Index Port
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MASK: 0x07
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MASK: 0x07
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},
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},
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DATA: {
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DATA: {
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PORT: 0x3C5
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PORT: 0x3C5 // Sequencer Data Port
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},
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},
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RESET: {
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RESET: {
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INDX: 0x00, // Sequencer Reset Register
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INDX: 0x00, // Sequencer Reset Register
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@ -1401,23 +1401,23 @@ Card.GRC = {
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POS1_PORT: 0x3CC, // EGA only, write-only
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POS1_PORT: 0x3CC, // EGA only, write-only
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POS2_PORT: 0x3CA, // EGA only, write-only
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POS2_PORT: 0x3CA, // EGA only, write-only
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INDX: {
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INDX: {
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PORT: 0x3CE,
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PORT: 0x3CE, // GRC Index Port
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MASK: 0x0F
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MASK: 0x0F
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},
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},
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DATA: {
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DATA: {
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PORT: 0x3CF
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PORT: 0x3CF // GRC Data Port
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},
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},
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SRESET: {
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SRESET: {
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INDX: 0x00 // SET/RESET (write-only; each bit used only if WRITE_MODE is 0 and corresponding ESR bit set)
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INDX: 0x00 // GRC Set/Reset Register (write-only; each bit used only if WRITE_MODE is 0 and corresponding ESR bit set)
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},
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},
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ESRESET: {
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ESRESET: {
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INDX: 0x01 // ENABLE SET/RESET
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INDX: 0x01 // GRC Enable Set/Reset Register
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},
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},
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COLORCMP: {
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COLORCMP: {
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INDX: 0x02 // COLOR COMPARE
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INDX: 0x02 // GRC Color Compare Register
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},
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},
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DATAROT: {
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DATAROT: {
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INDX: 0x03, // DATA ROTATE
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INDX: 0x03, // GRC Data Rotate Register
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COUNT: 0x07,
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COUNT: 0x07,
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AND: 0x08,
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AND: 0x08,
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OR: 0x10,
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OR: 0x10,
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@ -1426,11 +1426,11 @@ Card.GRC = {
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MASK: 0x1F
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MASK: 0x1F
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},
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},
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READMAP: {
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READMAP: {
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INDX: 0x04, // READ MAP SELECT
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INDX: 0x04, // GRC Read Map Select Register
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NUM: 0x03
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NUM: 0x03
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},
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},
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MODE: {
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MODE: {
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INDX: 0x05, // MODE REGISTER
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INDX: 0x05, // GRC Mode Register
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WRITE_MODE0: 0x00, // write mode 0x0: each plane written with CPU data, rotated as needed, unless SR enabled
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WRITE_MODE0: 0x00, // write mode 0x0: each plane written with CPU data, rotated as needed, unless SR enabled
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WRITE_MODE1: 0x01, // write mode 0x1: each plane written with contents of the processor latches (loaded by a read)
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WRITE_MODE1: 0x01, // write mode 0x1: each plane written with contents of the processor latches (loaded by a read)
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WRITE_MODE2: 0x02, // write mode 0x2: memory plane N is written with 8 bits matching data bit N
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WRITE_MODE2: 0x02, // write mode 0x2: memory plane N is written with 8 bits matching data bit N
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@ -1444,7 +1444,7 @@ Card.GRC = {
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COLOR256: 0x40 // VGA only
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COLOR256: 0x40 // VGA only
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},
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},
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MISC: {
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MISC: {
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INDX: 0x06, // MISCELLANEOUS
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INDX: 0x06, // GRC Miscellaneous Register
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GRAPHICS: 0x01, // set for graphics mode addressing, clear for text mode addressing
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GRAPHICS: 0x01, // set for graphics mode addressing, clear for text mode addressing
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CHAIN: 0x02, // set for odd/even planes selected with odd/even values of the processor AO bit
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CHAIN: 0x02, // set for odd/even planes selected with odd/even values of the processor AO bit
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MAPMEM: 0x0C, //
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MAPMEM: 0x0C, //
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@ -1454,10 +1454,10 @@ Card.GRC = {
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MAPB832: 0x0C //
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MAPB832: 0x0C //
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},
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},
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COLORDC: {
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COLORDC: {
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INDX: 0x07 // COLOR DON'T CARE
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INDX: 0x07 // GRC Color "Don't Care" Register
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},
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},
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BITMASK: {
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BITMASK: {
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INDX: 0x08 // BIT MASK
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INDX: 0x08 // GRC Bit Mask Register
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},
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},
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TOTAL_REGS: 0x09
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TOTAL_REGS: 0x09
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};
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};
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@ -1534,8 +1534,8 @@ if (DEBUGGER) Card.GRC.REGS = ["SRESET","ESRESET","COLORCMP","DATAROT","READMAP"
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*/
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*/
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Card.ACCESS = {
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Card.ACCESS = {
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READ: { // READ values are designed to be OR'ed with WRITE values
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READ: { // READ values are designed to be OR'ed with WRITE values
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MODE0: 0x4000,
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MODE0: 0x0400,
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MODE1: 0x4100,
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MODE1: 0x0500,
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EVENODD: 0x1000,
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EVENODD: 0x1000,
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MASK: 0xFF00
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MASK: 0xFF00
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},
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},
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@ -1549,9 +1549,9 @@ Card.ACCESS = {
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AND: 0x0060,
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AND: 0x0060,
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OR: 0x00A0,
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OR: 0x00A0,
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XOR: 0x00E0,
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XOR: 0x00E0,
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MASK: 0x00FB // 0xFB ensures we strip any lingering V2 bit from the value
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MASK: 0x00F7 // 0xF7 ensures we strip any lingering V2 bit from the value
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},
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},
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V2: 0x0004 // this is a signature bit used ONLY to differentiate V2 access values from V1
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V2: 0x0008 // this is a signature bit used ONLY to differentiate V2 access values from V1
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};
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};
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/*
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/*
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