From 31e316d6367bb52b0e12b82081db805b30a08267 Mon Sep 17 00:00:00 2001 From: Jeff Parsons Date: Thu, 16 Jul 2015 13:14:34 -0700 Subject: [PATCH] Fixed 32-bit INC, DEC, NEG, NOT, TEST, MOVSB and MOVSW (several things that slipped through the cracks during 32-bit development) --- modules/pcjs/lib/x86func.js | 36 ++++++++++++++++++------------------ modules/pcjs/lib/x86ops.js | 8 ++++---- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/modules/pcjs/lib/x86func.js b/modules/pcjs/lib/x86func.js index 5bc81de8c..c2b74b636 100644 --- a/modules/pcjs/lib/x86func.js +++ b/modules/pcjs/lib/x86func.js @@ -448,9 +448,9 @@ X86.fnDECb = function DECb(dst, src) */ X86.fnDECr = function DECr(w) { - var result = ((w & this.dataMask) - 1)|0; - this.setArithResult(w, 1, result, X86.RESULT.WORD | X86.RESULT.NOTCF, true); - this.nStepCycles -= 2; // the register form of INC takes 2 cycles on all CPUs + var result = (w - 1)|0; + this.setArithResult(w, 1, result, this.dataType | X86.RESULT.NOTCF, true); + this.nStepCycles -= 2; // the register form of DEC takes 2 cycles on all CPUs return (w & ~this.dataMask) | (result & this.dataMask); }; @@ -465,9 +465,9 @@ X86.fnDECr = function DECr(w) X86.fnDECw = function DECw(dst, src) { var w = (dst - 1)|0; - this.setArithResult(dst, 1, w, X86.RESULT.WORD | X86.RESULT.NOTCF, true); + this.setArithResult(dst, 1, w, this.dataType | X86.RESULT.NOTCF, true); this.nStepCycles -= (this.regEA === X86.ADDR_INVALID? this.cycleCounts.nOpCyclesIncR : this.cycleCounts.nOpCyclesIncM); - return w & 0xffff; + return w & this.dataMask; }; /** @@ -1168,8 +1168,8 @@ X86.fnINCb = function INCb(dst, src) */ X86.fnINCr = function INCr(w) { - var result = ((w & this.dataMask) + 1)|0; - this.setArithResult(w, 1, result, X86.RESULT.WORD | X86.RESULT.NOTCF); + var result = (w + 1)|0; + this.setArithResult(w, 1, result, this.dataType | X86.RESULT.NOTCF); this.nStepCycles -= 2; // the register form of INC takes 2 cycles on all CPUs return (w & ~this.dataMask) | (result & this.dataMask); }; @@ -1185,9 +1185,9 @@ X86.fnINCr = function INCr(w) X86.fnINCw = function INCw(dst, src) { var w = (dst + 1)|0; - this.setArithResult(dst, 1, w, X86.RESULT.WORD | X86.RESULT.NOTCF); + this.setArithResult(dst, 1, w, this.dataType | X86.RESULT.NOTCF); this.nStepCycles -= (this.regEA === X86.ADDR_INVALID? this.cycleCounts.nOpCyclesIncR : this.cycleCounts.nOpCyclesIncM); - return w & 0xffff; + return w & this.dataMask; }; /** @@ -1858,9 +1858,9 @@ X86.fnNEGb = function NEGb(dst, src) X86.fnNEGw = function NEGw(dst, src) { var w = (-dst)|0; - this.setArithResult(0, dst, w, X86.RESULT.WORD | X86.RESULT.ALL, true); + this.setArithResult(0, dst, w, this.dataType | X86.RESULT.ALL, true); this.nStepCycles -= (this.regEA === X86.ADDR_INVALID? this.cycleCounts.nOpCyclesNegR : this.cycleCounts.nOpCyclesNegM); - return w & 0xffff; + return w & this.dataMask; }; /** @@ -1888,7 +1888,7 @@ X86.fnNOTb = function NOTb(dst, src) X86.fnNOTw = function NOTw(dst, src) { this.nStepCycles -= (this.regEA === X86.ADDR_INVALID? this.cycleCounts.nOpCyclesNegR : this.cycleCounts.nOpCyclesNegM); - return dst ^ 0xffff; + return dst ^ this.dataMask; }; /** @@ -3169,14 +3169,14 @@ X86.fnSUBw = function SUBw(dst, src) }; /** - * fnTEST8(dst, src) + * fnTESTib(dst, src) * * @this {X86CPU} * @param {number} dst * @param {number} src (null; we have to supply the source ourselves) * @return {number} */ -X86.fnTEST8 = function TEST8(dst, src) +X86.fnTESTib = function TESTib(dst, src) { src = this.getIPByte(); this.setLogicResult(dst & src, X86.RESULT.BYTE); @@ -3186,17 +3186,17 @@ X86.fnTEST8 = function TEST8(dst, src) }; /** - * fnTEST16(dst, src) + * fnTESTiw(dst, src) * * @this {X86CPU} * @param {number} dst * @param {number} src (null; we have to supply the source ourselves) * @return {number} */ -X86.fnTEST16 = function TEST16(dst, src) +X86.fnTESTiw = function TESTiw(dst, src) { src = this.getIPWord(); - this.setLogicResult(dst & src, X86.RESULT.WORD); + this.setLogicResult(dst & src, this.dataType); this.nStepCycles -= (this.regEA === X86.ADDR_INVALID? this.cycleCounts.nOpCyclesTestRI : this.cycleCounts.nOpCyclesTestMI); this.opFlags |= X86.OPFLAG.NOWRITE; return dst; @@ -3228,7 +3228,7 @@ X86.fnTESTb = function TESTb(dst, src) */ X86.fnTESTw = function TESTw(dst, src) { - this.setLogicResult(dst & src, X86.RESULT.WORD); + this.setLogicResult(dst & src, this.dataType); this.nStepCycles -= (this.regEAWrite === X86.ADDR_INVALID? (this.regEA === X86.ADDR_INVALID? this.cycleCounts.nOpCyclesTestRR : this.cycleCounts.nOpCyclesTestRM) : this.cycleCounts.nOpCyclesTestRM); this.opFlags |= X86.OPFLAG.NOWRITE; return dst; diff --git a/modules/pcjs/lib/x86ops.js b/modules/pcjs/lib/x86ops.js index fde03e0d8..a4c7670ac 100644 --- a/modules/pcjs/lib/x86ops.js +++ b/modules/pcjs/lib/x86ops.js @@ -2549,7 +2549,7 @@ X86.opMOVSb = function MOVSb() } if (nReps--) { var nInc = ((this.regPS & X86.PS.DF)? -1 : 1); - this.setSOByte(this.segES, this.regEDI & this.addrMask, this.getSOByte(this.segData, this.regESI)); + this.setSOByte(this.segES, this.regEDI & this.addrMask, this.getSOByte(this.segData, this.regESI & this.addrMask)); this.regESI = (this.regESI & ~this.addrMask) | ((this.regESI + nInc) & this.addrMask); this.regEDI = (this.regEDI & ~this.addrMask) | ((this.regEDI + nInc) & this.addrMask); this.nStepCycles -= nCycles; @@ -2584,7 +2584,7 @@ X86.opMOVSw = function MOVSw() } if (nReps--) { var nInc = ((this.regPS & X86.PS.DF)? -this.dataSize : this.dataSize); - this.setSOWord(this.segES, this.regEDI & this.addrMask, this.getSOWord(this.segData, this.regESI)); + this.setSOWord(this.segES, this.regEDI & this.addrMask, this.getSOWord(this.segData, this.regESI & this.addrMask)); this.regESI = (this.regESI & ~this.addrMask) | ((this.regESI + nInc) & this.addrMask); this.regEDI = (this.regEDI & ~this.addrMask) | ((this.regEDI + nInc) & this.addrMask); this.nStepCycles -= nCycles; @@ -4210,12 +4210,12 @@ X86.aOpGrp2d = [ ]; X86.aOpGrp3b = [ - X86.fnTEST8, X86.fnGRPUndefined, X86.fnNOTb, X86.fnNEGb, // 0xF6(reg=0x0-0x3) + X86.fnTESTib, X86.fnGRPUndefined, X86.fnNOTb, X86.fnNEGb, // 0xF6(reg=0x0-0x3) X86.fnMULb, X86.fnIMULb, X86.fnDIVb, X86.fnIDIVb // 0xF6(reg=0x4-0x7) ]; X86.aOpGrp3w = [ - X86.fnTEST16, X86.fnGRPUndefined, X86.fnNOTw, X86.fnNEGw, // 0xF7(reg=0x0-0x3) + X86.fnTESTiw, X86.fnGRPUndefined, X86.fnNOTw, X86.fnNEGw, // 0xF7(reg=0x0-0x3) X86.fnMULw, X86.fnIMULw, X86.fnDIVw, X86.fnIDIVw // 0xF7(reg=0x4-0x7) ];