Protected-mode interrupt/trap gate fixes
This commit is contained in:
parent
6194aac5af
commit
311868bc95
19 changed files with 442 additions and 407 deletions
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@ -305,7 +305,7 @@ var X86Help = {
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* are there any other instructions that were, um, less explicit but also require a non-null selector?
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*/
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if ((src & X86.SEL.MASK) && this.segVER.load(src, true) != null) {
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var fConforming = ((this.segVER.acc & X86.DESC.ACC.TYPE.CODE_CONFORMING_EXECONLY) == X86.DESC.ACC.TYPE.CODE_CONFORMING_EXECONLY);
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var fConforming = ((this.segVER.acc & X86.DESC.ACC.TYPE.CODE_CONFORMING) == X86.DESC.ACC.TYPE.CODE_CONFORMING);
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if ((fConforming || this.segVER.dpl >= this.segCS.cpl) && this.segVER.dpl >= (src & X86.SEL.RPL)) {
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this.setZF();
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return this.segVER.limit;
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@ -453,18 +453,6 @@ var X86Help = {
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this.pushWord(regIP);
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}
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},
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/**
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* opHelpDIVOverflow()
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*
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* @this {X86CPU}
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*/
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opHelpDIVOverflow: function() {
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this.setIP(this.opEA - this.segCS.base);
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/*
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* TODO: Determine the proper cycle cost.
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*/
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X86Help.opHelpINT.call(this, X86.EXCEPTION.DIV_ERR, null, 2);
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},
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/**
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* opHelpINT(nIDT, nError, nCycles)
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*
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@ -478,6 +466,7 @@ var X86Help = {
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* TODO: We assess the cycle cost up front, because otherwise, if loadIDT() fails, no cost may be assessed.
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*/
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this.nStepCycles -= this.CYCLES.nOpCyclesInt + nCycles;
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this.segCS.fCall = true;
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var regPS = this.getPS();
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var regCS = this.segCS.sel;
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var regIP = this.regIP;
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@ -490,17 +479,6 @@ var X86Help = {
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if (nError != null) this.pushWord(nError);
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this.nFault = -1;
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}
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/*
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if (X86Help.opHelpLoadIDT.call(this, nIDT)) {
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if (this.descIDT.maskPS) {
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X86Help.opHelpPushPS.call(this, nError);
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} else {
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X86Help.opHelpSwitchTSS.call(this, this.descIDT.sel, true);
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}
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return;
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}
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X86Help.opHelpFault.call(this, X86.EXCEPTION.GP_FAULT, (nIDT << 3) | X86.ERRCODE.IDT | X86.ERRCODE.EXT, true);
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*/
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},
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/**
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* opHelpIRET()
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@ -516,7 +494,7 @@ var X86Help = {
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if (this.regPS & X86.PS.NT) {
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var addrNew = this.segTSS.base;
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var sel = this.getWord(addrNew + X86.TSS.PREV_TSS);
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X86Help.opHelpSwitchTSS.call(this, sel, false);
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X86Seg.switchTSS.call(this.segCS, sel, false);
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return;
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}
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}
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@ -529,137 +507,16 @@ var X86Help = {
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}
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},
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/**
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* opHelpLoadIDT(nIDT)
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*
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* Updates descIDT as follows:
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*
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* descIDT.off 0x0-0x1 offset of interrupt handler
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* descIDT.sel 0x2-0x3 selector of interrupt handler
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* descIDT.acc 0x4-0x5 access word (protected-mode only)
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* descIDT.maskPS mask to apply PS after saving current PS (0 if none; ie, task switch)
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* opHelpDIVOverflow()
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*
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* @this {X86CPU}
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* @param {number} nIDT
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* @return {boolean} true if successful, false if not (all failure cases currently limited to protected mode)
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*/
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opHelpLoadIDT: function(nIDT) {
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var offIDT;
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if (DEBUG) this.assert(nIDT >= 0 && nIDT < 256);
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if (this.regMSW & X86.MSW.PE) {
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offIDT = this.addrIDT + (nIDT << 3);
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if (offIDT + 7 > this.addrIDTLimit) {
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return false;
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}
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this.descIDT.off = this.getWord(offIDT);
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this.descIDT.sel = this.getWord(offIDT + 2);
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this.descIDT.acc = this.getWord(offIDT + 4);
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this.descIDT.maskPS = 0;
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switch (this.descIDT.acc & X86.DESC.ACC.TYPE.MASK) {
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case X86.DESC.ACC.TYPE.GATE_INT:
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this.descIDT.maskPS = ~(X86.PS.NT | X86.PS.TF | X86.PS.IF);
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break;
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case X86.DESC.ACC.TYPE.GATE_TRAP:
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this.descIDT.maskPS = ~(X86.PS.NT | X86.PS.TF);
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break;
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case X86.DESC.ACC.TYPE.GATE_TASK:
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break;
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default:
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if (DEBUG) this.assert(false, "INT 0x" + str.toHexByte(nIDT) + ": unrecognized IDT entry");
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return false;
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}
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return true;
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}
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if (DEBUG) this.assert(!this.addrIDT && this.addrIDTLimit == 0x03FF);
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opHelpDIVOverflow: function() {
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this.setIP(this.opEA - this.segCS.base);
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/*
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* Intel documentation for INT/INTO under "REAL ADDRESS MODE EXCEPTIONS" says:
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*
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* "[T]he 80286 will shut down if the SP = 1, 3, or 5 before executing the INT or INTO instruction--due to lack of stack space"
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*
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* TODO: Verify that 80286 real-mode actually enforces the above. See http://localhost:8088/pubs/pc/reference/intel/80286/progref/#page-260
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* TODO: Determine the proper cycle cost.
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*/
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offIDT = this.addrIDT + (nIDT << 2);
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this.descIDT.off = this.getWord(offIDT);
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this.descIDT.sel = this.getWord(offIDT + 2);
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this.descIDT.maskPS = ~(X86.PS.TF | X86.PS.IF);
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return true;
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},
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/**
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* opHelpSwitchTSS(selNew, fNest)
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*
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* Helper implementing TSS (Task State Segment) task switching.
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*
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* @this {X86CPU}
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* @param {number} selNew
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* @param {boolean} fNest is true if nesting, false if un-nesting
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* @return {boolean} true if successful, false if error
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*/
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opHelpSwitchTSS: function(selNew, fNest) {
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var addrOld = this.segTSS.base;
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var cplOld = this.segCS.cpl;
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var selOld = this.segTSS.sel;
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if (!fNest) {
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if (this.segTSS.type != X86.DESC.ACC.TYPE.TSS_BUSY) {
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X86Help.opHelpFault.call(this, X86.EXCEPTION.TS_FAULT, selNew, true);
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return false;
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}
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this.setWord(this.segTSS.addrDesc + X86.DESC.ACC.OFFSET, (this.segTSS.acc & ~X86.DESC.ACC.TYPE.TSS_BUSY) | X86.DESC.ACC.TYPE.TSS);
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}
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if (this.segTSS.load(selNew) == null) {
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return false;
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}
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var addrNew = this.segTSS.base;
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if (DEBUG) {
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this.messageDebugger((fNest? "Task switch" : "Task return") + ": TR " + str.toHexWord(selOld) + " (%" + str.toHex(addrOld, 6) + "), new TR " + str.toHexWord(selNew) + " (%" + str.toHex(addrNew, 6) + ")", Debugger.MESSAGE.TSS);
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}
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if (fNest) {
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if (this.segTSS.type == X86.DESC.ACC.TYPE.TSS_BUSY) {
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X86Help.opHelpFault.call(this, X86.EXCEPTION.GP_FAULT, selNew, true);
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return false;
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}
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this.setWord(this.segTSS.addrDesc + X86.DESC.ACC.OFFSET, this.segTSS.acc |= X86.DESC.ACC.TYPE.TSS_BUSY);
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this.segTSS.type = X86.DESC.ACC.TYPE.TSS_BUSY;
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}
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this.setWord(addrOld + X86.TSS.TASK_IP, this.regIP);
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this.setWord(addrOld + X86.TSS.TASK_PS, this.getPS());
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this.setWord(addrOld + X86.TSS.TASK_AX, this.regAX);
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this.setWord(addrOld + X86.TSS.TASK_CX, this.regCX);
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this.setWord(addrOld + X86.TSS.TASK_DX, this.regDX);
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this.setWord(addrOld + X86.TSS.TASK_BX, this.regBX);
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this.setWord(addrOld + X86.TSS.TASK_SP, this.regSP);
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this.setWord(addrOld + X86.TSS.TASK_BP, this.regBP);
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this.setWord(addrOld + X86.TSS.TASK_SI, this.regSI);
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this.setWord(addrOld + X86.TSS.TASK_DI, this.regDI);
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this.setWord(addrOld + X86.TSS.TASK_ES, this.segES.sel);
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this.setWord(addrOld + X86.TSS.TASK_CS, this.segCS.sel);
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this.setWord(addrOld + X86.TSS.TASK_SS, this.segSS.sel);
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this.setWord(addrOld + X86.TSS.TASK_DS, this.segDS.sel);
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var offSS = X86.TSS.TASK_SS;
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var offSP = X86.TSS.TASK_SP;
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this.setPS(this.getWord(addrNew + X86.TSS.TASK_PS) | (fNest? X86.PS.NT : 0));
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if (DEBUG) this.assert(!fNest || !!(this.regPS & X86.PS.NT));
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this.regAX = this.getWord(addrNew + X86.TSS.TASK_AX);
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this.regCX = this.getWord(addrNew + X86.TSS.TASK_CX);
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this.regDX = this.getWord(addrNew + X86.TSS.TASK_DX);
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this.regBX = this.getWord(addrNew + X86.TSS.TASK_BX);
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this.regBP = this.getWord(addrNew + X86.TSS.TASK_BP);
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this.regSI = this.getWord(addrNew + X86.TSS.TASK_SI);
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this.regDI = this.getWord(addrNew + X86.TSS.TASK_DI);
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this.segES.load(this.getWord(addrNew + X86.TSS.TASK_ES));
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this.segDS.load(this.getWord(addrNew + X86.TSS.TASK_DS));
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this.setCSIP(this.getWord(addrNew + X86.TSS.TASK_IP), this.getWord(addrNew + X86.TSS.TASK_CS));
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if (this.segCS.cpl < cplOld) {
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offSP = (this.segCS.cpl << 2) + X86.TSS.CPL0_SP;
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offSS = offSP + 2;
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}
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this.regSP = this.getWord(addrNew + offSP);
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this.segSS.load(this.getWord(addrNew + offSS));
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this.segLDT.load(this.getWord(addrNew + X86.TSS.TASK_LDT));
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if (fNest) this.setWord(addrNew + X86.TSS.PREV_TSS, selOld);
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this.regMSW |= X86.MSW.TS;
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return true;
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X86Help.opHelpINT.call(this, X86.EXCEPTION.DIV_ERR, null, 2);
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},
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/**
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* opHelpFault(nFault, nError, fHalt)
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@ -671,27 +528,28 @@ var X86Help = {
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* @param {number} [nError]
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* @param {boolean} [fHalt] will halt the CPU if true *and* a Debugger is loaded
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*/
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opHelpFault: function(nFault, nError, fHalt) {
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if (!this.aFlags.fComplete) {
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// this.messageDebugger("Fault " + str.toHexByte(nFault) + " blocked by Debugger", Debugger.MESSAGE.WARN);
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opHelpFault: function(nFault, nError, fHalt)
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{
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if (!this.bitField.fComplete) {
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this.messageDebugger("Fault " + str.toHexByte(nFault) + " blocked by Debugger", Debugger.MESSAGE.WARN);
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this.setIP(this.opEA - this.segCS.base);
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return;
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}
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var fFault = false;
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var fDispatch = false;
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if (this.model >= X86.MODEL_80186) {
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if (this.nFault < 0) {
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/*
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* Single-fault (error code is passed through, and the responsible instruction is restartable)
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*/
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this.setIP(this.opEA - this.segCS.base);
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fFault = true;
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fDispatch = true;
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} else if (this.nFault != X86.EXCEPTION.DF_FAULT) {
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/*
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* Double-fault (error code is always zero, and the responsible instruction is not restartable)
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*/
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nError = 0;
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nFault = X86.EXCEPTION.DF_FAULT;
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fFault = true;
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fDispatch = true;
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} else {
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/*
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* Triple-fault (usually referred to in Intel literature as a "shutdown", but at least on the 80286,
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@ -703,9 +561,24 @@ var X86Help = {
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}
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}
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if (X86Help.opHelpFaultMessage.call(this, nFault, nError, fHalt)) {
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fFault = false;
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fDispatch = false;
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}
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if (fDispatch) X86Help.opHelpINT.call(this, this.nFault = nFault, nError, 0);
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/*
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* Since this fault is likely being issued in the context of an instruction that hasn't finished
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* executing, and since we currently don't do anything to interrupt that execution (eg, throw a
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* JavaScript exception), and since we don't want that instruction to perform any writes that might
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* be destructive, we should shut off all further reads/writes for the current instruction.
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*
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* As long as we're not using EAFUNCS, this is easy for any EA-based memory accesses: simply set
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* the NOREAD and NOWRITE flags. However, there may still be direct, non-EA-based memory accesses that
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* could cause us grief. TODO: Implement the ultimate solution, which will involve setting a special
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* flag and throwing an exception that the CPU must intercept and then quietly ignore.
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*/
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if (!EAFUNCS) {
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this.opFlags &= ~(X86.OPFLAG.NOREAD | X86.OPFLAG.NOWRITE);
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}
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if (fFault) X86Help.opHelpINT.call(this, this.nFault = nFault, nError, 0);
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},
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/**
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* opHelpFaultMessage()
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@ -714,22 +587,26 @@ var X86Help = {
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* halt exception processing in tracks: return true to prevent the fault handler from being dispatched.
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*
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* TODO: Provide the Debugger with some UI to control its "interference" with fault dispatching, and to
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* continue the dispatch after it has interfered.
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* continue the dispatch after it has interfered. At the moment, your only option is to single-step over
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* the offending instruction to allow the fault to be dispatched.
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*
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* @this {X86CPU}
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* @param {number} nFault
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* @param {number} [nError]
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* @param {boolean} [fHalt] will halt the CPU if true *and* a Debugger is loaded
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* @return {boolean} true to halt the CPU, false if not
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* @return {boolean|undefined} true to block the fault, otherwise dispatch it
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*/
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opHelpFaultMessage: function(nFault, nError, fHalt) {
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/*
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* TODO: When we're done examining all GP faults, change the following to "fHalt || false"
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*/
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fHalt = fHalt || (nFault == X86.EXCEPTION.GP_FAULT);
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opHelpFaultMessage: function(nFault, nError, fHalt)
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{
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var bitsMessage = Debugger.MESSAGE.FAULT;
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var bOpcode = this.bus.getByteDirect(this.regEIP);
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var fDebugger = false;
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if (DEBUGGER && this.dbg) {
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fDebugger = true;
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if (nFault == X86.EXCEPTION.GP_FAULT) fHalt = true;
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}
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/*
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* OS/2 1.0 uses an INT3 (0xCC) opcode in conjunction with an invalid IDT to trigger a triple-fault
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* reset and return to real-mode, and these resets happen quite frequently during boot; for example,
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@ -755,14 +632,19 @@ var X86Help = {
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if (this.regEIP >= 0x0F0000 && this.regEIP <= 0x0FFFFF) {
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fHalt = false;
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}
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var sMessage = "Fault " + str.toHexByte(nFault) + (nError != null? " (" + str.toHexWord(nError) + ")" : "") + " on opcode 0x" + str.toHexByte(bOpcode) + " at " + str.toHexAddr(this.regIP, this.segCS.sel) + " (%" + str.toHex(this.regEIP, 6) + ")";
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if (DEBUGGER && this.dbg) {
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this.messageDebugger(sMessage, bitsMessage);
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if (fHalt) this.dbg.stopCPU();
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} else if (fHalt) {
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this.notice(sMessage);
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this.stopCPU();
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if (fDebugger && this.dbg.messageEnabled(bitsMessage) || !fDebugger && fHalt) {
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var sMessage = "Fault " + str.toHexByte(nFault) + (nError != null? " (" + str.toHexWord(nError) + ")" : "") + " on opcode 0x" + str.toHexByte(bOpcode) + " at " + str.toHexAddr(this.regIP, this.segCS.sel) + " (%" + str.toHex(this.regEIP, 6) + ")";
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if (fDebugger) {
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this.messageDebugger(sMessage, bitsMessage);
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if (fHalt) {
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fHalt = this.bitField.fRunning;
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this.dbg.stopCPU();
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}
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} else if (fHalt) {
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this.notice(sMessage);
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this.stopCPU();
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}
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}
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return fHalt;
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}
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