A few Debugger fixes whilst tracking down TSS issues
This commit is contained in:
Jeff Parsons
jeffpar
parent
a28fa95d25
commit
30d0d22e41
3 changed files with 235 additions and 198 deletions
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@ -1424,7 +1424,7 @@ if (DEBUGGER) {
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* should be done only as a last resort.
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* should be done only as a last resort.
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*
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*
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* @param {number|null|undefined} sel
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* @param {number|null|undefined} sel
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* @return {X86Seg} seg
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* @return {X86Seg|null} seg
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*/
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*/
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Debugger.prototype.getSegment = function(sel)
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Debugger.prototype.getSegment = function(sel)
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{
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{
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@ -1436,6 +1436,7 @@ if (DEBUGGER) {
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if (sel === this.cpu.getFS()) return this.cpu.segFS;
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if (sel === this.cpu.getFS()) return this.cpu.segFS;
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if (sel === this.cpu.getGS()) return this.cpu.segGS;
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if (sel === this.cpu.getGS()) return this.cpu.segGS;
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}
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}
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if (this.nBreakSuppress) return null;
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var seg = new X86Seg(this.cpu, X86Seg.ID.DEBUG, "DBG");
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var seg = new X86Seg(this.cpu, X86Seg.ID.DEBUG, "DBG");
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/*
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/*
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* Note the load() function's fSuppress parameter, which the Debugger should ALWAYS set to true
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* Note the load() function's fSuppress parameter, which the Debugger should ALWAYS set to true
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@ -1466,13 +1467,16 @@ if (DEBUGGER) {
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*/
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*/
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var addr = dbgAddr.addr;
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var addr = dbgAddr.addr;
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if (addr == null) {
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if (addr == null) {
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addr = X86.ADDR_INVALID;
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var seg = this.getSegment(dbgAddr.sel);
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var seg = this.getSegment(dbgAddr.sel);
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if (!fWrite) {
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if (seg) {
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addr = seg.checkRead(dbgAddr.off, cb || 1, true);
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if (!fWrite) {
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} else {
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addr = seg.checkRead(dbgAddr.off, cb || 1, true);
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addr = seg.checkWrite(dbgAddr.off, cb || 1, true);
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} else {
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addr = seg.checkWrite(dbgAddr.off, cb || 1, true);
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}
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dbgAddr.addr = addr;
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}
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}
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dbgAddr.addr = addr;
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}
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}
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return addr;
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return addr;
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};
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};
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@ -1639,8 +1643,8 @@ if (DEBUGGER) {
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Debugger.prototype.checkLimit = function(dbgAddr)
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Debugger.prototype.checkLimit = function(dbgAddr)
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{
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{
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if (dbgAddr.sel != null) {
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if (dbgAddr.sel != null) {
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var limit = this.getSegment(dbgAddr.sel).limit;
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var seg = this.getSegment(dbgAddr.sel);
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if (dbgAddr.off > limit) {
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if (!seg || dbgAddr.off > seg.limit) {
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dbgAddr.off = 0;
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dbgAddr.off = 0;
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dbgAddr.addr = null;
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dbgAddr.addr = null;
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}
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}
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@ -1816,8 +1820,8 @@ if (DEBUGGER) {
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}
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}
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var seg = this.getSegment(sel);
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var seg = this.getSegment(sel);
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this.println("dumpDesc(" + str.toHexWord(seg? seg.sel : sel) + "): %" + str.toHex(seg? seg.addrDesc : null, this.cchAddr));
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this.println("dumpDesc(" + str.toHexWord(seg.sel) + "): %" + str.toHex(seg.addrDesc, this.cchAddr));
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if (!seg) return;
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var sType;
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var sType;
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var fGate = false;
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var fGate = false;
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@ -1879,7 +1883,68 @@ if (DEBUGGER) {
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* been incorporated into the limit and base properties of the segment register; all we care about here
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* been incorporated into the limit and base properties of the segment register; all we care about here
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* are whether EXT contains any of the AVAIL (0x10), BIG (0x40) or LIMITPAGES (0x80) bits.
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* are whether EXT contains any of the AVAIL (0x10), BIG (0x40) or LIMITPAGES (0x80) bits.
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*/
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*/
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this.println(sDump + " dpl=" + str.toHexByte(seg.dpl) + " type=" + str.toHexByte(seg.type >> 8) + " (" + sType + ")" + " ext=" + str.toHexWord(seg.ext & ~(X86.DESC.EXT.LIMIT1619 | X86.DESC.EXT.BASE2431)));
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this.println(sDump + " type=" + str.toHexByte(seg.type >> 8) + " (" + sType + ")" + " ext=" + str.toHexWord(seg.ext & ~(X86.DESC.EXT.LIMIT1619 | X86.DESC.EXT.BASE2431)) + " dpl=" + str.toHexByte(seg.dpl));
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};
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/**
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* dumpHistory(sCount)
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*
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* @this {Debugger}
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* @param {string|undefined} sCount is the number of instructions to rewind to (default is 10)
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*/
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Debugger.prototype.dumpHistory = function(sCount)
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{
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var sMore = "";
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var cLines = 10;
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var iHistory = this.iOpcodeHistory;
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var aHistory = this.aOpcodeHistory;
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if (aHistory.length) {
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var n = (sCount === undefined? this.nextHistory : +sCount);
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if (isNaN(n))
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n = cLines;
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else
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sMore = "more ";
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if (n > aHistory.length) {
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this.println("note: only " + aHistory.length + " available");
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n = aHistory.length;
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}
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iHistory -= n;
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if (iHistory < 0) {
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if (aHistory[aHistory.length - 1][1] != null) {
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iHistory += aHistory.length;
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} else {
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n = iHistory + n;
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iHistory = 0;
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}
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}
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if (sCount !== undefined) {
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this.println(n + " instructions earlier:");
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}
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while (cLines && iHistory != this.iOpcodeHistory) {
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var dbgAddr = aHistory[iHistory++];
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if (dbgAddr.sel == null) break;
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/*
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* We must create a new dbgAddr from the address we obtained from aHistory, because dbgAddr
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* was a reference, not a copy, and we don't want getInstruction() modifying the original.
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*/
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dbgAddr = this.newAddr(dbgAddr.off, dbgAddr.sel, dbgAddr.addr);
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this.println(this.getInstruction(dbgAddr, "history", n--));
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/*
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* If there was an OPERAND or ADDRESS override on the previous instruction, getInstruction()
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* will have automatically disassembled the next instruction, so skip one more history entry.
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*/
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if (dbgAddr.fOverride) {
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iHistory++; n--;
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}
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if (iHistory >= aHistory.length) iHistory = 0;
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this.nextHistory = n;
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cLines--;
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}
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}
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if (cLines == 10) {
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this.println("no " + sMore + "history available");
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this.nextHistory = undefined;
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}
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};
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};
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/**
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/**
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@ -1904,7 +1969,8 @@ if (DEBUGGER) {
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seg = this.getSegment(sel);
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seg = this.getSegment(sel);
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}
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}
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this.println("dumpTSS(" + str.toHexWord(seg.sel) + "): %" + str.toHex(seg.base, this.cchAddr));
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this.println("dumpTSS(" + str.toHexWord(seg? seg.sel : sel) + "): %" + str.toHex(seg? seg.base : null, this.cchAddr));
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if (!seg) return;
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var sDump = "";
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var sDump = "";
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for (var sField in Debugger.aTSSFields) {
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for (var sField in Debugger.aTSSFields) {
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@ -2829,6 +2895,12 @@ if (DEBUGGER) {
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}
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}
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}
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}
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this.aBreakWrite = ["write"];
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this.aBreakWrite = ["write"];
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/*
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* nBreakSuppress ensures we can't get into an infinite loop where a breakpoint lookup requires
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* reading a segment descriptor via getSegment(), and that triggers more memory reads, which triggers
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* more breakpoint checks.
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*/
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this.nBreakSuppress = 0;
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};
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};
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/**
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/**
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@ -3017,39 +3089,42 @@ if (DEBUGGER) {
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* or history data (see checkInstruction), since we might not actually execute the current instruction.
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* or history data (see checkInstruction), since we might not actually execute the current instruction.
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*/
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*/
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var fBreak = false;
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var fBreak = false;
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addr = this.mapBreakpoint(addr);
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if (!this.nBreakSuppress++) {
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for (var i = 1; i < aBreak.length; i++) {
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addr = this.mapBreakpoint(addr);
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for (var i = 1; i < aBreak.length; i++) {
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var dbgAddrBreak = aBreak[i];
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var dbgAddrBreak = aBreak[i];
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/*
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/*
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* We need to zap the linear address field of the breakpoint address before
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* We need to zap the linear address field of the breakpoint address before
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* calling getAddr(), to force it to recalculate the linear address every time,
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* calling getAddr(), to force it to recalculate the linear address every time,
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* unless this is a breakpoint on a linear address (as indicated by a -1 offset).
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* unless this is a breakpoint on a linear address (as indicated by a -1 offset).
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*/
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*/
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if (dbgAddrBreak.off != -1) dbgAddrBreak.addr = null;
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if (dbgAddrBreak.off != -1) dbgAddrBreak.addr = null;
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/*
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/*
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* We used to calculate the linear address of the breakpoint at the time the
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* We used to calculate the linear address of the breakpoint at the time the
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* breakpoint was added, so that a breakpoint set in one mode (eg, in real-mode)
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* breakpoint was added, so that a breakpoint set in one mode (eg, in real-mode)
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* would still work as intended if the mode changed later (eg, to protected-mode).
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* would still work as intended if the mode changed later (eg, to protected-mode).
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*
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*
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* However, that created difficulties setting protected-mode breakpoints in segments
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* However, that created difficulties setting protected-mode breakpoints in segments
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* that might not be defined yet, or that could move in physical memory.
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* that might not be defined yet, or that could move in physical memory.
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*
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*
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* If you want to create a real-mode breakpoint that will break regardless of mode,
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* If you want to create a real-mode breakpoint that will break regardless of mode,
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* use the physical address of the real-mode memory location instead.
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* use the physical address of the real-mode memory location instead.
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*/
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*/
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if (addr == this.mapBreakpoint(this.getAddr(dbgAddrBreak))) {
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if (addr == this.mapBreakpoint(this.getAddr(dbgAddrBreak))) {
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if (dbgAddrBreak.fTempBreak) {
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if (dbgAddrBreak.fTempBreak) {
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this.findBreakpoint(aBreak, dbgAddrBreak, true);
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this.findBreakpoint(aBreak, dbgAddrBreak, true);
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} else if (!fTemp) {
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} else if (!fTemp) {
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this.println("breakpoint hit: " + this.hexAddr(dbgAddrBreak) + " (" + aBreak[0] + ")");
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this.println("breakpoint hit: " + this.hexAddr(dbgAddrBreak) + " (" + aBreak[0] + ")");
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}
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fBreak = true;
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break;
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}
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}
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fBreak = true;
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break;
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}
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}
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}
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}
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this.nBreakSuppress--;
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return fBreak;
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return fBreak;
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};
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};
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@ -4167,9 +4242,10 @@ if (DEBUGGER) {
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sDumpers += ",state,symbols";
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sDumpers += ",state,symbols";
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this.println("\ndump commands:");
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this.println("\ndump commands:");
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this.println("\tdb [a] [#] dump # bytes at address a");
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this.println("\tdb [a] [#] dump # bytes at address a");
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if (BACKTRACK) this.println("\tdi [a] dump backtrack info at address a");
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this.println("\tdw [a] [#] dump # words at address a");
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this.println("\tdw [a] [#] dump # words at address a");
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this.println("\tdd [a] [#] dump # dwords at address a");
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this.println("\tdd [a] [#] dump # dwords at address a");
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this.println("\tdh [#] dump # instructions prior");
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if (BACKTRACK) this.println("\tdi [a] dump backtrack info at address a");
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if (sDumpers.length) this.println("dump extensions:\n\t" + sDumpers);
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if (sDumpers.length) this.println("dump extensions:\n\t" + sDumpers);
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return;
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return;
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}
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}
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@ -4181,6 +4257,10 @@ if (DEBUGGER) {
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this.dumpSymbols();
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this.dumpSymbols();
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return;
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return;
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}
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}
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if (sCmd == "dh") {
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this.dumpHistory(sAddr);
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return;
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}
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if (sCmd == "ds") { // transform a "ds" command into a "d desc" command
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if (sCmd == "ds") { // transform a "ds" command into a "d desc" command
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sCmd = 'd';
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sCmd = 'd';
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sLen = sAddr;
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sLen = sAddr;
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@ -4326,57 +4406,7 @@ if (DEBUGGER) {
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this.stopCPU();
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this.stopCPU();
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return;
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return;
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}
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}
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var sMore = "";
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this.dumpHistory(sCount);
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var cLines = 10;
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var iHistory = this.iOpcodeHistory;
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var aHistory = this.aOpcodeHistory;
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if (aHistory.length) {
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var n = (sCount === undefined? this.nextHistory : +sCount);
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if (isNaN(n))
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n = cLines;
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else
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sMore = "more ";
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if (n > aHistory.length) {
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this.println("note: only " + aHistory.length + " available");
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n = aHistory.length;
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}
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iHistory -= n;
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if (iHistory < 0) {
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if (aHistory[aHistory.length - 1][1] != null) {
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iHistory += aHistory.length;
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} else {
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n = iHistory + n;
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iHistory = 0;
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}
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}
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if (sCount !== undefined) {
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this.println(n + " instructions earlier:");
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}
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while (cLines && iHistory != this.iOpcodeHistory) {
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var dbgAddr = aHistory[iHistory++];
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if (dbgAddr.sel == null) break;
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/*
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* We must create a new dbgAddr from the address we obtained from aHistory, because dbgAddr
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* was a reference, not a copy, and we don't want getInstruction() modifying the original.
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*/
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dbgAddr = this.newAddr(dbgAddr.off, dbgAddr.sel, dbgAddr.addr);
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this.println(this.getInstruction(dbgAddr, "history", n--));
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/*
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* If there was an OPERAND or ADDRESS override on the previous instruction, getInstruction()
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* will have automatically disassembled the next instruction, so skip one more history entry.
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*/
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if (dbgAddr.fOverride) {
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iHistory++; n--;
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}
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if (iHistory >= aHistory.length) iHistory = 0;
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this.nextHistory = n;
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cLines--;
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}
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}
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if (cLines == 10) {
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this.println("no " + sMore + "history available");
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this.nextHistory = undefined;
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}
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};
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};
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/**
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/**
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@ -3802,11 +3802,10 @@ X86.opHLT = function HLT()
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this.intFlags |= X86.INTFLAG.HALT;
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this.intFlags |= X86.INTFLAG.HALT;
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this.nStepCycles -= 2;
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this.nStepCycles -= 2;
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/*
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/*
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* If a Debugger is present AND Debugger checks are enabled (eg, one or more breakpoints are set,
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* If a Debugger is present and the HALT message category is enabled, then we REALLY halt the CPU,
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* or the global DEBUG flag is set, etc), then we REALLY halt the CPU, on the theory that whoever's
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* on the theory that whoever's using the Debugger would like to see HLTs.
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* using the Debugger would like to see HLTs.
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*/
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*/
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if (DEBUGGER && this.dbg && this.dbg.checksEnabled(true)) {
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if (DEBUGGER && this.dbg && this.messageEnabled(Messages.HALT)) {
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this.advanceIP(-1); // this is purely for the Debugger's benefit, to show the HLT
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this.advanceIP(-1); // this is purely for the Debugger's benefit, to show the HLT
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this.stopCPU();
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this.stopCPU();
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return;
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return;
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@ -44,7 +44,7 @@ if (typeof module !== 'undefined') {
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* @property {number} sel
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* @property {number} sel
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* @property {number} limit (in protected-mode, this comes from descriptor word 0x0)
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* @property {number} limit (in protected-mode, this comes from descriptor word 0x0)
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* @property {number} base (in protected-mode, this comes from descriptor word 0x2)
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* @property {number} base (in protected-mode, this comes from descriptor word 0x2)
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* @property {number} acc (in protected-mode, this comes from descriptor word 0x4, masked with 0xff00; bits 0-7 supplement base bits 16-23)
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* @property {number} acc (in protected-mode, this comes from descriptor word 0x4; bits 0-7 supplement base bits 16-23)
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* @property {number} ext (in protected-mode, this is descriptor word 0x6, 80386 only; supplements limit bits 16-19 and base bits 24-31)
|
* @property {number} ext (in protected-mode, this is descriptor word 0x6, 80386 only; supplements limit bits 16-19 and base bits 24-31)
|
||||||
*
|
*
|
||||||
* TODO: Determine what good, if any, these class annotations are for either an IDE like WebStorm or a tool like
|
* TODO: Determine what good, if any, these class annotations are for either an IDE like WebStorm or a tool like
|
||||||
|
|
@ -409,102 +409,6 @@ X86Seg.prototype.checkWriteProtDisallowed = function checkWriteProtDisallowed(of
|
||||||
return X86.ADDR_INVALID;
|
return X86.ADDR_INVALID;
|
||||||
};
|
};
|
||||||
|
|
||||||
/**
|
|
||||||
* switchTSS(selNew, fNest)
|
|
||||||
*
|
|
||||||
* Implements TSS (Task State Segment) task switching.
|
|
||||||
*
|
|
||||||
* NOTES: This typically occurs during double-fault processing, because the IDT entry for DF_FAULT normally
|
|
||||||
* contains a task gate. Interestingly, if we force a GP_FAULT to occur at a sufficiently early point in the
|
|
||||||
* OS/2 1.0 initialization code, OS/2 does a nice job of displaying the GP fault and then shutting down:
|
|
||||||
*
|
|
||||||
* 0090:067B FB STI
|
|
||||||
* 0090:067C EBFD JMP 067B
|
|
||||||
*
|
|
||||||
* but it may not have yet reprogrammed the master PIC to re-vector hardware interrupts to IDT entries 0x50-0x57,
|
|
||||||
* so when the next timer interrupt (IRQ 0) occurs, it vectors through IDT entry 0x08, which is the DF_FAULT
|
|
||||||
* vector. A spurious double-fault is generated, and a clean shutdown turns into a messy crash.
|
|
||||||
*
|
|
||||||
* Of course, that all could have been avoided if IBM had heeded Intel's advice and not used Intel-reserved IDT
|
|
||||||
* entries for PC interrupts.
|
|
||||||
*
|
|
||||||
* TODO: Add 80386 TSS support (including CR3 support).
|
|
||||||
*
|
|
||||||
* @this {X86Seg}
|
|
||||||
* @param {number} selNew
|
|
||||||
* @param {boolean} fNest is true if nesting, false if un-nesting
|
|
||||||
* @return {boolean} true if successful, false if error
|
|
||||||
*/
|
|
||||||
X86Seg.prototype.switchTSS = function switchTSS(selNew, fNest)
|
|
||||||
{
|
|
||||||
var cpu = this.cpu;
|
|
||||||
cpu.assert(this === cpu.segCS);
|
|
||||||
|
|
||||||
var addrOld = cpu.segTSS.base;
|
|
||||||
var cplOld = this.cpl;
|
|
||||||
var selOld = cpu.segTSS.sel;
|
|
||||||
if (!fNest) {
|
|
||||||
if (cpu.segTSS.type != X86.DESC.ACC.TYPE.TSS_BUSY) {
|
|
||||||
X86.fnFault.call(cpu, X86.EXCEPTION.TS_FAULT, selNew, true);
|
|
||||||
return false;
|
|
||||||
}
|
|
||||||
cpu.setShort(cpu.segTSS.addrDesc + X86.DESC.ACC.OFFSET, (cpu.segTSS.acc & ~X86.DESC.ACC.TYPE.TSS_BUSY) | X86.DESC.ACC.TYPE.TSS);
|
|
||||||
}
|
|
||||||
if (cpu.segTSS.load(selNew) === X86.ADDR_INVALID) {
|
|
||||||
return false;
|
|
||||||
}
|
|
||||||
var addrNew = cpu.segTSS.base;
|
|
||||||
if (DEBUG && DEBUGGER && this.dbg && this.dbg.messageEnabled(Messages.TSS)) {
|
|
||||||
this.dbg.message((fNest? "Task switch" : "Task return") + ": TR " + str.toHexWord(selOld) + " (%" + str.toHex(addrOld, 6) + "), new TR " + str.toHexWord(selNew) + " (%" + str.toHex(addrNew, 6) + ")");
|
|
||||||
}
|
|
||||||
if (fNest) {
|
|
||||||
if (cpu.segTSS.type == X86.DESC.ACC.TYPE.TSS_BUSY) {
|
|
||||||
X86.fnFault.call(cpu, X86.EXCEPTION.GP_FAULT, selNew, true);
|
|
||||||
return false;
|
|
||||||
}
|
|
||||||
cpu.setShort(cpu.segTSS.addrDesc + X86.DESC.ACC.OFFSET, cpu.segTSS.acc |= X86.DESC.ACC.TYPE.TSS_BUSY);
|
|
||||||
cpu.segTSS.type = X86.DESC.ACC.TYPE.TSS_BUSY;
|
|
||||||
}
|
|
||||||
cpu.setShort(addrOld + X86.TSS.TASK_IP, cpu.getIP());
|
|
||||||
cpu.setShort(addrOld + X86.TSS.TASK_PS, cpu.getPS());
|
|
||||||
cpu.setShort(addrOld + X86.TSS.TASK_AX, cpu.regEAX);
|
|
||||||
cpu.setShort(addrOld + X86.TSS.TASK_CX, cpu.regECX);
|
|
||||||
cpu.setShort(addrOld + X86.TSS.TASK_DX, cpu.regEDX);
|
|
||||||
cpu.setShort(addrOld + X86.TSS.TASK_BX, cpu.regEBX);
|
|
||||||
cpu.setShort(addrOld + X86.TSS.TASK_SP, cpu.getSP());
|
|
||||||
cpu.setShort(addrOld + X86.TSS.TASK_BP, cpu.regEBP);
|
|
||||||
cpu.setShort(addrOld + X86.TSS.TASK_SI, cpu.regESI);
|
|
||||||
cpu.setShort(addrOld + X86.TSS.TASK_DI, cpu.regEDI);
|
|
||||||
cpu.setShort(addrOld + X86.TSS.TASK_ES, cpu.segES.sel);
|
|
||||||
cpu.setShort(addrOld + X86.TSS.TASK_CS, cpu.segCS.sel);
|
|
||||||
cpu.setShort(addrOld + X86.TSS.TASK_SS, cpu.segSS.sel);
|
|
||||||
cpu.setShort(addrOld + X86.TSS.TASK_DS, cpu.segDS.sel);
|
|
||||||
var offSS = X86.TSS.TASK_SS;
|
|
||||||
var offSP = X86.TSS.TASK_SP;
|
|
||||||
cpu.setPS(cpu.getShort(addrNew + X86.TSS.TASK_PS) | (fNest? X86.PS.NT : 0));
|
|
||||||
cpu.assert(!fNest || !!(cpu.regPS & X86.PS.NT));
|
|
||||||
cpu.regEAX = cpu.getShort(addrNew + X86.TSS.TASK_AX);
|
|
||||||
cpu.regECX = cpu.getShort(addrNew + X86.TSS.TASK_CX);
|
|
||||||
cpu.regEDX = cpu.getShort(addrNew + X86.TSS.TASK_DX);
|
|
||||||
cpu.regEBX = cpu.getShort(addrNew + X86.TSS.TASK_BX);
|
|
||||||
cpu.regEBP = cpu.getShort(addrNew + X86.TSS.TASK_BP);
|
|
||||||
cpu.regESI = cpu.getShort(addrNew + X86.TSS.TASK_SI);
|
|
||||||
cpu.regEDI = cpu.getShort(addrNew + X86.TSS.TASK_DI);
|
|
||||||
cpu.segES.load(cpu.getShort(addrNew + X86.TSS.TASK_ES));
|
|
||||||
cpu.segDS.load(cpu.getShort(addrNew + X86.TSS.TASK_DS));
|
|
||||||
cpu.setCSIP(cpu.getShort(addrNew + X86.TSS.TASK_IP), cpu.getShort(addrNew + X86.TSS.TASK_CS));
|
|
||||||
if (this.cpl < cplOld) {
|
|
||||||
offSP = (this.cpl << 2) + X86.TSS.CPL0_SP;
|
|
||||||
offSS = offSP + 2;
|
|
||||||
}
|
|
||||||
cpu.setSS(cpu.getShort(addrNew + offSS), true);
|
|
||||||
cpu.setSP(cpu.getShort(addrNew + offSP));
|
|
||||||
cpu.segLDT.load(cpu.getShort(addrNew + X86.TSS.TASK_LDT));
|
|
||||||
if (fNest) cpu.setShort(addrNew + X86.TSS.PREV_TSS, selOld);
|
|
||||||
cpu.regCR0 |= X86.CR0.MSW.TS;
|
|
||||||
return true;
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* loadAcc(sel, fGDT)
|
* loadAcc(sel, fGDT)
|
||||||
*
|
*
|
||||||
|
|
@ -567,7 +471,7 @@ X86Seg.prototype.loadDesc6 = function(addrDesc, sel)
|
||||||
this.addrDesc = addrDesc;
|
this.addrDesc = addrDesc;
|
||||||
this.updateMode(true);
|
this.updateMode(true);
|
||||||
|
|
||||||
this.messageSeg(sel, base, limit, acc);
|
this.messageSeg(sel, base, limit, this.type);
|
||||||
|
|
||||||
return base;
|
return base;
|
||||||
};
|
};
|
||||||
|
|
@ -650,6 +554,14 @@ X86Seg.prototype.loadDesc8 = function(addrDesc, sel, fSuppress)
|
||||||
}
|
}
|
||||||
fGate = false;
|
fGate = false;
|
||||||
}
|
}
|
||||||
|
else if (type == X86.DESC.ACC.TYPE.TSS) {
|
||||||
|
if (!this.switchTSS(sel, true)) {
|
||||||
|
base = addrDesc = X86.ADDR_INVALID;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
if (DEBUG) cpu.stopCPU();
|
||||||
|
return this.base;
|
||||||
|
}
|
||||||
else if (type == X86.DESC.ACC.TYPE.GATE_CALL) {
|
else if (type == X86.DESC.ACC.TYPE.GATE_CALL) {
|
||||||
fGate = true;
|
fGate = true;
|
||||||
regPSMask = ~0;
|
regPSMask = ~0;
|
||||||
|
|
@ -807,10 +719,106 @@ X86Seg.prototype.loadDesc8 = function(addrDesc, sel, fSuppress)
|
||||||
this.updateMode(true);
|
this.updateMode(true);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
if (!fSuppress) this.messageSeg(sel, base, limit, acc, ext);
|
if (!fSuppress) this.messageSeg(sel, base, limit, type, ext);
|
||||||
return base;
|
return base;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* switchTSS(selNew, fNest)
|
||||||
|
*
|
||||||
|
* Implements TSS (Task State Segment) task switching.
|
||||||
|
*
|
||||||
|
* NOTES: This typically occurs during double-fault processing, because the IDT entry for DF_FAULT normally
|
||||||
|
* contains a task gate. Interestingly, if we force a GP_FAULT to occur at a sufficiently early point in the
|
||||||
|
* OS/2 1.0 initialization code, OS/2 does a nice job of displaying the GP fault and then shutting down:
|
||||||
|
*
|
||||||
|
* 0090:067B FB STI
|
||||||
|
* 0090:067C EBFD JMP 067B
|
||||||
|
*
|
||||||
|
* but it may not have yet reprogrammed the master PIC to re-vector hardware interrupts to IDT entries 0x50-0x57,
|
||||||
|
* so when the next timer interrupt (IRQ 0) occurs, it vectors through IDT entry 0x08, which is the DF_FAULT
|
||||||
|
* vector. A spurious double-fault is generated, and a clean shutdown turns into a messy crash.
|
||||||
|
*
|
||||||
|
* Of course, that all could have been avoided if IBM had heeded Intel's advice and not used Intel-reserved IDT
|
||||||
|
* entries for PC interrupts.
|
||||||
|
*
|
||||||
|
* TODO: Add 80386 TSS support (including CR3 support).
|
||||||
|
*
|
||||||
|
* @this {X86Seg}
|
||||||
|
* @param {number} selNew
|
||||||
|
* @param {boolean} fNest is true if nesting, false if un-nesting
|
||||||
|
* @return {boolean} true if successful, false if error
|
||||||
|
*/
|
||||||
|
X86Seg.prototype.switchTSS = function switchTSS(selNew, fNest)
|
||||||
|
{
|
||||||
|
var cpu = this.cpu;
|
||||||
|
cpu.assert(this === cpu.segCS);
|
||||||
|
|
||||||
|
var addrOld = cpu.segTSS.base;
|
||||||
|
var cplOld = this.cpl;
|
||||||
|
var selOld = cpu.segTSS.sel;
|
||||||
|
if (!fNest) {
|
||||||
|
if (cpu.segTSS.type != X86.DESC.ACC.TYPE.TSS_BUSY) {
|
||||||
|
X86.fnFault.call(cpu, X86.EXCEPTION.TS_FAULT, selNew, true);
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
cpu.setShort(cpu.segTSS.addrDesc + X86.DESC.ACC.OFFSET, (cpu.segTSS.acc & ~X86.DESC.ACC.TYPE.TSS_BUSY) | X86.DESC.ACC.TYPE.TSS);
|
||||||
|
}
|
||||||
|
if (cpu.segTSS.load(selNew) === X86.ADDR_INVALID) {
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
var addrNew = cpu.segTSS.base;
|
||||||
|
if (DEBUG && DEBUGGER && this.dbg && this.dbg.messageEnabled(Messages.TSS)) {
|
||||||
|
this.dbg.message((fNest? "Task switch" : "Task return") + ": TR " + str.toHexWord(selOld) + " (%" + str.toHex(addrOld, 6) + "), new TR " + str.toHexWord(selNew) + " (%" + str.toHex(addrNew, 6) + ")");
|
||||||
|
}
|
||||||
|
if (fNest) {
|
||||||
|
if (cpu.segTSS.type == X86.DESC.ACC.TYPE.TSS_BUSY) {
|
||||||
|
X86.fnFault.call(cpu, X86.EXCEPTION.GP_FAULT, selNew, true);
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
cpu.setShort(cpu.segTSS.addrDesc + X86.DESC.ACC.OFFSET, cpu.segTSS.acc |= X86.DESC.ACC.TYPE.TSS_BUSY);
|
||||||
|
cpu.segTSS.type = X86.DESC.ACC.TYPE.TSS_BUSY;
|
||||||
|
}
|
||||||
|
cpu.setShort(addrOld + X86.TSS.TASK_IP, cpu.getIP());
|
||||||
|
cpu.setShort(addrOld + X86.TSS.TASK_PS, cpu.getPS());
|
||||||
|
cpu.setShort(addrOld + X86.TSS.TASK_AX, cpu.regEAX);
|
||||||
|
cpu.setShort(addrOld + X86.TSS.TASK_CX, cpu.regECX);
|
||||||
|
cpu.setShort(addrOld + X86.TSS.TASK_DX, cpu.regEDX);
|
||||||
|
cpu.setShort(addrOld + X86.TSS.TASK_BX, cpu.regEBX);
|
||||||
|
cpu.setShort(addrOld + X86.TSS.TASK_SP, cpu.getSP());
|
||||||
|
cpu.setShort(addrOld + X86.TSS.TASK_BP, cpu.regEBP);
|
||||||
|
cpu.setShort(addrOld + X86.TSS.TASK_SI, cpu.regESI);
|
||||||
|
cpu.setShort(addrOld + X86.TSS.TASK_DI, cpu.regEDI);
|
||||||
|
cpu.setShort(addrOld + X86.TSS.TASK_ES, cpu.segES.sel);
|
||||||
|
cpu.setShort(addrOld + X86.TSS.TASK_CS, cpu.segCS.sel);
|
||||||
|
cpu.setShort(addrOld + X86.TSS.TASK_SS, cpu.segSS.sel);
|
||||||
|
cpu.setShort(addrOld + X86.TSS.TASK_DS, cpu.segDS.sel);
|
||||||
|
var offSS = X86.TSS.TASK_SS;
|
||||||
|
var offSP = X86.TSS.TASK_SP;
|
||||||
|
cpu.setPS(cpu.getShort(addrNew + X86.TSS.TASK_PS) | (fNest? X86.PS.NT : 0));
|
||||||
|
cpu.assert(!fNest || !!(cpu.regPS & X86.PS.NT));
|
||||||
|
cpu.regEAX = cpu.getShort(addrNew + X86.TSS.TASK_AX);
|
||||||
|
cpu.regECX = cpu.getShort(addrNew + X86.TSS.TASK_CX);
|
||||||
|
cpu.regEDX = cpu.getShort(addrNew + X86.TSS.TASK_DX);
|
||||||
|
cpu.regEBX = cpu.getShort(addrNew + X86.TSS.TASK_BX);
|
||||||
|
cpu.regEBP = cpu.getShort(addrNew + X86.TSS.TASK_BP);
|
||||||
|
cpu.regESI = cpu.getShort(addrNew + X86.TSS.TASK_SI);
|
||||||
|
cpu.regEDI = cpu.getShort(addrNew + X86.TSS.TASK_DI);
|
||||||
|
cpu.segES.load(cpu.getShort(addrNew + X86.TSS.TASK_ES));
|
||||||
|
cpu.segDS.load(cpu.getShort(addrNew + X86.TSS.TASK_DS));
|
||||||
|
cpu.setCSIP(cpu.getShort(addrNew + X86.TSS.TASK_IP), cpu.getShort(addrNew + X86.TSS.TASK_CS));
|
||||||
|
if (this.cpl < cplOld) {
|
||||||
|
offSP = (this.cpl << 2) + X86.TSS.CPL0_SP;
|
||||||
|
offSS = offSP + 2;
|
||||||
|
}
|
||||||
|
cpu.setSS(cpu.getShort(addrNew + offSS), true);
|
||||||
|
cpu.setSP(cpu.getShort(addrNew + offSP));
|
||||||
|
cpu.segLDT.load(cpu.getShort(addrNew + X86.TSS.TASK_LDT));
|
||||||
|
if (fNest) cpu.setShort(addrNew + X86.TSS.PREV_TSS, selOld);
|
||||||
|
cpu.regCR0 |= X86.CR0.MSW.TS;
|
||||||
|
return true;
|
||||||
|
};
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* setBase(addr)
|
* setBase(addr)
|
||||||
*
|
*
|
||||||
|
|
@ -1008,23 +1016,23 @@ X86Seg.prototype.updateMode = function(fLoad, fProt)
|
||||||
};
|
};
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* messageSeg(sel, base, limit, acc, ext)
|
* messageSeg(sel, base, limit, type, ext)
|
||||||
*
|
*
|
||||||
* @this {X86Seg}
|
* @this {X86Seg}
|
||||||
* @param {number} sel
|
* @param {number} sel
|
||||||
* @param {number} base
|
* @param {number} base
|
||||||
* @param {number} limit
|
* @param {number} limit
|
||||||
* @param {number} acc
|
* @param {number} type
|
||||||
* @param {number} [ext]
|
* @param {number} [ext]
|
||||||
*/
|
*/
|
||||||
X86Seg.prototype.messageSeg = function(sel, base, limit, acc, ext)
|
X86Seg.prototype.messageSeg = function(sel, base, limit, type, ext)
|
||||||
{
|
{
|
||||||
if (DEBUG) {
|
if (DEBUG) {
|
||||||
if (DEBUGGER && this.dbg && this.dbg.messageEnabled(Messages.SEG)) {
|
if (DEBUGGER && this.dbg && this.dbg.messageEnabled(Messages.SEG)) {
|
||||||
var ch = (this.sName.length < 3? " " : "");
|
var ch = (this.sName.length < 3? " " : "");
|
||||||
var sDPL = " dpl=" + this.dpl;
|
var sDPL = " dpl=" + this.dpl;
|
||||||
if (this.id == X86Seg.ID.CODE) sDPL += " cpl=" + this.cpl;
|
if (this.id == X86Seg.ID.CODE) sDPL += " cpl=" + this.cpl;
|
||||||
this.dbg.message("loadSeg(" + this.sName + "):" + ch + "sel=" + str.toHexWord(sel) + " base=" + str.toHex(base) + " limit=" + str.toHexWord(limit) + " acc=" + str.toHexWord(acc) + sDPL);
|
this.dbg.message("loadSeg(" + this.sName + "):" + ch + "sel=" + str.toHexWord(sel) + " base=" + str.toHex(base) + " limit=" + str.toHexWord(limit) + " type=" + str.toHexWord(type) + sDPL, true);
|
||||||
}
|
}
|
||||||
this.cpu.assert(/* base !== X86.ADDR_INVALID && */ (this.cpu.model >= X86.MODEL_80386 || !ext || ext == X86.DESC.EXT.AVAIL));
|
this.cpu.assert(/* base !== X86.ADDR_INVALID && */ (this.cpu.model >= X86.MODEL_80386 || !ext || ext == X86.DESC.EXT.AVAIL));
|
||||||
}
|
}
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue