A few Debugger fixes whilst tracking down TSS issues
This commit is contained in:
Jeff Parsons
jeffpar
parent
a28fa95d25
commit
30d0d22e41
3 changed files with 235 additions and 198 deletions
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@ -44,7 +44,7 @@ if (typeof module !== 'undefined') {
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* @property {number} sel
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* @property {number} limit (in protected-mode, this comes from descriptor word 0x0)
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* @property {number} base (in protected-mode, this comes from descriptor word 0x2)
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* @property {number} acc (in protected-mode, this comes from descriptor word 0x4, masked with 0xff00; bits 0-7 supplement base bits 16-23)
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* @property {number} acc (in protected-mode, this comes from descriptor word 0x4; bits 0-7 supplement base bits 16-23)
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* @property {number} ext (in protected-mode, this is descriptor word 0x6, 80386 only; supplements limit bits 16-19 and base bits 24-31)
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*
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* TODO: Determine what good, if any, these class annotations are for either an IDE like WebStorm or a tool like
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@ -409,102 +409,6 @@ X86Seg.prototype.checkWriteProtDisallowed = function checkWriteProtDisallowed(of
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return X86.ADDR_INVALID;
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};
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/**
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* switchTSS(selNew, fNest)
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*
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* Implements TSS (Task State Segment) task switching.
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*
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* NOTES: This typically occurs during double-fault processing, because the IDT entry for DF_FAULT normally
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* contains a task gate. Interestingly, if we force a GP_FAULT to occur at a sufficiently early point in the
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* OS/2 1.0 initialization code, OS/2 does a nice job of displaying the GP fault and then shutting down:
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*
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* 0090:067B FB STI
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* 0090:067C EBFD JMP 067B
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*
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* but it may not have yet reprogrammed the master PIC to re-vector hardware interrupts to IDT entries 0x50-0x57,
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* so when the next timer interrupt (IRQ 0) occurs, it vectors through IDT entry 0x08, which is the DF_FAULT
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* vector. A spurious double-fault is generated, and a clean shutdown turns into a messy crash.
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*
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* Of course, that all could have been avoided if IBM had heeded Intel's advice and not used Intel-reserved IDT
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* entries for PC interrupts.
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*
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* TODO: Add 80386 TSS support (including CR3 support).
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*
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* @this {X86Seg}
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* @param {number} selNew
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* @param {boolean} fNest is true if nesting, false if un-nesting
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* @return {boolean} true if successful, false if error
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*/
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X86Seg.prototype.switchTSS = function switchTSS(selNew, fNest)
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{
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var cpu = this.cpu;
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cpu.assert(this === cpu.segCS);
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var addrOld = cpu.segTSS.base;
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var cplOld = this.cpl;
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var selOld = cpu.segTSS.sel;
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if (!fNest) {
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if (cpu.segTSS.type != X86.DESC.ACC.TYPE.TSS_BUSY) {
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X86.fnFault.call(cpu, X86.EXCEPTION.TS_FAULT, selNew, true);
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return false;
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}
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cpu.setShort(cpu.segTSS.addrDesc + X86.DESC.ACC.OFFSET, (cpu.segTSS.acc & ~X86.DESC.ACC.TYPE.TSS_BUSY) | X86.DESC.ACC.TYPE.TSS);
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}
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if (cpu.segTSS.load(selNew) === X86.ADDR_INVALID) {
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return false;
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}
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var addrNew = cpu.segTSS.base;
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if (DEBUG && DEBUGGER && this.dbg && this.dbg.messageEnabled(Messages.TSS)) {
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this.dbg.message((fNest? "Task switch" : "Task return") + ": TR " + str.toHexWord(selOld) + " (%" + str.toHex(addrOld, 6) + "), new TR " + str.toHexWord(selNew) + " (%" + str.toHex(addrNew, 6) + ")");
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}
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if (fNest) {
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if (cpu.segTSS.type == X86.DESC.ACC.TYPE.TSS_BUSY) {
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X86.fnFault.call(cpu, X86.EXCEPTION.GP_FAULT, selNew, true);
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return false;
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}
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cpu.setShort(cpu.segTSS.addrDesc + X86.DESC.ACC.OFFSET, cpu.segTSS.acc |= X86.DESC.ACC.TYPE.TSS_BUSY);
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cpu.segTSS.type = X86.DESC.ACC.TYPE.TSS_BUSY;
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}
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cpu.setShort(addrOld + X86.TSS.TASK_IP, cpu.getIP());
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cpu.setShort(addrOld + X86.TSS.TASK_PS, cpu.getPS());
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cpu.setShort(addrOld + X86.TSS.TASK_AX, cpu.regEAX);
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cpu.setShort(addrOld + X86.TSS.TASK_CX, cpu.regECX);
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cpu.setShort(addrOld + X86.TSS.TASK_DX, cpu.regEDX);
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cpu.setShort(addrOld + X86.TSS.TASK_BX, cpu.regEBX);
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cpu.setShort(addrOld + X86.TSS.TASK_SP, cpu.getSP());
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cpu.setShort(addrOld + X86.TSS.TASK_BP, cpu.regEBP);
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cpu.setShort(addrOld + X86.TSS.TASK_SI, cpu.regESI);
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cpu.setShort(addrOld + X86.TSS.TASK_DI, cpu.regEDI);
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cpu.setShort(addrOld + X86.TSS.TASK_ES, cpu.segES.sel);
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cpu.setShort(addrOld + X86.TSS.TASK_CS, cpu.segCS.sel);
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cpu.setShort(addrOld + X86.TSS.TASK_SS, cpu.segSS.sel);
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cpu.setShort(addrOld + X86.TSS.TASK_DS, cpu.segDS.sel);
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var offSS = X86.TSS.TASK_SS;
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var offSP = X86.TSS.TASK_SP;
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cpu.setPS(cpu.getShort(addrNew + X86.TSS.TASK_PS) | (fNest? X86.PS.NT : 0));
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cpu.assert(!fNest || !!(cpu.regPS & X86.PS.NT));
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cpu.regEAX = cpu.getShort(addrNew + X86.TSS.TASK_AX);
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cpu.regECX = cpu.getShort(addrNew + X86.TSS.TASK_CX);
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cpu.regEDX = cpu.getShort(addrNew + X86.TSS.TASK_DX);
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cpu.regEBX = cpu.getShort(addrNew + X86.TSS.TASK_BX);
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cpu.regEBP = cpu.getShort(addrNew + X86.TSS.TASK_BP);
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cpu.regESI = cpu.getShort(addrNew + X86.TSS.TASK_SI);
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cpu.regEDI = cpu.getShort(addrNew + X86.TSS.TASK_DI);
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cpu.segES.load(cpu.getShort(addrNew + X86.TSS.TASK_ES));
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cpu.segDS.load(cpu.getShort(addrNew + X86.TSS.TASK_DS));
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cpu.setCSIP(cpu.getShort(addrNew + X86.TSS.TASK_IP), cpu.getShort(addrNew + X86.TSS.TASK_CS));
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if (this.cpl < cplOld) {
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offSP = (this.cpl << 2) + X86.TSS.CPL0_SP;
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offSS = offSP + 2;
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}
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cpu.setSS(cpu.getShort(addrNew + offSS), true);
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cpu.setSP(cpu.getShort(addrNew + offSP));
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cpu.segLDT.load(cpu.getShort(addrNew + X86.TSS.TASK_LDT));
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if (fNest) cpu.setShort(addrNew + X86.TSS.PREV_TSS, selOld);
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cpu.regCR0 |= X86.CR0.MSW.TS;
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return true;
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};
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/**
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* loadAcc(sel, fGDT)
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*
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@ -567,7 +471,7 @@ X86Seg.prototype.loadDesc6 = function(addrDesc, sel)
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this.addrDesc = addrDesc;
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this.updateMode(true);
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this.messageSeg(sel, base, limit, acc);
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this.messageSeg(sel, base, limit, this.type);
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return base;
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};
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@ -650,6 +554,14 @@ X86Seg.prototype.loadDesc8 = function(addrDesc, sel, fSuppress)
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}
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fGate = false;
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}
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else if (type == X86.DESC.ACC.TYPE.TSS) {
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if (!this.switchTSS(sel, true)) {
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base = addrDesc = X86.ADDR_INVALID;
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break;
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}
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if (DEBUG) cpu.stopCPU();
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return this.base;
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}
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else if (type == X86.DESC.ACC.TYPE.GATE_CALL) {
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fGate = true;
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regPSMask = ~0;
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@ -807,10 +719,106 @@ X86Seg.prototype.loadDesc8 = function(addrDesc, sel, fSuppress)
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this.updateMode(true);
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break;
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}
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if (!fSuppress) this.messageSeg(sel, base, limit, acc, ext);
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if (!fSuppress) this.messageSeg(sel, base, limit, type, ext);
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return base;
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};
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/**
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* switchTSS(selNew, fNest)
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*
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* Implements TSS (Task State Segment) task switching.
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*
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* NOTES: This typically occurs during double-fault processing, because the IDT entry for DF_FAULT normally
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* contains a task gate. Interestingly, if we force a GP_FAULT to occur at a sufficiently early point in the
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* OS/2 1.0 initialization code, OS/2 does a nice job of displaying the GP fault and then shutting down:
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*
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* 0090:067B FB STI
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* 0090:067C EBFD JMP 067B
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*
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* but it may not have yet reprogrammed the master PIC to re-vector hardware interrupts to IDT entries 0x50-0x57,
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* so when the next timer interrupt (IRQ 0) occurs, it vectors through IDT entry 0x08, which is the DF_FAULT
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* vector. A spurious double-fault is generated, and a clean shutdown turns into a messy crash.
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*
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* Of course, that all could have been avoided if IBM had heeded Intel's advice and not used Intel-reserved IDT
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* entries for PC interrupts.
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*
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* TODO: Add 80386 TSS support (including CR3 support).
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*
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* @this {X86Seg}
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* @param {number} selNew
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* @param {boolean} fNest is true if nesting, false if un-nesting
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* @return {boolean} true if successful, false if error
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*/
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X86Seg.prototype.switchTSS = function switchTSS(selNew, fNest)
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{
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var cpu = this.cpu;
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cpu.assert(this === cpu.segCS);
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var addrOld = cpu.segTSS.base;
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var cplOld = this.cpl;
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var selOld = cpu.segTSS.sel;
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if (!fNest) {
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if (cpu.segTSS.type != X86.DESC.ACC.TYPE.TSS_BUSY) {
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X86.fnFault.call(cpu, X86.EXCEPTION.TS_FAULT, selNew, true);
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return false;
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}
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cpu.setShort(cpu.segTSS.addrDesc + X86.DESC.ACC.OFFSET, (cpu.segTSS.acc & ~X86.DESC.ACC.TYPE.TSS_BUSY) | X86.DESC.ACC.TYPE.TSS);
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}
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if (cpu.segTSS.load(selNew) === X86.ADDR_INVALID) {
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return false;
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}
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var addrNew = cpu.segTSS.base;
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if (DEBUG && DEBUGGER && this.dbg && this.dbg.messageEnabled(Messages.TSS)) {
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this.dbg.message((fNest? "Task switch" : "Task return") + ": TR " + str.toHexWord(selOld) + " (%" + str.toHex(addrOld, 6) + "), new TR " + str.toHexWord(selNew) + " (%" + str.toHex(addrNew, 6) + ")");
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}
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if (fNest) {
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if (cpu.segTSS.type == X86.DESC.ACC.TYPE.TSS_BUSY) {
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X86.fnFault.call(cpu, X86.EXCEPTION.GP_FAULT, selNew, true);
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return false;
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}
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cpu.setShort(cpu.segTSS.addrDesc + X86.DESC.ACC.OFFSET, cpu.segTSS.acc |= X86.DESC.ACC.TYPE.TSS_BUSY);
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cpu.segTSS.type = X86.DESC.ACC.TYPE.TSS_BUSY;
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}
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cpu.setShort(addrOld + X86.TSS.TASK_IP, cpu.getIP());
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cpu.setShort(addrOld + X86.TSS.TASK_PS, cpu.getPS());
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cpu.setShort(addrOld + X86.TSS.TASK_AX, cpu.regEAX);
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cpu.setShort(addrOld + X86.TSS.TASK_CX, cpu.regECX);
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cpu.setShort(addrOld + X86.TSS.TASK_DX, cpu.regEDX);
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cpu.setShort(addrOld + X86.TSS.TASK_BX, cpu.regEBX);
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cpu.setShort(addrOld + X86.TSS.TASK_SP, cpu.getSP());
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cpu.setShort(addrOld + X86.TSS.TASK_BP, cpu.regEBP);
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cpu.setShort(addrOld + X86.TSS.TASK_SI, cpu.regESI);
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cpu.setShort(addrOld + X86.TSS.TASK_DI, cpu.regEDI);
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cpu.setShort(addrOld + X86.TSS.TASK_ES, cpu.segES.sel);
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cpu.setShort(addrOld + X86.TSS.TASK_CS, cpu.segCS.sel);
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cpu.setShort(addrOld + X86.TSS.TASK_SS, cpu.segSS.sel);
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cpu.setShort(addrOld + X86.TSS.TASK_DS, cpu.segDS.sel);
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var offSS = X86.TSS.TASK_SS;
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var offSP = X86.TSS.TASK_SP;
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cpu.setPS(cpu.getShort(addrNew + X86.TSS.TASK_PS) | (fNest? X86.PS.NT : 0));
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cpu.assert(!fNest || !!(cpu.regPS & X86.PS.NT));
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cpu.regEAX = cpu.getShort(addrNew + X86.TSS.TASK_AX);
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cpu.regECX = cpu.getShort(addrNew + X86.TSS.TASK_CX);
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cpu.regEDX = cpu.getShort(addrNew + X86.TSS.TASK_DX);
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cpu.regEBX = cpu.getShort(addrNew + X86.TSS.TASK_BX);
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cpu.regEBP = cpu.getShort(addrNew + X86.TSS.TASK_BP);
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cpu.regESI = cpu.getShort(addrNew + X86.TSS.TASK_SI);
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cpu.regEDI = cpu.getShort(addrNew + X86.TSS.TASK_DI);
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cpu.segES.load(cpu.getShort(addrNew + X86.TSS.TASK_ES));
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cpu.segDS.load(cpu.getShort(addrNew + X86.TSS.TASK_DS));
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cpu.setCSIP(cpu.getShort(addrNew + X86.TSS.TASK_IP), cpu.getShort(addrNew + X86.TSS.TASK_CS));
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if (this.cpl < cplOld) {
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offSP = (this.cpl << 2) + X86.TSS.CPL0_SP;
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offSS = offSP + 2;
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}
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cpu.setSS(cpu.getShort(addrNew + offSS), true);
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cpu.setSP(cpu.getShort(addrNew + offSP));
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cpu.segLDT.load(cpu.getShort(addrNew + X86.TSS.TASK_LDT));
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if (fNest) cpu.setShort(addrNew + X86.TSS.PREV_TSS, selOld);
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cpu.regCR0 |= X86.CR0.MSW.TS;
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return true;
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};
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/**
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* setBase(addr)
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*
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@ -1008,23 +1016,23 @@ X86Seg.prototype.updateMode = function(fLoad, fProt)
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};
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/**
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* messageSeg(sel, base, limit, acc, ext)
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* messageSeg(sel, base, limit, type, ext)
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*
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* @this {X86Seg}
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* @param {number} sel
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* @param {number} base
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* @param {number} limit
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* @param {number} acc
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* @param {number} type
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* @param {number} [ext]
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*/
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X86Seg.prototype.messageSeg = function(sel, base, limit, acc, ext)
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X86Seg.prototype.messageSeg = function(sel, base, limit, type, ext)
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{
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if (DEBUG) {
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if (DEBUGGER && this.dbg && this.dbg.messageEnabled(Messages.SEG)) {
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var ch = (this.sName.length < 3? " " : "");
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var sDPL = " dpl=" + this.dpl;
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if (this.id == X86Seg.ID.CODE) sDPL += " cpl=" + this.cpl;
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this.dbg.message("loadSeg(" + this.sName + "):" + ch + "sel=" + str.toHexWord(sel) + " base=" + str.toHex(base) + " limit=" + str.toHexWord(limit) + " acc=" + str.toHexWord(acc) + sDPL);
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this.dbg.message("loadSeg(" + this.sName + "):" + ch + "sel=" + str.toHexWord(sel) + " base=" + str.toHex(base) + " limit=" + str.toHexWord(limit) + " type=" + str.toHexWord(type) + sDPL, true);
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}
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this.cpu.assert(/* base !== X86.ADDR_INVALID && */ (this.cpu.model >= X86.MODEL_80386 || !ext || ext == X86.DESC.EXT.AVAIL));
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}
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