Cleaned up debugger message handling
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6248972684
commit
2ff339f190
31 changed files with 640 additions and 735 deletions
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@ -966,7 +966,7 @@ X86CPU.prototype.checkIntNotify = function(nInt)
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* checksEnabled() function, and therefore in fDebugCheck, so for maximum speed, we check fDebugCheck first.
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*/
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if (DEBUGGER && this.bitField.fDebugCheck) {
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if (this.dbg.messageEnabled(Debugger.MESSAGE.INT) && this.dbg.messageInt(nInt, this.regEIP)) {
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if (this.messageEnabled(Debugger.MESSAGE.INT) && this.dbg.messageInt(nInt, this.regEIP)) {
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this.addIntReturn(this.regEIP, function(cpu, nCycles) {
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return function onIntReturn(nLevel) {
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cpu.dbg.messageIntReturn(nInt, nLevel, cpu.getCycles() - nCycles);
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@ -1210,7 +1210,7 @@ X86CPU.prototype.getSeg = function(sName)
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* HACK: We return a fake segment register object in which only the base physical address is valid,
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* because that's all the caller provided (ie, we must be restoring from an older state).
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*/
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if (DEBUG) this.assert(typeof sName == "number");
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this.assert(typeof sName == "number");
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return [0, sName, 0, 0, ""];
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}
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};
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@ -1311,7 +1311,7 @@ X86CPU.prototype.setIP = function(off)
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*/
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X86CPU.prototype.setCSIP = function(off, sel, fCall)
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{
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if (DEBUG) this.assert((off & 0xffff) == off);
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this.assert((off & 0xffff) == off);
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this.segCS.fCall = fCall;
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/*
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* We break this operation into the following discrete steps (eg, set IP, load CS, and then update EIP)
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@ -1668,7 +1668,7 @@ X86CPU.prototype.setPS = function(regPS)
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/*
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* Assert that all requested flag bits now agree with our simulated (PS_INDIRECT) bits
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*/
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if (DEBUG) this.assert((regPS & X86.PS.INDIRECT) == (this.getPS() & X86.PS.INDIRECT));
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this.assert((regPS & X86.PS.INDIRECT) == (this.getPS() & X86.PS.INDIRECT));
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if (this.regPS & X86.PS.TF) {
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this.intFlags |= X86.INTFLAG.TRAP;
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@ -2233,7 +2233,7 @@ X86CPU.prototype.popWord = function()
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*/
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X86CPU.prototype.pushWord = function(w)
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{
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if (DEBUG) this.assert((w & 0xffff) == w);
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this.assert((w & 0xffff) == w);
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this.setSOWord(this.segSS, (this.regSP = (this.regSP - 2) & 0xffff), w);
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};
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@ -2308,7 +2308,7 @@ X86CPU.prototype.pushWord = function(w)
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*/
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X86CPU.prototype.checkINTR = function()
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{
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if (DEBUG) this.assert(this.intFlags);
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this.assert(this.intFlags);
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if (!(this.opFlags & X86.OPFLAG.NOINTR)) {
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if ((this.intFlags & X86.INTFLAG.INTR) && (this.regPS & X86.PS.IF)) {
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var nIDT = this.chipset.getIRRVector();
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@ -2495,7 +2495,7 @@ X86CPU.prototype.stepCPU = function(nMinCycles)
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* One exception I make here is when you've asked the Debugger to display PIC messages, the idea being that
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* if you're watching the PIC that closely, then you want to hardware interrupts to occur regardless.
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*/
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if (!nMinCycles && this.dbg && !this.dbg.messageEnabled(Debugger.MESSAGE.PIC)) this.opFlags |= X86.OPFLAG.NOINTR;
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if (!nMinCycles && !this.messageEnabled(Debugger.MESSAGE.PIC)) this.opFlags |= X86.OPFLAG.NOINTR;
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do {
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var opPrefixes = this.opFlags & X86.OPFLAG.PREFIXES;
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@ -2553,7 +2553,7 @@ X86CPU.prototype.stepCPU = function(nMinCycles)
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if (++this.iSampleFreq >= this.nSampleFreq) {
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this.iSampleFreq = 0;
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if (this.iSampleSkip < this.nSampleSkip) {
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this.iSampleSkip++
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this.iSampleSkip++;
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} else {
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if (this.iSampleNext == this.nSamples) {
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this.println("sample buffer full");
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@ -2621,25 +2621,6 @@ X86CPU.prototype.stepCPU = function(nMinCycles)
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return (this.bitField.fComplete? this.nBurstCycles - this.nStepCycles : (this.bitField.fComplete === undefined? 0 : -1));
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};
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/**
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* messageDebugger(sMessage, bitsMessage)
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*
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* This is a combination of the Debugger's messageEnabled(MESSAGE_CPU) and message() functions, for convenience.
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*
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* @this {X86CPU}
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* @param {string} sMessage is any caller-defined message string
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* @param {number} [bitsMessage] is one or more Debugger MESSAGE_* category flag(s)
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*/
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X86CPU.prototype.messageDebugger = function(sMessage, bitsMessage)
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{
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if (DEBUGGER && this.dbg) {
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if (bitsMessage == null) {
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bitsMessage = Debugger.MESSAGE.CPU;
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}
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if (this.dbg.messageEnabled(bitsMessage)) this.dbg.message(sMessage);
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}
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};
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/**
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* X86CPU.init()
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*
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