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Ongoing problems with tabs in README markdown files

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This commit is contained in:
Jeff Parsons 2016-11-26 14:05:53 -08:00 • committed by Jeff Parsons
commit 1e72c6a822
5 changed files with 114 additions and 115 deletions
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11
disks/dec/rl02k/xxdp/ekbad0/README.md
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@ -15,16 +15,16 @@ p. 1-6:
ABSTRACT: ABSTRACT:
This diagnostic is the first part of the 11/70 CPU, it designed to detect and This diagnostic is the first part of the 11/70 CPU, it designed to detect and
report logic faults in the CPU. Any fault detected in this program causes the report logic faults in the CPU. Any fault detected in this program causes the
program to "HALT". After this, run the second part of the CPU test, EKBBF0. program to "HALT". After this, run the second part of the CPU test, EKBBF0.
OPERATING PROCEDURES: OPERATING PROCEDURES:
Set the switch register by <CONTROL P> (RD console) Set the switch register by <CONTROL P> (RD console)
CON = xxxxxxWZ CON = xxxxxxWZ
(W = deposit xxxxxx into console switch register) (W = deposit xxxxxx into console switch register)
(R = read and type console switch settings) (R = read and type console switch settings)
(Z = switch console terminal back to program) (Z = switch console terminal back to program)
.R EKBAD0 .R EKBAD0
@ -51,4 +51,3 @@ on [bitsavers.org](http://bitsavers.trailing-edge.com/pdf/dec/pdp11/microfiche/f
PRODUCT NAME: CEKBAD0 11/70 CPU #1 PRODUCT NAME: CEKBAD0 11/70 CPU #1
DATE CREATED: MAY, 1980 DATE CREATED: MAY, 1980
MAINTAINER: DIAGNOSTIC ENGINEERING MAINTAINER: DIAGNOSTIC ENGINEERING

58
disks/dec/rl02k/xxdp/ekbbf0/README.md
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@ -15,15 +15,15 @@ p. 1-7:
ABSTRACT: ABSTRACT:
This diagnostic is the second part of the 11/70 CPU, it tests advanced This diagnostic is the second part of the 11/70 CPU, it tests advanced
instructions and miscellaneous logic. instructions and miscellaneous logic.
OPERATING PROCEDURES: OPERATING PROCEDURES:
Set the switch register by <CONTROL P> (RD console) Set the switch register by <CONTROL P> (RD console)
CON = xxxxxxWZ CON = xxxxxxWZ
(W = deposit xxxxxx into console switch register) (W = deposit xxxxxx into console switch register)
(R = read and type console switch settings) (R = read and type console switch settings)
(Z = switch console terminal back to program) (Z = switch console terminal back to program)
.R EKBBF0 .R EKBBF0
@ -144,28 +144,28 @@ The source code listing for TEST 40 matches the code above, and begins at the sa
ERROR 235 ;RED ZONE REFERENCE FAILED TO TRAP ERROR 235 ;RED ZONE REFERENCE FAILED TO TRAP
BR 8$ BR 8$
3$: MOV #STACK,SP ;RESET THE SP 3$: MOV #STACK,SP ;RESET THE SP
MOV #CPUSPUR,@#ERRVEC ;RESTORE LOCATION 4 MOV #CPUSPUR,@#ERRVEC ;RESTORE LOCATION 4
ERROR 237 ;BEN 13 FAILED TO PUP.00 ERROR 237 ;BEN 13 FAILED TO PUP.00
BR 8$ BR 8$
1$: CMP @#0,#6$ ;DID BEN 13 FAIL? 1$: CMP @#0,#6$ ;DID BEN 13 FAIL?
BEQ 7$ ;BRANCH IF NO BEQ 7$ ;BRANCH IF NO
MOV #STACK,SP ;RESET THE SP MOV #STACK,SP ;RESET THE SP
MOV #CPUSPUR,@#ERRVEC ;RESTORE ERRVEC MOV #CPUSPUR,@#ERRVEC ;RESTORE ERRVEC
ERROR 240 ;BEN 13 FAILED TO BRK.80 ERROR 240 ;BEN 13 FAILED TO BRK.80
BR 8$ BR 8$
7$: CMP #-1,@#336 ;;DID YEL ZONE OCCUR? 7$: CMP #-1,@#336 ;;DID YEL ZONE OCCUR?
BNE 8$ ;BRANCH IF NO BNE 8$ ;BRANCH IF NO
CLR @#336 ;SETUP FOR LOOPING CLR @#336 ;SETUP FOR LOOPING
ERROR 251 ;YEL ZONE IN RED REGION ERROR 251 ;YEL ZONE IN RED REGION
; ;
;TEST TO ENSURE PSW REFERENCE VIA THE SP CAUSES A RED ZONE TRAP ;TEST TO ENSURE PSW REFERENCE VIA THE SP CAUSES A RED ZONE TRAP
8$: MOV #63$,$LPERR ;SETUP ERROR LOOP 8$: MOV #63$,$LPERR ;SETUP ERROR LOOP
63$: MOV #4$,@#ERRVEC ;SETUP ERRVEC 63$: MOV #4$,@#ERRVEC ;SETUP ERRVEC
MOV #PSW,SP ;PUT ADDRESS OF PSW IN SP MOV #PSW,SP ;PUT ADDRESS OF PSW IN SP
CLR (SP) ;EXECUTE THE TRAP CAUSING INSTRUCTION CLR (SP) ;EXECUTE THE TRAP CAUSING INSTRUCTION
MOV #1076,SP ;RESET THE SP MOV #1076,SP ;RESET THE SP
MOV #CPUSPUR,@#ERRVEC ;RESTORE ERRVEC MOV #CPUSPUR,@#ERRVEC ;RESTORE ERRVEC
ERROR 241 ;NO RED ZONE ON STACK OVERFLOW ERROR 241 ;NO RED ZONE ON STACK OVERFLOW
PDPjs was failing to trigger a RED stack violation on this instruction: PDPjs was failing to trigger a RED stack violation on this instruction:
@ -189,20 +189,20 @@ and begins at the same address (031532):
;* OCCURS AND NOT THE T BIT TRAP. ;* OCCURS AND NOT THE T BIT TRAP.
;;*************************************************************** ;;***************************************************************
TST63: SCOPE TST63: SCOPE
MOV #TST64,NEXTTST ;SAVE ADDRESS OF NEXT TEST MOV #TST64,NEXTTST ;SAVE ADDRESS OF NEXT TEST
MOV #^D1990,$ICNT ;ADJUST ITTERATION COUNT MOV #^D1990,$ICNT ;ADJUST ITTERATION COUNT
MOV #10$,$LPADR ;SETUP LOOP ADR MOV #10$,$LPADR ;SETUP LOOP ADR
10$: MOV #2$,@#TPVEC ;SETUP TELEPRINTER VECTOR 10$: MOV #2$,@#TPVEC ;SETUP TELEPRINTER VECTOR
MOV #1$,$LPERR ;SETUP ERROR LOOP MOV #1$,$LPERR ;SETUP ERROR LOOP
1$: MOV #STACK,SP ;INITIALIZE THE SP 1$: MOV #STACK,SP ;INITIALIZE THE SP
SPL 3 SPL 3
MOV #BIT6,@$TPS ;SET PRINTER INTERRUPT FLAG MOV #BIT6,@$TPS ;SET PRINTER INTERRUPT FLAG
MOV #15,@$TPB ;SEND CHARACTER MOV #15,@$TPB ;SEND CHARACTER
WAIT ;EXECUTE INSTRUCTION UNDER TEST WAIT ;EXECUTE INSTRUCTION UNDER TEST
;FAILURE ;FAILURE
CLR @$TPS ;CLEAR INTERR ENABLE BIT CLR @$TPS ;CLEAR INTERR ENABLE BIT
ERROR 377 ;WAIT INSTRUCTION DID NOT ERROR 377 ;WAIT INSTRUCTION DID NOT
BR 5$ ;WAIT FOR INTERRUPT BR 5$ ;WAIT FOR INTERRUPT
After setting and hitting a breakpoint at 031532, we can step through the instructions in this test: After setting and hitting a breakpoint at 031532, we can step through the instructions in this test:

56
disks/dec/rl02k/xxdp/ekbee1/README.md
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@ -15,33 +15,33 @@ p. 1-10:
ABSTRACT: ABSTRACT:
This program was designed using a "BOTTOM UP" approach starting with the smallest segment of MEMORY This program was designed using a "BOTTOM UP" approach starting with the smallest segment of MEMORY
MANAGEMENT logic and building up to cover all the logic. The program begins by testing some of the MANAGEMENT logic and building up to cover all the logic. The program begins by testing some of the
internal CPU data and address path and address detection logic, then works outward through the MEM. internal CPU data and address path and address detection logic, then works outward through the MEM.
MANAGEMENT registers. It is assumed that both the CPU and the CACHE have been tested, or are known MANAGEMENT registers. It is assumed that both the CPU and the CACHE have been tested, or are known
to be good. to be good.
OPERATING PROCEDURES: OPERATING PROCEDURES:
Set the switch register by <CONTROL P> Set the switch register by <CONTROL P>
CON = xxxxxxWZ CON = xxxxxxWZ
(W = deposit xxxxxx into console switch register) (W = deposit xxxxxx into console switch register)
(R = read and type console switch settings / CON = R) (R = read and type console switch settings / CON = R)
(Z = switch console terminal back to program) (Z = switch console terminal back to program)
.R EKBEE1 .R EKBEE1
SWITCH SETTINGS SWITCH SETTINGS
SW15 = 1 halt on error SW15 = 1 halt on error
SW14 = 1 loop on current test SW14 = 1 loop on current test
SW13 = 1 inhibit all error typeouts SW13 = 1 inhibit all error typeouts
SW12 = 1 inhibit trace trapping SW12 = 1 inhibit trace trapping
SW11 = 1 inhibit iterations SW11 = 1 inhibit iterations
SW10 = 1 ring bell on error SW10 = 1 ring bell on error
SW09 = 1 loop on error SW09 = 1 loop on error
SW08 = 1 loop on test in SWR <06:00> SW08 = 1 loop on test in SWR <06:00>
SW07 = 1 inhibit multiple error typeouts SW07 = 1 inhibit multiple error typeouts
SW06 = 1 selects subtest SW06 = 1 selects subtest
... ...
The closest we have to a source code listing of the EKBEE1 diagnostic comes from some The closest we have to a source code listing of the EKBEE1 diagnostic comes from some
[scanned microfiche](http://archive.pcjs.org/pubs/dec/pdp11/diags/AC-7975E-MC_CEKBEE0_1170_MEM_MGMT_May80.pdf) [scanned microfiche](http://archive.pcjs.org/pubs/dec/pdp11/diags/AC-7975E-MC_CEKBEE0_1170_MEM_MGMT_May80.pdf)
@ -59,13 +59,13 @@ the PDF (p. 199 of the source code listing):
;*TEST 122 KT BEND ;*TEST 122 KT BEND
;* ;*
;* THIS TEST ENSURES THAT TMCE KT BEND GOES LOW ON AN ODD ;* THIS TEST ENSURES THAT TMCE KT BEND GOES LOW ON AN ODD
;* ADDRESS ERROR, SL RED, AND NEXM. THIS IS DONE BY EXECUTING ;* ADDRESS ERROR, SL RED, AND NEXM. THIS IS DONE BY EXECUTING
;* AN INSTRUCTION FOR EACH Of THESE THESE CASES THAT ALSO ;* AN INSTRUCTION FOR EACH Of THESE THESE CASES THAT ALSO
;* CAUSES A KT ABORT. THE ABORT SHOULD NOT BE HONORED. ;* CAUSES A KT ABORT. THE ABORT SHOULD NOT BE HONORED.
;* ;*
;* NOTE: ON A KB11-E OR KB11-EM THE KT ABORT SHOULD BE HONORED OVER A ;* NOTE: ON A KB11-E OR KB11-EM THE KT ABORT SHOULD BE HONORED OVER A
;* NEXM TRAP. IF THIS IS A KB11-E/EM THEN THIS FEATURE IS TESTED. ;* NEXM TRAP. IF THIS IS A KB11-E/EM THEN THIS FEATURE IS TESTED.
;;*************************************************************** ;;***************************************************************
As noted in the *mapVirtualToPhysical()* function in [cpustate.js](/modules/pdp11/lib/cpustate.js), this test As noted in the *mapVirtualToPhysical()* function in [cpustate.js](/modules/pdp11/lib/cpustate.js), this test
begins at PC 076060, which is exactly 0100 bytes lower than the address shown in the source code listing (076160). begins at PC 076060, which is exactly 0100 bytes lower than the address shown in the source code listing (076160).