Cleaned up management of unused PSW bits
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85c7d0151c
commit
1e1db7b78e
24 changed files with 574 additions and 530 deletions
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@ -1736,7 +1736,7 @@ PDP11.opSPL = function(opCode)
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return;
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}
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if (!(this.regPSW & PDP11.PSW.CMODE)) {
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this.regPSW = (this.regPSW & ~(PDP11.PSW.UNUSED | PDP11.PSW.PRI)) | ((opCode & 0x7) << PDP11.PSW.SHIFT.PRI);
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this.regPSW = (this.regPSW & ~PDP11.PSW.PRI) | ((opCode & 0x7) << PDP11.PSW.SHIFT.PRI);
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this.opFlags |= PDP11.OPFLAG.IRQ_DELAY;
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this.opFlags &= ~PDP11.OPFLAG.IRQ;
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}
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@ -134,14 +134,18 @@ CPUStatePDP11.prototype.initProcessor = function()
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this.offRegSrc = 0;
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this.maskRegSrcByte = 0xff;
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if (this.model == PDP11.MODEL_1120) {
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if (this.model <= PDP11.MODEL_1120) {
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this.decode = PDP11.op1120.bind(this);
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this.checkStackLimit = this.checkStackLimit1120;
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this.offRegSrc = 8;
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this.maskRegSrcByte = -1;
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this.pswUsed = ~(PDP11.PSW.UNUSED | PDP11.PSW.REGSET | PDP11.PSW.PMODE | PDP11.PSW.CMODE) & 0xffff;
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this.pswRegSet = 0;
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} else {
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this.decode = PDP11.op1145.bind(this);
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this.checkStackLimit = this.checkStackLimit1145;
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this.pswUsed = ~(PDP11.PSW.UNUSED | (this.model < PDP11.MODEL_1145? PDP11.PSW.REGSET : 0)) & 0xffff;
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this.pswRegSet = (this.model >= PDP11.MODEL_1145? PDP11.PSW.REGSET : 0);
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}
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this.initRegs();
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@ -728,16 +732,15 @@ CPUStatePDP11.prototype.setNF = function()
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*/
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CPUStatePDP11.prototype.getOpcode = function()
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{
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var pc = this.regsGen[PDP11.REG.PC];
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this.opLast = pc;
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var pc = this.opLast = this.regsGen[PDP11.REG.PC];
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/*
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* If PC is unaligned, a BUS trap will be generated, and because it will generate an
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* exception, the next line (the equivalent of advancePC(2)) will not be executed, ensuring that
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* original unaligned PC will be pushed onto the stack by trap().
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*/
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var op = this.readWord(pc);
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var opCode = this.readWord(pc);
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this.regsGen[PDP11.REG.PC] = (pc + 2) & 0xffff;
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return op;
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return opCode;
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};
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/**
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@ -1124,9 +1127,9 @@ CPUStatePDP11.prototype.getPSW = function()
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/**
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* setPSW(newPSW)
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*
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* This updates the CPU Processor Status Word. The PSW should generally be written through
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* This updates the CPU Processor Status Word. The PSW should generally be written through
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* this routine so that changes can be tracked properly, for example the correct register set,
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* the current memory management mode, etc. An exception is SPL which writes the priority directly.
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* the current memory management mode, etc. An exception is SPL which writes the priority directly.
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* Note that that N, Z, V, and C flags are actually stored separately for performance reasons.
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*
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* PSW 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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@ -1137,11 +1140,12 @@ CPUStatePDP11.prototype.getPSW = function()
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*/
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CPUStatePDP11.prototype.setPSW = function(newPSW)
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{
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newPSW &= this.pswUsed;
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this.flagN = newPSW << 12;
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this.flagZ = (~newPSW) & 4;
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this.flagV = newPSW << 14;
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this.flagC = newPSW << 16;
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if ((newPSW ^ this.regPSW) & PDP11.PSW.REGSET) {
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if ((newPSW ^ this.regPSW) & this.pswRegSet) {
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/*
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* Swap register sets
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*/
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@ -1500,7 +1504,7 @@ CPUStatePDP11.prototype.trapReturn = function()
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* safer, but if we're going to do pushes in trap(), then I see no reason to avoid doing pops in trapReturn().
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*/
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var addr = this.popWord();
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var newPSW = this.popWord() & ~PDP11.PSW.UNUSED;
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var newPSW = this.popWord();
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if (this.regPSW & PDP11.PSW.CMODE) {
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/*
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* Keep SPL and allow lower only for modes and register set.
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@ -2594,11 +2598,11 @@ CPUStatePDP11.prototype.branch = function(opCode, condition)
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CPUStatePDP11.prototype.stepCPU = function(nMinCycles)
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{
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/*
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* The Debugger uses fComplete to determine if the instruction completed (true) or was interrupted
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* The Debugger uses complete to determine if the instruction completed (true) or was interrupted
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* by a breakpoint or some other exceptional condition (false). NOTE: this does NOT include JavaScript
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* exceptions, which stepCPU() expects the caller to catch using its own exception handler.
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*
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* The CPU relies on the use of stopCPU() rather than fComplete, because the CPU never single-steps
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* The CPU relies on the use of stopCPU() rather than complete, because the CPU never single-steps
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* (ie, nMinCycles is always some large number), whereas the Debugger does. And conversely, when the
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* Debugger is single-stepping (even when performing multiple single-steps), fRunning is never set,
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* so stopCPU() would have no effect as far as the Debugger is concerned.
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@ -2618,11 +2622,7 @@ CPUStatePDP11.prototype.stepCPU = function(nMinCycles)
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* if nDebugState is <= zero).
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*/
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var nDebugState = (!nMinCycles)? -1 : (this.flags.starting? 0 : 1);
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/*
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* We've moved beyond "starting" now and have officially "started".
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*/
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this.flags.starting = false;
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this.flags.starting = false; // we've moved beyond "starting" and have officially "started" now
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/*
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* We move the minimum cycle count to nStepCycles (the number of cycles left to step), so that other
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@ -2631,16 +2631,25 @@ CPUStatePDP11.prototype.stepCPU = function(nMinCycles)
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*/
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this.nBurstCycles = this.nStepCycles = nMinCycles;
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/*
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* And finally, move the nDebugCheck state to an OPFLAG bit, so that the loop need check only one variable.
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*/
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this.opFlags = (this.opFlags & ~PDP11.OPFLAG.DEBUGGER) | (nDebugCheck? PDP11.OPFLAG.DEBUGGER : 0);
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do {
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if (DEBUGGER && nDebugCheck) {
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if (this.dbg.checkInstruction(this.getPC(), nDebugState)) {
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this.stopCPU();
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break;
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}
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if (!nDebugState) nDebugState++;
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nDebugCheck++;
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}
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if (this.opFlags) {
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/*
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* NOTE: We still check DEBUGGER to ensure that this code will be compiled out of existence in
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* non-DEBUGGER builds.
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*/
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if (DEBUGGER && (this.opFlags & PDP11.OPFLAG.DEBUGGER)) {
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if (this.dbg.checkInstruction(this.getPC(), nDebugState)) {
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this.stopCPU();
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break;
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}
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if (!++nDebugCheck) this.opFlags &= ~PDP11.OPFLAG.DEBUGGER;
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if (!nDebugState) nDebugState++;
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}
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/*
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* If we're in the IRQ or WAIT state, check for any pending interrupts.
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*
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@ -2651,7 +2660,7 @@ CPUStatePDP11.prototype.stepCPU = function(nMinCycles)
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*/
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if ((this.opFlags & (PDP11.OPFLAG.IRQ_MASK | PDP11.OPFLAG.WAIT)) /* && nDebugState >= 0 */) {
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if (this.checkInterrupts()) {
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if (DEBUGGER && nDebugCheck && this.dbg.checkInstruction(this.getPC(), nDebugState)) {
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if ((this.opFlags & PDP11.OPFLAG.DEBUGGER) && this.dbg.checkInstruction(this.getPC(), nDebugState)) {
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this.stopCPU();
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break;
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}
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@ -2674,15 +2683,13 @@ CPUStatePDP11.prototype.stepCPU = function(nMinCycles)
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*/
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if (this.opFlags & PDP11.OPFLAG.TRAP_MASK) {
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if (this.checkTraps()) {
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if (DEBUGGER && nDebugCheck && this.dbg.checkInstruction(this.getPC(), nDebugState)) {
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if ((this.opFlags & PDP11.OPFLAG.DEBUGGER) && this.dbg.checkInstruction(this.getPC(), nDebugState)) {
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this.stopCPU();
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break;
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}
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if (nDebugState < 0) break;
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}
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}
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} else {
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this.assert(!this.irqNext && !this.regPIR);
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}
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/*
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@ -2691,7 +2698,8 @@ CPUStatePDP11.prototype.stepCPU = function(nMinCycles)
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*/
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this.opFlags = (this.opFlags & PDP11.OPFLAG.PRESERVE) | (this.regPSW & PDP11.PSW.TF);
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this.decode(this.getOpcode());
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var opCode = this.getOpcode();
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this.decode(opCode);
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} while (this.nStepCycles > 0);
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@ -124,8 +124,20 @@ var PDP11 = {
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/*
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* CPU model numbers (supported)
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*
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* The 11/20 includes the 11/10, which is not identified separately because there was
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* nothing functionally different about it.
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*
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* The 11/40 added the MODE bits to the PSW (but only KERNEL=00 and USER=11) and 18-bit
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* addressing via an MMU; there was still only one register set.
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*
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* The 11/45 added REGSET bit to the PSW (along with the second register set), and added
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* SUPERVISOR=01 to the set of modes.
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*
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* The 11/70 added 22-bit addressing and corresponding extensions to the MMU.
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*/
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MODEL_1120: 1120,
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MODEL_1140: 1140,
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MODEL_1145: 1145,
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MODEL_1170: 1170,
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@ -169,9 +181,13 @@ var PDP11 = {
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PRI: 0x00E0, // bits 5-7 (000340) Priority
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UNUSED: 0x0700, // bits 8-10 (003400) UNUSED
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/*
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* PSW bits above this point are unused on 11/20-class machines
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* The REGSET bit (and the alternate register set stored in regsAlt) came into existence
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* with the 11/45; (ie, they were not present on the 11/10, 11/20, or 11/40).
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*/
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REGSET: 0x0800, // bit 11 (004000) Register Set
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/*
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* The MODE bits came into existence with the 11/40 (eg, not present on the 11/10 or 11/20).
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*/
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PMODE: 0x3000, // bits 12-13 (030000) Prev Mode (see PDP11.MODE)
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CMODE: 0xC000, // bits 14-15 (140000) Curr Mode (see PDP11.MODE)
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SHIFT: {
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@ -266,6 +282,7 @@ var PDP11 = {
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IRQ_DELAY: 0x0001, // incremented until it becomes IRQ (set by SPL and traps)
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IRQ: 0x0002, // time to call checkInterrupts()
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IRQ_MASK: 0x0003,
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DEBUGGER: 0x0004, // set if the Debugger wants to perform checks
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WAIT: 0x0008, // WAIT operation in progress
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PRESERVE: 0x000F, // OPFLAG bits to preserve prior to the next instruction
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TRAP_TF: 0x0010, // aka PDP11.PSW.TF (WARNING: do not change this bit, or you will likely break opRTI())
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@ -873,8 +890,7 @@ PDP11.ACCESS.UPDATE_WORD = PDP11.ACCESS.WORD | PDP11.ACCESS.UPDATE; // forme
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PDP11.ACCESS.UPDATE_BYTE = PDP11.ACCESS.BYTE | PDP11.ACCESS.UPDATE; // formerly MODIFY_BYTE (1 | 2 | 4)
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/*
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* PSW arithmetic flags are NOT stored directly into the PSW register; they are maintained across separate
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* flag registers.
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* PSW arithmetic flags are NOT stored directly into the PSW register; they are maintained across separate flag registers.
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*/
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PDP11.PSW.FLAGS = (PDP11.PSW.NF | PDP11.PSW.ZF | PDP11.PSW.VF | PDP11.PSW.CF);
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@ -1078,11 +1078,13 @@ DevicePDP11.prototype.writePSW = function(data, addr)
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*
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* 004174: 052767 000020 173574 BIS #20,177776
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*
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* Since that test was written for the PDP-11/20, it's possible that newer machines
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* have a different behavior, but for now, we assume that all machines allow setting PSW.TF.
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* Since that test was written for the PDP-11/20, it's possible that newer machines have a different
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* behavior, but for now, we assume that all machines allow setting PSW.TF.
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*
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* Moreover, we have changed setPSW() to disallow the setting of any bits not supported by the current
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* CPU model, so it seems rather pointless to do any masking of bits here.
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*/
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var maskDisallowed = PDP11.PSW.UNUSED;
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this.cpu.setPSW((data & ~maskDisallowed) | (this.cpu.getPSW() & maskDisallowed));
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this.cpu.setPSW(data);
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};
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/**
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