Added some comments on cycle times

This commit is contained in:
Jeff 2016-09-29 15:36:34 -07:00 committed by Jeff Parsons
commit 1d395b7bd5
2 changed files with 26 additions and 1 deletions

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@ -3,7 +3,7 @@
<machine id="test1170" class="pdp11" border="1" pos="center" background="#FAEBD7">
<name pos="center">PDP-11/70 Test Machine</name>
<computer id="computer" busWidth="22"/>
<cpu id="cpu" model="1170" cycles="2000000" resetAddr="0xC000"/>
<cpu id="cpu" model="1170" cycles="6666667" resetAddr="0xC000"/>
<ram id="ram" addr="0x0000" size="0xC000"/>
<rom id="rom" addr="0xC000" size="0x0570" file="/devices/pdp11/rom/custom/boot.json"/>
<ram id="ram" addr="0x10000" size="0x34000"/>

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@ -40,6 +40,31 @@ if (NODE) {
var MessagesPDP11 = require("./messages");
}
/*
* A word (or more) about PDP-11 speeds:
*
* After looking over the timings of PDP-11/70 instructions, nearly all of them appear
* to be multiples of 150ns. So that's what we'll consider a cycle. How many 150ns are
* in one second? Approximately 6666667. So by way of comparison to other PCjs machines,
* that makes the PDP-11 (or at least the PDP-11/70) look like a 6.67Mhz machine.
*
* I've started with the PDP-11/70, since that's what Paul Nankervis started with. When
* I go back and add support for earlier PDP-11 models (primarily by neutering functions
* that didn't exist), I will no doubt have to tweak some instruction cycle counts, too.
*
* Examples of operations that take 1 extra cycle (150ns): single and double operand byte
* instructions with an odd address (except MOV/MTPI/MTPD/JMP/JRS), ADD/SUB/BIC/BIS/MOVB/CMP/BIT
* instructions with src of R1-R7 and dst of R6-R7, RORB/ASRB with an odd address, and each
* shift of ASH/ASHC. As you can see, the rules are not simple.
*
* We're not simulating cache hardware, but our timings should be optimistic and assume 100%
* cache hits; for cache hits, each read cycle is 300ns. As for write cycles, they are always
* 750ns. My initial take on DEC's timings is that they are including the write time as part
* of the total EF (execute/fetch) time. So, for instructions that write to memory, it looks
* like we'll normally need to add 5 cycles (750/150) to the instruction's base time, but
* we'll need to keep an eye for exceptions.
*/
/**
* CPUPDP11(parmsCPU, nCyclesDefault)
*