PC8080 skeleton
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Jeff Parsons
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modules/pc8080/lib/cpudef.js
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modules/pc8080/lib/cpudef.js
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/**
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* @fileoverview Defines PC8080 constants.
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* @author <a href="mailto:Jeff@pcjs.org">Jeff Parsons</a>
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* @version 1.0
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* Created 2016-Apr-18
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*
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* Copyright © 2012-2016 Jeff Parsons <Jeff@pcjs.org>
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*
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* This file is part of PCjs, which is part of the JavaScript Machines Project (aka JSMachines)
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* at <http://jsmachines.net/> and <http://pcjs.org/>.
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*
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* PCjs is free software: you can redistribute it and/or modify it under the terms of the
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* GNU General Public License as published by the Free Software Foundation, either version 3
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* of the License, or (at your option) any later version.
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*
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* PCjs is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without
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* even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCjs. If not,
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* see <http://www.gnu.org/licenses/gpl.html>.
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*
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* You are required to include the above copyright notice in every source code file of every
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* copy or modified version of this work, and to display that copyright notice on every screen
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* that loads or runs any version of this software (see Computer.COPYRIGHT).
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*
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* Some PCjs files also attempt to load external resource files, such as character-image files,
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* ROM files, and disk image files. Those external resource files are not considered part of the
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* PCjs program for purposes of the GNU General Public License, and the author does not claim
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* any copyright as to their contents.
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*/
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"use strict";
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var CPUDef = {
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/*
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* CPU model numbers (supported)
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*/
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MODEL_8080: 8080,
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/*
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* This constant is used to mark points in the code where the physical address being returned
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* is invalid and should not be used.
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*
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* In a 32-bit CPU, -1 (ie, 0xffffffff) could actually be a valid address, so consider changing
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* ADDR_INVALID to NaN or null (which is also why all ADDR_INVALID tests should use strict equality
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* operators).
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*
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* The main reason I'm NOT using NaN or null now is my concern that, by mixing non-numbers
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* (specifically, values outside the range of signed 32-bit integers), performance may suffer.
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*
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* WARNING: Like many of the properties defined here, ADDR_INVALID is a common constant, which the
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* Closure Compiler will happily inline (with or without @const annotations; in fact, I've yet to
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* see a @const annotation EVER improve automatic inlining). However, if you don't make ABSOLUTELY
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* certain that this file is included BEFORE the first reference to any of these properties, that
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* automatic inlining will no longer occur.
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*/
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ADDR_INVALID: -1,
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/*
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* Processor Status flag definitions (stored in regPS)
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*/
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PS: {
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CF: 0x0001, // bit 0: Carry flag
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BIT1: 0x0002, // bit 1: reserved, always set
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PF: 0x0004, // bit 2: Parity flag
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BIT3: 0x0008, // bit 3: reserved, always clear
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AF: 0x0010, // bit 4: Auxiliary Carry flag
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BIT5: 0x0020, // bit 5: reserved, always clear
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ZF: 0x0040, // bit 6: Zero flag
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SF: 0x0080, // bit 7: Sign flag
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ALL: 0x00D5, // CF, PF, AF, ZF, SF
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MASK: 0x00FF, //
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IF: 0x0200, // bit 9: Interrupt flag (for internal use only)
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OF: 0x0800 // bit 11: Overflow flag (for internal use only)
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},
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RESULT: {
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/*
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* Flags are computed using the following internal registers:
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*
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* CF: resultZeroCarry & resultSize (ie, 0x100 or 0x10000)
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* PF: resultParitySign & 0xff
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* AF: (resultParitySign ^ resultAuxOverflow) & 0x0010
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* ZF: resultZeroCarry & (resultSize - 1)
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* SF: resultParitySign & (resultSize >> 1)
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* OF: (resultParitySign ^ resultAuxOverflow ^ (resultParitySign >> 1)) & (resultSize >> 1)
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*/
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SIZE_BYTE: 0x00100, // mask for byte arithmetic instructions (after subtracting 1)
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SIZE_WORD: 0x10000, // mask for word arithmetic instructions (after subtracting 1)
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AUXOVF_AF: 0x00010,
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AUXOVF_OF: 0x08080,
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AUXOVF_CF: 0x10100
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},
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PARITY: [ // 256-byte array with a 1 wherever the number of set bits of the array index is EVEN
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1
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],
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/*
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* Bit values for opFlags, which are all reset to zero prior to each instruction
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*/
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OPFLAG: {
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NOREAD: 0x0001, // disable memory reads for the remainder of the current instruction
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NOWRITE: 0x0002, // disable memory writes for the remainder of the current instruction
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NOINTR: 0x0004 // a segreg has been set, or a prefix, or an STI (delay INTR acknowledgement)
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},
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/*
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* Bit values for intFlags
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*/
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INTFLAG: {
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NONE: 0x00,
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INTR: 0x01, // h/w interrupt requested
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HALT: 0x04 // halt (HLT) requested
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},
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/*
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* Opcode definitions
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*/
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OPCODE: {
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ACI: 0xCE, // PS.ALL
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CALL: 0xCD
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// to be continued....
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},
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CYCLES: {
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ACI: 7 // 2 cycles, 7 states
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// to be continued....
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}
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};
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/*
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* Some PS flags are stored directly in regPS, hence the "direct" designation.
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*/
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CPUDef.PS.DIRECT = (CPUDef.PS.IF);
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/*
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* However, PS "arithmetic" flags are NOT stored in regPS; they are maintained across
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* separate result registers, hence the "indirect" designation.
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*/
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CPUDef.PS.INDIRECT = (CPUDef.PS.CF | CPUDef.PS.PF | CPUDef.PS.AF | CPUDef.PS.ZF | CPUDef.PS.SF | CPUDef.PS.OF);
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/*
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* These are the default "always set" PS bits for the 8080.
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*/
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CPUDef.PS.SET = (CPUDef.PS.BIT1);
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if (NODE) module.exports = CPUDef;
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