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Infrastructure in place for 8080 hardware interrupts (more specifically, vertical retrace interrupts)

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This commit is contained in:
Jeff Parsons 2016-04-25 18:39:43 -07:00
commit 07259c93ef
17 changed files with 1072 additions and 434 deletions
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16
modules/pc8080/lib/cpudef.js
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@ -91,28 +91,22 @@ var CPUDef = {
0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1
],
/*
* Bit values for opFlags, which are all reset to zero prior to each instruction
*/
OPFLAG: {
NOREAD: 0x0001, // disable memory reads for the remainder of the current instruction
NOWRITE: 0x0002, // disable memory writes for the remainder of the current instruction
NOINTR: 0x0004 // a segreg has been set, or a prefix, or an STI (delay INTR acknowledgement)
},
/*
* Bit values for intFlags
*/
INTFLAG: {
NONE: 0x00,
INTR: 0x01, // h/w interrupt requested
HALT: 0x04 // halt (HLT) requested
INTL: 0x07, // last interrupt level requested
INTR: 0x08, // set if interrupt has been requested
HALT: 0x10 // halt requested; see the HLT opcode
},
/*
* Opcode definitions
*/
OPCODE: {
ACI: 0xCE, // PS.ALL
CALL: 0xCD
CALL: 0xCD,
RST0: 0xC7
// to be continued....
}
};