Fixed a double-trap MMU bug (both src and dst operands triggered a trap, but since the latter was an abort, the former needed to be ignored)
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Jeff
Jeff Parsons
parent
9148cec085
commit
05c2f0ebfe
4 changed files with 47 additions and 37 deletions
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@ -169,9 +169,10 @@ CPUStatePDP11.prototype.initRegs = function()
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/*
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* TODO: Verify the initial state of all PDP-11 flags and registers (are they well-documented?)
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*/
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var f = 0xffff;
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this.flagC = 0x10000; // PSW C bit
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this.flagV = 0x8000; // PSW V bit
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this.flagZ = 0xffff; // ~ PSW Z bit (TODO: Why do we clear instead of set Z, like other flags?)
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this.flagZ = f; // ~ PSW Z bit (TODO: Why do we clear instead of set Z, like other flags?)
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this.flagN = 0x8000; // PSW N bit
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this.regPSW = 0x000f; // PSW other bits (TODO: What's the point of setting the flag bits here, too?)
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this.regsGen = [ // General R0 - R7
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@ -185,19 +186,18 @@ CPUStatePDP11.prototype.initRegs = function()
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];
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this.mmuMode = 0; // current memory management mode (see PDP11.MODE.KERNEL | SUPER | UNUSED | USER)
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this.mmuLastPage = 0;
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// this.mmuLastVirtual = 0;
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this.mapMMR3 = [4,2,0,1]; // map from mode to MMR3 I/D bit
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this.mmuPDR = [ // memory management PDR registers by mode
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[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], // kernel 0
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[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], // super 1
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[0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff], // mode 2 with illegal PDRs
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[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] // user 3
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[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], // KERNEL (8 KIPDR regs followed by 8 KDPDR regs)
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[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], // SUPER (8 SIPDR regs followed by 8 SDPDR regs)
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[f, f, f, f, f, f, f, f, f, f, f, f, f, f, f, f], // mode 2 (not used)
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[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] // USER (8 UIPDR regs followed by 8 UDPDR regs)
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];
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this.mmuPAR = [ // memory management PAR registers by mode
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[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], // kernel 0
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[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], // super 1
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[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], // KERNEL (8 KIPAR regs followed by 8 KDPAR regs)
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[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], // SUPER (8 SIPDR regs followed by 8 SDPDR regs)
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[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], // mode 2 (not used)
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[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] // user 3
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[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] // USER (8 UIPDR regs followed by 8 UDPDR regs)
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];
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this.unibusMap = [ // 32 unibus map registers
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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@ -1541,7 +1541,6 @@ CPUStatePDP11.prototype.mapVirtualToPhysical = function(virtualAddress, accessFl
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*/
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if (!(accessFlags & this.mmuEnable)) {
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physicalAddress = virtualAddress & 0xffff;
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// this.mmuLastVirtual = physicalAddress;
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if (physicalAddress >= BusPDP11.IOPAGE_16BIT) {
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physicalAddress |= this.addrIOPage;
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}
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@ -1552,44 +1551,54 @@ CPUStatePDP11.prototype.mapVirtualToPhysical = function(virtualAddress, accessFl
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if (!(this.regMMR3 & this.mapMMR3[this.mmuMode])) page &= 7;
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pdr = this.mmuPDR[this.mmuMode][page];
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physicalAddress = ((this.mmuPAR[this.mmuMode][page] << 6) + (virtualAddress & 0x1fff)) & this.mmuMask;
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// this.mmuLastVirtual = virtualAddress;
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var newMMR0 = 0;
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switch (pdr & 0x7) {
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case 1: // read-only with trap
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switch (pdr & PDP11.PDR.ACF.MASK) {
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case PDP11.PDR.ACF.RO1: // 0x1: read-only, abort on write attempt, memory management trap on read (11/70 only)
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newMMR0 = PDP11.MMR0.TRAP_MMU;
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/* falls through */
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case 2: // read-only
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pdr |= 0x80; // Set A bit
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case PDP11.PDR.ACF.RO: // 0x2: read-only, abort on write attempt
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pdr |= PDP11.PDR.ACCESSED;
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if (accessFlags & PDP11.ACCESS.WRITE) {
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newMMR0 = PDP11.MMR0.ABORT_RO;
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}
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break;
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case 4: // read-write with read-write trap
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case PDP11.PDR.ACF.RW1: // 0x4: read/write, memory management trap upon completion of a read or write
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newMMR0 = PDP11.MMR0.TRAP_MMU;
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/* falls through */
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case 5: // read-write with write trap
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case PDP11.PDR.ACF.RW2: // 0x5: read/write, memory management trap upon completion of a write (11/70 only)
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if (accessFlags & PDP11.ACCESS.WRITE) {
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newMMR0 = PDP11.MMR0.TRAP_MMU;
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}
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/* falls through */
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case 6: // read-write: set A & W bits
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case PDP11.PDR.ACF.RW: // 0x6: read/write, no system trap/abort action
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pdr |= ((accessFlags & PDP11.ACCESS.WRITE) ? 0xc0 : 0x80);
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break;
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default:
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default: // 0x0 (non-resident, abort all accesses) or 0x3 or 0x7 (unused, abort all accesses)
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newMMR0 = PDP11.MMR0.ABORT_NR;
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break;
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}
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if ((pdr & 0x7f08) != 0x7f00) { // skip checking most common case (hopefully)
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if (pdr & 0x8) { // expand downwards
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if (pdr & 0x7f00) {
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if ((virtualAddress & 0x1fc0) < ((pdr >> 2) & 0x1fc0)) {
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if ((pdr & (PDP11.PDR.PLF | PDP11.PDR.ED)) != PDP11.PDR.PLF) { // skip checking most common case (hopefully)
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/*
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* The Page Descriptor Register (PDR) Page Length Field (PLF) is a 7-bit block number, where a block
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* is 64 bytes. Since the bit 0 of the block number is located at bit 8 of the PDR, we shift the PDR
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* right 2 bits and then clear the bottom 6 bits by masking it with 0x1FC0.
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*/
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if (pdr & PDP11.PDR.ED) {
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if (pdr & PDP11.PDR.PLF) {
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if ((virtualAddress & 0x1FC0) < ((pdr >> 2) & 0x1FC0)) {
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newMMR0 |= PDP11.MMR0.ABORT_PL;
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}
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}
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} else { // expand upwards
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if ((virtualAddress & 0x1fc0) > ((pdr >> 2) & 0x1fc0)) {
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} else {
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if ((virtualAddress & 0x1FC0) > ((pdr >> 2) & 0x1FC0)) {
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newMMR0 |= PDP11.MMR0.ABORT_PL;
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}
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}
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@ -1619,7 +1628,7 @@ CPUStatePDP11.prototype.mapVirtualToPhysical = function(virtualAddress, accessFl
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* because otherwise we run the risk of infinitely looping; eg, we call trap(), which
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* calls mapVirtualToPhysical() on the trap vector, which faults again, etc.
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*/
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this.trap(PDP11.TRAP.MMU, 0, PDP11.REASON.ABORT);
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this.trap(PDP11.TRAP.MMU, PDP11.OPFLAG.TRAP_MMU, PDP11.REASON.ABORT);
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}
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}
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if (!(this.regMMR0 & (PDP11.MMR0.ABORT | PDP11.MMR0.TRAP_MMU))) {
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@ -360,9 +360,10 @@ var PDP11 = {
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RW1: 0x4, // read/write, memory management trap upon completion of a read or write
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RW2: 0x5, // read/write, memory management trap upon completion of a write (11/70 only)
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RW: 0x6, // read/write, no system trap/abort action
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U2: 0x7 // unused, abort all accesses--reserved for future use
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U2: 0x7, // unused, abort all accesses--reserved for future use
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MASK: 0x7
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},
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ED: 0x0080, // expansion direction (if set, the page expands downward from block number 127)
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ED: 0x0008, // expansion direction (if set, the page expands downward from block number 127)
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UNUSED: 0x0030,
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MODIFIED: 0x0040, // page has been written (bit cleared when either PDR or PAR is written)
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ACCESSED: 0x0080, // page has been accessed (bit cleared when either PDR or PAR is written) (11/70 only)
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