1dd8cf1e81
Add IDE reset to port 0xcf9. Reset IDE error register on reset of non-existent devices. Fixes IDE related issues on soft reset for ASUS boards.
220 lines
8.5 KiB
C
220 lines
8.5 KiB
C
/*PRD format :
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word 0 - base address
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word 1 - bits 1 - 15 = byte count, bit 31 = end of transfer
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*/
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#include <string.h>
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#include "ibm.h"
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#include "ide.h"
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#include "ide_sff8038i.h"
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#include "keyboard_at.h"
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#include "io.h"
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#include "mem.h"
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#include "pci.h"
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#include "pic.h"
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#include "piix.h"
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static uint8_t card_piix[256], card_piix_ide[256];
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static sff_busmaster_t piix_busmaster[2];
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static uint8_t piix_rc = 0;
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static void (*piix_nb_reset)();
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void piix_write(int func, int addr, uint8_t val, void *priv)
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{
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// pclog("piix_write: func=%d addr=%02x val=%02x %04x:%08x\n", func, addr, val, CS, pc);
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if (func > 1)
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return;
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if (func == 1) /*IDE*/
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{
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switch (addr)
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{
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case 0x04:
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card_piix_ide[0x04] = (card_piix_ide[0x04] & ~5) | (val & 5);
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break;
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case 0x07:
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card_piix_ide[0x07] = (card_piix_ide[0x07] & ~0x38) | (val & 0x38);
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break;
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case 0x0d:
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card_piix_ide[0x0d] = val;
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break;
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case 0x20:
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card_piix_ide[0x20] = (val & ~0x0f) | 1;
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break;
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case 0x21:
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card_piix_ide[0x21] = val;
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break;
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case 0x40:
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card_piix_ide[0x40] = val;
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break;
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case 0x41:
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card_piix_ide[0x41] = val;
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break;
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case 0x42:
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card_piix_ide[0x42] = val;
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break;
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case 0x43:
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card_piix_ide[0x43] = val;
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break;
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}
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if (addr == 4 || (addr & ~3) == 0x20) /*Bus master base address*/
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{
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uint16_t base = (card_piix_ide[0x20] & 0xf0) | (card_piix_ide[0x21] << 8);
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io_removehandler(0, 0x10000, sff_bus_master_read, NULL, NULL, sff_bus_master_write, NULL, NULL, piix_busmaster);
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if (card_piix_ide[0x04] & 1)
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io_sethandler(base, 0x10, sff_bus_master_read, NULL, NULL, sff_bus_master_write, NULL, NULL, piix_busmaster);
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}
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if (addr == 4 || addr == 0x41 || addr == 0x43)
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{
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ide_pri_disable();
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ide_sec_disable();
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if (card_piix_ide[0x04] & 1)
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{
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if (card_piix_ide[0x41] & 0x80)
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ide_pri_enable();
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if (card_piix_ide[0x43] & 0x80)
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ide_sec_enable();
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}
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}
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// pclog("PIIX write %02X %02X\n", addr, val);
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}
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else
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{
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if (addr >= 0x0f && addr < 0x4c)
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return;
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switch (addr)
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{
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case 0x00: case 0x01: case 0x02: case 0x03:
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case 0x08: case 0x09: case 0x0a: case 0x0b:
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case 0x0e:
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return;
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case 0x60:
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// pclog("IRQ routing %02x %02x\n", addr, val);
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if (val & 0x80)
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pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
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else
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pci_set_irq_routing(PCI_INTA, val & 0xf);
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break;
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case 0x61:
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// pclog("IRQ routing %02x %02x\n", addr, val);
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if (val & 0x80)
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pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
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else
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pci_set_irq_routing(PCI_INTB, val & 0xf);
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break;
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case 0x62:
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// pclog("IRQ routing %02x %02x\n", addr, val);
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if (val & 0x80)
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pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
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else
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pci_set_irq_routing(PCI_INTC, val & 0xf);
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break;
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case 0x63:
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// pclog("IRQ routing %02x %02x\n", addr, val);
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if (val & 0x80)
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pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
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else
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pci_set_irq_routing(PCI_INTD, val & 0xf);
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break;
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}
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card_piix[addr] = val;
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}
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}
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uint8_t piix_read(int func, int addr, void *priv)
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{
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// pclog("piix_read: func=%d addr=%02x %04x:%08x\n", func, addr, CS, pc);
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if (func > 1)
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return 0xff;
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if (func == 1) /*IDE*/
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{
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// pclog("PIIX IDE read %02X %02X\n", addr, card_piix_ide[addr]);
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return card_piix_ide[addr];
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}
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else
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return card_piix[addr];
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}
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uint8_t piix_rc_read(uint16_t port, void *p)
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{
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return piix_rc;
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}
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void piix_rc_write(uint16_t port, uint8_t val, void *p)
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{
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if (val & 4)
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{
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if (val & 2) /*Hard reset*/
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{
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piix_nb_reset();
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keyboard_at_reset(); /*Reset keyboard controller to reset system flag*/
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ide_reset_devices();
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}
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resetx86();
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}
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piix_rc = val & ~4;
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}
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void piix_init(int card, int pci_a, int pci_b, int pci_c, int pci_d, void (*nb_reset)())
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{
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pci_add_specific(card, piix_read, piix_write, NULL);
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memset(card_piix, 0, 256);
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card_piix[0x00] = 0x86; card_piix[0x01] = 0x80; /*Intel*/
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card_piix[0x02] = 0x2e; card_piix[0x03] = 0x12; /*82371FB (PIIX)*/
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card_piix[0x04] = 0x07; card_piix[0x05] = 0x00;
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card_piix[0x06] = 0x80; card_piix[0x07] = 0x02;
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card_piix[0x08] = 0x00; /*A0 stepping*/
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card_piix[0x09] = 0x00; card_piix[0x0a] = 0x01; card_piix[0x0b] = 0x06;
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card_piix[0x0e] = 0x80; /*Multi-function device*/
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card_piix[0x4c] = 0x4d;
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card_piix[0x4e] = 0x03;
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card_piix[0x60] = card_piix[0x61] = card_piix[0x62] = card_piix[0x63] = 0x80;
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card_piix[0x69] = 0x02;
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card_piix[0x70] = card_piix[0x71] = 0x80;
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card_piix[0x76] = card_piix[0x77] = 0x0c;
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card_piix[0x78] = 0x02; card_piix[0x79] = 0x00;
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card_piix[0xa0] = 0x08;
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card_piix[0xa2] = card_piix[0xa3] = 0x00;
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card_piix[0xa4] = card_piix[0xa5] = card_piix[0xa6] = card_piix[0xa7] = 0x00;
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card_piix[0xa8] = 0x0f;
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card_piix[0xaa] = card_piix[0xab] = 0x00;
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card_piix[0xac] = 0x00;
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card_piix[0xae] = 0x00;
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card_piix_ide[0x00] = 0x86; card_piix_ide[0x01] = 0x80; /*Intel*/
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card_piix_ide[0x02] = 0x30; card_piix_ide[0x03] = 0x12; /*82371FB (PIIX)*/
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card_piix_ide[0x04] = 0x02; card_piix_ide[0x05] = 0x00;
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card_piix_ide[0x06] = 0x80; card_piix_ide[0x07] = 0x02;
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card_piix_ide[0x08] = 0x00;
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card_piix_ide[0x09] = 0x80; card_piix_ide[0x0a] = 0x01; card_piix_ide[0x0b] = 0x01;
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card_piix_ide[0x0d] = 0x00;
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card_piix_ide[0x0e] = 0x00;
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card_piix_ide[0x20] = 0x01; card_piix_ide[0x21] = card_piix_ide[0x22] = card_piix_ide[0x23] = 0x00; /*Bus master interface base address*/
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card_piix_ide[0x40] = card_piix_ide[0x41] = 0x00;
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card_piix_ide[0x42] = card_piix_ide[0x43] = 0x00;
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sff_bus_master_init(piix_busmaster);
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pci_set_card_routing(pci_a, PCI_INTA);
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pci_set_card_routing(pci_b, PCI_INTB);
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pci_set_card_routing(pci_c, PCI_INTC);
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pci_set_card_routing(pci_d, PCI_INTD);
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ide_pri_disable();
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ide_sec_disable();
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pic_init_elcrx();
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io_sethandler(0x0cf9, 0x0001, piix_rc_read, NULL, NULL, piix_rc_write, NULL, NULL, NULL);
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piix_nb_reset = nb_reset;
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}
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