389 lines
13 KiB
C
389 lines
13 KiB
C
#ifdef __ARM_EABI__
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#include <stdlib.h>
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#include "ibm.h"
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#include "codegen.h"
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#include "codegen_backend.h"
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#include "codegen_backend_arm_defs.h"
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#include "codegen_backend_arm_ops.h"
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#include "codegen_reg.h"
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#include "x86.h"
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#include "x87.h"
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#if defined(__linux__) || defined(__APPLE__)
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#include <sys/mman.h>
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#include <unistd.h>
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#endif
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#if defined WIN32 || defined _WIN32 || defined _WIN32
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#include <windows.h>
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#endif
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void *codegen_mem_load_byte;
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void *codegen_mem_load_word;
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void *codegen_mem_load_long;
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void *codegen_mem_load_quad;
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void *codegen_mem_load_single;
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void *codegen_mem_load_double;
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void *codegen_mem_store_byte;
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void *codegen_mem_store_word;
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void *codegen_mem_store_long;
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void *codegen_mem_store_quad;
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void *codegen_mem_store_single;
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void *codegen_mem_store_double;
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void *codegen_fp_round;
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int codegen_host_reg_list[CODEGEN_HOST_REGS] =
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{
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REG_R4,
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REG_R5,
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REG_R6,
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REG_R7,
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REG_R8,
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REG_R9,
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REG_R11,
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};
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int codegen_host_fp_reg_list[CODEGEN_HOST_FP_REGS] =
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{
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REG_D8,
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REG_D9,
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REG_D10,
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REG_D11,
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REG_D12,
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REG_D13,
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REG_D14,
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REG_D15
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};
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static void build_load_routine(codeblock_t *block, int size, int is_float)
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{
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uint32_t *branch_offset;
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uint32_t *misaligned_offset;
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/*In - R0 = address
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Out - R0 = data, R1 = abrt*/
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/*MOV R1, R0, LSR #12
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MOV R2, #readlookup2
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LDR R1, [R2, R1, LSL #2]
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CMP R1, #-1
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BNE +
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LDRB R0, [R1, R0]
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MOV R1, #0
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MOV PC, LR
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* STR LR, [SP, -4]!
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BL readmemb386l
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LDRB R1, cpu_state.abrt
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LDR PC, [SP], #4
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*/
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host_arm_MOV_REG_LSR(block, REG_R1, REG_R0, 12);
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host_arm_MOV_IMM(block, REG_R2, (uint32_t)readlookup2);
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host_arm_LDR_REG_LSL(block, REG_R1, REG_R2, REG_R1, 2);
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if (size != 1)
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{
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host_arm_TST_IMM(block, REG_R0, size-1);
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misaligned_offset = host_arm_BNE_(block);
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}
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host_arm_CMP_IMM(block, REG_R1, -1);
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branch_offset = host_arm_BEQ_(block);
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if (size == 1 && !is_float)
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host_arm_LDRB_REG(block, REG_R0, REG_R1, REG_R0);
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else if (size == 2 && !is_float)
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host_arm_LDRH_REG(block, REG_R0, REG_R1, REG_R0);
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else if (size == 4 && !is_float)
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host_arm_LDR_REG(block, REG_R0, REG_R1, REG_R0);
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else if (size == 4 && is_float)
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{
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host_arm_ADD_REG(block, REG_R0, REG_R0, REG_R1);
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host_arm_VLDR_S(block, REG_D_TEMP, REG_R0, 0);
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}
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else if (size == 8)
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{
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host_arm_ADD_REG(block, REG_R0, REG_R0, REG_R1);
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host_arm_VLDR_D(block, REG_D_TEMP, REG_R0, 0);
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}
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host_arm_MOV_IMM(block, REG_R1, 0);
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host_arm_MOV_REG(block, REG_PC, REG_LR);
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*branch_offset |= ((((uintptr_t)&block->data[block_pos] - (uintptr_t)branch_offset) - 8) & 0x3fffffc) >> 2;
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if (size != 1)
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*misaligned_offset |= ((((uintptr_t)&block->data[block_pos] - (uintptr_t)misaligned_offset) - 8) & 0x3fffffc) >> 2;
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host_arm_STR_IMM_WB(block, REG_LR, REG_HOST_SP, -4);
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if (size == 1)
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host_arm_BL(block, (uintptr_t)readmemb386l);
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else if (size == 2)
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host_arm_BL(block, (uintptr_t)readmemwl);
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else if (size == 4)
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host_arm_BL(block, (uintptr_t)readmemll);
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else if (size == 8)
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host_arm_BL(block, (uintptr_t)readmemql);
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else
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fatal("build_load_routine - unknown size %i\n", size);
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if (size == 4 && is_float)
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host_arm_VMOV_S_32(block, REG_D_TEMP, REG_R0);
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else if (size == 8)
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host_arm_VMOV_D_64(block, REG_D_TEMP, REG_R0, REG_R1);
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host_arm_LDRB_ABS(block, REG_R1, &cpu_state.abrt);
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host_arm_LDR_IMM_POST(block, REG_PC, REG_HOST_SP, 4);
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block_pos = (block_pos + 63) & ~63;
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}
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static void build_store_routine(codeblock_t *block, int size, int is_float)
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{
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uint32_t *branch_offset;
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uint32_t *misaligned_offset;
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/*In - R0 = address
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Out - R0 = data, R1 = abrt*/
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/*MOV R1, R0, LSR #12
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MOV R2, #readlookup2
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LDR R1, [R2, R1, LSL #2]
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CMP R1, #-1
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BNE +
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LDRB R0, [R1, R0]
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MOV R1, #0
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MOV PC, LR
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* STR LR, [SP, -4]!
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BL readmemb386l
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LDRB R1, cpu_state.abrt
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LDR PC, [SP], #4
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*/
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host_arm_MOV_REG_LSR(block, REG_R2, REG_R0, 12);
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host_arm_MOV_IMM(block, REG_R3, (uint32_t)writelookup2);
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host_arm_LDR_REG_LSL(block, REG_R2, REG_R3, REG_R2, 2);
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if (size != 1)
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{
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host_arm_TST_IMM(block, REG_R0, size-1);
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misaligned_offset = host_arm_BNE_(block);
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}
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host_arm_CMP_IMM(block, REG_R2, -1);
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branch_offset = host_arm_BEQ_(block);
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if (size == 1 && !is_float)
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host_arm_STRB_REG(block, REG_R1, REG_R2, REG_R0);
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else if (size == 2 && !is_float)
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host_arm_STRH_REG(block, REG_R1, REG_R2, REG_R0);
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else if (size == 4 && !is_float)
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host_arm_STR_REG(block, REG_R1, REG_R2, REG_R0);
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else if (size == 4 && is_float)
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{
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host_arm_ADD_REG(block, REG_R0, REG_R0, REG_R2);
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host_arm_VSTR_S(block, REG_D_TEMP, REG_R0, 0);
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}
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else if (size == 8)
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{
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host_arm_ADD_REG(block, REG_R0, REG_R0, REG_R2);
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host_arm_VSTR_D(block, REG_D_TEMP, REG_R0, 0);
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}
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host_arm_MOV_IMM(block, REG_R1, 0);
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host_arm_MOV_REG(block, REG_PC, REG_LR);
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*branch_offset |= ((((uintptr_t)&block->data[block_pos] - (uintptr_t)branch_offset) - 8) & 0x3fffffc) >> 2;
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if (size != 1)
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*misaligned_offset |= ((((uintptr_t)&block->data[block_pos] - (uintptr_t)misaligned_offset) - 8) & 0x3fffffc) >> 2;
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host_arm_STR_IMM_WB(block, REG_LR, REG_HOST_SP, -4);
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if (size == 4 && is_float)
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host_arm_VMOV_32_S(block, REG_R1, REG_D_TEMP);
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else if (size == 8)
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host_arm_VMOV_64_D(block, REG_R2, REG_R3, REG_D_TEMP);
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if (size == 1)
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host_arm_BL(block, (uintptr_t)writememb386l);
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else if (size == 2)
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host_arm_BL(block, (uintptr_t)writememwl);
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else if (size == 4)
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host_arm_BL(block, (uintptr_t)writememll);
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else if (size == 8)
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host_arm_BL_r1(block, (uintptr_t)writememql);
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else
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fatal("build_store_routine - unknown size %i\n", size);
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host_arm_LDRB_ABS(block, REG_R1, &cpu_state.abrt);
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host_arm_LDR_IMM_POST(block, REG_PC, REG_HOST_SP, 4);
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block_pos = (block_pos + 63) & ~63;
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}
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static void build_loadstore_routines(codeblock_t *block)
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{
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codegen_mem_load_byte = &codeblock[block_current].data[block_pos];
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build_load_routine(block, 1, 0);
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codegen_mem_load_word = &codeblock[block_current].data[block_pos];
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build_load_routine(block, 2, 0);
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codegen_mem_load_long = &codeblock[block_current].data[block_pos];
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build_load_routine(block, 4, 0);
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codegen_mem_load_quad = &codeblock[block_current].data[block_pos];
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build_load_routine(block, 8, 0);
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codegen_mem_load_single = &codeblock[block_current].data[block_pos];
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build_load_routine(block, 4, 1);
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codegen_mem_load_double = &codeblock[block_current].data[block_pos];
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build_load_routine(block, 8, 1);
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codegen_mem_store_byte = &codeblock[block_current].data[block_pos];
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build_store_routine(block, 1, 0);
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codegen_mem_store_word = &codeblock[block_current].data[block_pos];
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build_store_routine(block, 2, 0);
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codegen_mem_store_long = &codeblock[block_current].data[block_pos];
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build_store_routine(block, 4, 0);
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codegen_mem_store_quad = &codeblock[block_current].data[block_pos];
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build_store_routine(block, 8, 0);
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codegen_mem_store_single = &codeblock[block_current].data[block_pos];
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build_store_routine(block, 4, 1);
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codegen_mem_store_double = &codeblock[block_current].data[block_pos];
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build_store_routine(block, 8, 1);
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}
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/*VFP has a specific round-to-zero instruction, and the default rounding mode
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is nearest. For round up/down, temporarily change the rounding mode in FPCSR*/
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#define FPCSR_ROUNDING_MASK (3 << 22)
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#define FPCSR_ROUNDING_UP (1 << 22)
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#define FPCSR_ROUNDING_DOWN (2 << 22)
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static void build_fp_round_routine(codeblock_t *block)
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{
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uint32_t *jump_table;
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host_arm_MOV_REG(block, REG_TEMP2, REG_LR);
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host_arm_MOV_REG(block, REG_LR, REG_TEMP2);
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host_arm_LDR_IMM(block, REG_TEMP, REG_CPUSTATE, (uintptr_t)&cpu_state.new_fp_control - (uintptr_t)&cpu_state);
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host_arm_LDR_REG(block, REG_PC, REG_PC, REG_TEMP);
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addlong(0);
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jump_table = (uint32_t *)&block->data[block_pos];
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addlong(0);
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addlong(0);
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addlong(0);
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addlong(0);
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jump_table[X87_ROUNDING_NEAREST] = (uint64_t)(uintptr_t)&block->data[block_pos]; //tie even
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host_arm_VCVTR_IS_D(block, REG_D_TEMP, REG_D_TEMP);
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host_arm_MOV_REG(block, REG_PC, REG_LR);
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jump_table[X87_ROUNDING_UP] = (uint64_t)(uintptr_t)&block->data[block_pos]; //pos inf
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host_arm_LDR_IMM(block, REG_TEMP, REG_CPUSTATE, (uintptr_t)&cpu_state.old_fp_control - (uintptr_t)&cpu_state);
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host_arm_BIC_IMM(block, REG_TEMP2, REG_TEMP, FPCSR_ROUNDING_MASK);
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host_arm_ORR_IMM(block, REG_TEMP2, REG_TEMP2, FPCSR_ROUNDING_UP);
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host_arm_VMSR_FPSCR(block, REG_TEMP2);
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host_arm_VCVTR_IS_D(block, REG_D_TEMP, REG_D_TEMP);
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host_arm_VMSR_FPSCR(block, REG_TEMP);
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host_arm_MOV_REG(block, REG_PC, REG_LR);
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jump_table[X87_ROUNDING_DOWN] = (uint64_t)(uintptr_t)&block->data[block_pos]; //neg inf
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host_arm_LDR_IMM(block, REG_TEMP, REG_CPUSTATE, (uintptr_t)&cpu_state.old_fp_control - (uintptr_t)&cpu_state);
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host_arm_BIC_IMM(block, REG_TEMP2, REG_TEMP, FPCSR_ROUNDING_MASK);
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host_arm_ORR_IMM(block, REG_TEMP2, REG_TEMP, FPCSR_ROUNDING_DOWN);
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host_arm_VMSR_FPSCR(block, REG_TEMP2);
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host_arm_VCVTR_IS_D(block, REG_D_TEMP, REG_D_TEMP);
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host_arm_VMSR_FPSCR(block, REG_TEMP);
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host_arm_MOV_REG(block, REG_PC, REG_LR);
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jump_table[X87_ROUNDING_CHOP] = (uint64_t)(uintptr_t)&block->data[block_pos]; //zero
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host_arm_VCVT_IS_D(block, REG_D_TEMP, REG_D_TEMP);
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host_arm_MOV_REG(block, REG_PC, REG_LR);
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block_pos = (block_pos + 63) & ~63;
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}
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void codegen_backend_init()
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{
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int c;
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#if defined(__linux__) || defined(__APPLE__)
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void *start;
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size_t len;
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long pagesize = sysconf(_SC_PAGESIZE);
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long pagemask = ~(pagesize - 1);
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#endif
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#if defined WIN32 || defined _WIN32 || defined _WIN32
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codeblock_data = VirtualAlloc(NULL, (BLOCK_SIZE+1) * BLOCK_DATA_SIZE, MEM_COMMIT, PAGE_EXECUTE_READWRITE);
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#else
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codeblock_data = malloc((BLOCK_SIZE+1) * BLOCK_DATA_SIZE);
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#endif
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if (!codeblock_data)
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fatal("codeblock_data failed to alloc - %i\n", (BLOCK_SIZE+1) * BLOCK_DATA_SIZE);
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codeblock = malloc((BLOCK_SIZE+1) * sizeof(codeblock_t));
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codeblock_hash = malloc(HASH_SIZE * sizeof(codeblock_t *));
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memset(codeblock, 0, (BLOCK_SIZE+1) * sizeof(codeblock_t));
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memset(codeblock_hash, 0, HASH_SIZE * sizeof(codeblock_t *));
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for (c = 0; c < BLOCK_SIZE+1; c++)
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{
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codeblock[c].pc = BLOCK_PC_INVALID;
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codeblock[c].data = &codeblock_data[c * BLOCK_DATA_SIZE];
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}
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#if defined(__linux__) || defined(__APPLE__)
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start = (void *)((long)codeblock_data & pagemask);
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len = (((BLOCK_SIZE+1) * BLOCK_DATA_SIZE) + pagesize) & pagemask;
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if (mprotect(start, len, PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
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{
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perror("mprotect");
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exit(-1);
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}
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#endif
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// pclog("Codegen is %p\n", (void *)pages[0xfab12 >> 12].block);
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block_current = BLOCK_SIZE;
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block_pos = 0;
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build_loadstore_routines(&codeblock[block_current]);
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codegen_fp_round = &codeblock[block_current].data[block_pos];
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build_fp_round_routine(&codeblock[block_current]);
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asm("vmrs %0, fpscr\n"
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: "=r" (cpu_state.old_fp_control)
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);
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if ((cpu_state.old_fp_control >> 22) & 3)
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fatal("VFP not in nearest rounding mode\n");
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}
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void codegen_set_rounding_mode(int mode)
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{
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if (mode < 0 || mode > 3)
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fatal("codegen_set_rounding_mode - invalid mode\n");
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cpu_state.new_fp_control = mode << 2;
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}
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/*R10 - cpu_state*/
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void codegen_backend_prologue(codeblock_t *block)
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{
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block_pos = 0;
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block_pos = BLOCK_GPF_OFFSET;
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host_arm_MOV_IMM(block, REG_R0, 0);
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host_arm_MOV_IMM(block, REG_R1, 0);
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host_arm_call(block, x86gpf);
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while (block_pos != BLOCK_EXIT_OFFSET)
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host_arm_nop(block);
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block_pos = BLOCK_EXIT_OFFSET; /*Exit code*/
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host_arm_ADD_IMM(block, REG_HOST_SP, REG_HOST_SP, 0x40);
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host_arm_LDMIA_WB(block, REG_HOST_SP, REG_MASK_LOCAL | REG_MASK_PC);
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while (block_pos != BLOCK_START)
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host_arm_nop(block);
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/*Entry code*/
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host_arm_STMDB_WB(block, REG_HOST_SP, REG_MASK_LOCAL | REG_MASK_LR);
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host_arm_SUB_IMM(block, REG_HOST_SP, REG_HOST_SP, 0x40);
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host_arm_MOV_IMM(block, REG_CPUSTATE, (uint32_t)&cpu_state);
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if (block->flags & CODEBLOCK_HAS_FPU)
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{
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host_arm_LDR_IMM(block, REG_TEMP, REG_CPUSTATE, (uintptr_t)&cpu_state.TOP - (uintptr_t)&cpu_state);
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host_arm_SUB_IMM(block, REG_TEMP, REG_TEMP, block->TOP);
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host_arm_STR_IMM(block, REG_TEMP, REG_HOST_SP, IREG_TOP_diff_stack_offset);
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}
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}
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void codegen_backend_epilogue(codeblock_t *block)
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{
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host_arm_ADD_IMM(block, REG_HOST_SP, REG_HOST_SP, 0x40);
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host_arm_LDMIA_WB(block, REG_HOST_SP, REG_MASK_LOCAL | REG_MASK_PC);
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if (block_pos > ARM_LITERAL_POOL_OFFSET)
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fatal("Over limit!\n");
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__clear_cache(&block->data[0], &block->data[block_pos]);
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}
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#endif
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