f3607c2308
- FCOM/FUCOM - FSUBR/FSUBRP/FDIVR/FDIVRP - FLDCW/FSTCW - FILD/FIST/FISTP (16-bit, 32-bit and 64-bit variants) - FLD/FST/FSTP double precision - Integer and double precision variants of FADD/FSUB/FMUL/FDIV Also added 64-bit readmemq/writememq functions.
159 lines
3.7 KiB
C
159 lines
3.7 KiB
C
static int opMOVD_l_mm_a16(uint32_t fetchdat)
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{
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MMX_ENTER();
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fetch_ea_16(fetchdat);
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if (mod == 3)
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{
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MM[reg].l[0] = regs[rm].l;
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MM[reg].l[1] = 0;
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CLOCK_CYCLES(1);
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}
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else
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{
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uint32_t dst;
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dst = readmeml(easeg, eaaddr); if (abrt) return 1;
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MM[reg].l[0] = dst;
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MM[reg].l[1] = 0;
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CLOCK_CYCLES(2);
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}
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return 0;
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}
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static int opMOVD_l_mm_a32(uint32_t fetchdat)
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{
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MMX_ENTER();
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fetch_ea_32(fetchdat);
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if (mod == 3)
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{
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MM[reg].l[0] = regs[rm].l;
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MM[reg].l[1] = 0;
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CLOCK_CYCLES(1);
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}
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else
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{
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uint32_t dst;
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dst = readmeml(easeg, eaaddr); if (abrt) return 1;
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MM[reg].l[0] = dst;
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MM[reg].l[1] = 0;
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CLOCK_CYCLES(2);
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}
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return 0;
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}
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static int opMOVD_mm_l_a16(uint32_t fetchdat)
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{
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MMX_ENTER();
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fetch_ea_16(fetchdat);
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if (mod == 3)
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{
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regs[rm].l = MM[reg].l[0];
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CLOCK_CYCLES(1);
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}
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else
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{
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CHECK_WRITE(ea_seg, eaaddr, eaaddr + 3);
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writememl(easeg, eaaddr, MM[reg].l[0]); if (abrt) return 1;
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CLOCK_CYCLES(2);
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}
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return 0;
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}
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static int opMOVD_mm_l_a32(uint32_t fetchdat)
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{
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MMX_ENTER();
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fetch_ea_32(fetchdat);
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if (mod == 3)
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{
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regs[rm].l = MM[reg].l[0];
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CLOCK_CYCLES(1);
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}
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else
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{
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CHECK_WRITE(ea_seg, eaaddr, eaaddr + 3);
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writememl(easeg, eaaddr, MM[reg].l[0]); if (abrt) return 1;
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CLOCK_CYCLES(2);
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}
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return 0;
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}
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static int opMOVQ_q_mm_a16(uint32_t fetchdat)
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{
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MMX_ENTER();
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fetch_ea_16(fetchdat);
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if (mod == 3)
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{
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MM[reg].q = MM[rm].q;
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CLOCK_CYCLES(1);
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}
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else
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{
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uint64_t dst;
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dst = readmemq(easeg, eaaddr); if (abrt) return 1;
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MM[reg].q = dst;
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CLOCK_CYCLES(2);
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}
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return 0;
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}
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static int opMOVQ_q_mm_a32(uint32_t fetchdat)
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{
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MMX_ENTER();
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fetch_ea_32(fetchdat);
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if (mod == 3)
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{
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MM[reg].q = MM[rm].q;
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CLOCK_CYCLES(1);
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}
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else
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{
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uint64_t dst;
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dst = readmemq(easeg, eaaddr); if (abrt) return 1;
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MM[reg].q = dst;
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CLOCK_CYCLES(2);
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}
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return 0;
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}
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static int opMOVQ_mm_q_a16(uint32_t fetchdat)
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{
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MMX_ENTER();
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fetch_ea_16(fetchdat);
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if (mod == 3)
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{
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MM[rm].q = MM[reg].q;
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CLOCK_CYCLES(1);
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}
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else
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{
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CHECK_WRITE(ea_seg, eaaddr, eaaddr + 7);
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writememq(easeg, eaaddr, MM[reg].l[0]);
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}
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return 0;
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}
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static int opMOVQ_mm_q_a32(uint32_t fetchdat)
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{
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MMX_ENTER();
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fetch_ea_32(fetchdat);
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if (mod == 3)
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{
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MM[rm].q = MM[reg].q;
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CLOCK_CYCLES(1);
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}
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else
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{
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CHECK_WRITE(ea_seg, eaaddr, eaaddr + 7);
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writememq(easeg, eaaddr, MM[reg].q);
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}
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return 0;
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}
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